Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	413	1			T4	1		T47	3		T48	1
all_values[1]	468	1			T4	1		T47	2		T48	5
all_values[2]	451	1			T4	2		T47	2		T148	1
all_values[3]	502	1			T4	1		T48	3		T148	1
all_values[4]	450	1			T5	1		T47	1		T48	2
all_values[5]	468	1			T4	1		T48	1		T148	1
all_values[6]	501	1			T4	1		T5	1		T47	1
all_values[7]	536	1			T4	1		T5	1		T148	2
all_values[8]	482	1			T5	1		T47	3		T48	2
all_values[9]	456	1			T4	1		T5	1		T47	1
all_values[10]	442	1			T4	2		T47	2		T48	1
all_values[11]	509	1			T4	2		T47	1		T48	2
all_values[12]	484	1			T4	2		T5	1		T48	3
all_values[13]	480	1			T47	2		T48	3		T148	1
all_values[14]	503	1			T4	3		T47	4		T48	2
all_values[15]	522	1			T4	1		T47	2		T48	2
all_values[16]	479	1			T4	1		T47	1		T48	4
all_values[17]	435	1			T4	1		T5	1		T48	1
all_values[18]	448	1			T47	2		T48	1		T148	1
all_values[19]	439	1			T4	3		T5	1		T48	3
all_values[20]	459	1			T5	1		T47	2		T148	1
all_values[21]	454	1			T47	1		T48	2		T148	1
all_values[22]	490	1			T4	1		T5	1		T47	5
all_values[23]	489	1			T47	3		T142	4		T205	2
all_values[24]	463	1			T4	3		T47	3		T48	3
all_values[25]	470	1			T4	1		T5	2		T47	4
all_values[26]	507	1			T47	3		T148	1		T142	2
all_values[27]	443	1			T4	1		T5	1		T48	2
all_values[28]	496	1			T4	2		T5	1		T47	5
all_values[29]	437	1			T5	1		T48	2		T204	1
all_values[30]	489	1			T47	5		T48	3		T148	1
all_values[31]	448	1			T4	4		T48	2		T203	1
all_values[32]	503	1			T5	1		T47	1		T48	2
all_values[33]	457	1			T4	1		T5	1		T42	1
all_values[34]	485	1			T47	2		T48	2		T142	1
all_values[35]	452	1			T47	1		T148	2		T203	1
all_values[36]	465	1			T4	3		T47	1		T48	1
all_values[37]	477	1			T4	2		T47	4		T48	1
all_values[38]	485	1			T4	3		T47	3		T48	1
all_values[39]	525	1			T4	2		T5	1		T47	1
all_values[40]	473	1			T4	2		T5	1		T47	3
all_values[41]	486	1			T4	2		T47	1		T203	1
all_values[42]	475	1			T4	1		T47	3		T48	3
all_values[43]	497	1			T4	1		T47	2		T148	1
all_values[44]	461	1			T47	2		T148	2		T204	1
all_values[45]	495	1			T5	1		T47	3		T48	3
all_values[46]	495	1			T7	1		T4	2		T47	1
all_values[47]	472	1			T4	1		T47	3		T48	1
all_values[48]	489	1			T4	1		T47	2		T148	3
all_values[49]	466	1			T4	1		T47	3		T48	2