Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3565	1			T4	18		T5	4		T47	21
all_values[1]	3548	1			T4	23		T5	7		T59	2
all_values[2]	3621	1			T4	13		T5	6		T59	2
all_values[3]	3635	1			T4	17		T5	6		T59	2
all_values[4]	3561	1			T4	14		T5	4		T59	6
all_values[5]	3555	1			T4	24		T5	1		T59	4
all_values[6]	3568	1			T4	21		T5	3		T59	1
all_values[7]	3653	1			T4	17		T5	8		T59	1
all_values[8]	3505	1			T4	16		T5	3		T59	5
all_values[9]	3535	1			T4	15		T5	5		T59	2
all_values[10]	3585	1			T4	16		T5	9		T59	3
all_values[11]	3601	1			T4	15		T5	4		T59	2
all_values[12]	3584	1			T4	12		T5	1		T59	1
all_values[13]	3604	1			T4	13		T5	2		T59	1
all_values[14]	3542	1			T4	13		T5	4		T59	3
all_values[15]	3589	1			T4	9		T5	5		T59	5
all_values[16]	3605	1			T4	18		T5	4		T59	2
all_values[17]	3529	1			T4	13		T5	6		T59	2
all_values[18]	3578	1			T4	14		T5	8		T59	2
all_values[19]	3506	1			T4	17		T5	7		T59	4
all_values[20]	3668	1			T4	14		T5	3		T59	2
all_values[21]	3558	1			T4	19		T5	3		T47	18
all_values[22]	3567	1			T4	18		T5	5		T59	2
all_values[23]	3606	1			T4	19		T5	5		T59	2
all_values[24]	3588	1			T4	13		T5	3		T59	5
all_values[25]	3648	1			T4	15		T5	2		T59	1
all_values[26]	3603	1			T4	20		T5	7		T59	1
all_values[27]	3610	1			T4	13		T5	5		T59	3
all_values[28]	3559	1			T4	17		T5	5		T59	3
all_values[29]	3742	1			T4	22		T5	7		T59	2
all_values[30]	3637	1			T4	17		T5	2		T59	5
all_values[31]	3494	1			T4	24		T5	2		T59	5
all_values[32]	3553	1			T4	12		T5	6		T59	4
all_values[33]	3610	1			T4	19		T5	4		T59	2
all_values[34]	3464	1			T4	27		T5	4		T59	3
all_values[35]	3653	1			T4	21		T5	7		T59	1
all_values[36]	3577	1			T4	18		T5	8		T59	2
all_values[37]	3631	1			T4	25		T5	4		T59	2
all_values[38]	3638	1			T4	26		T5	5		T59	4
all_values[39]	3577	1			T4	15		T5	6		T47	12
all_values[40]	3606	1			T4	17		T5	3		T59	1
all_values[41]	3558	1			T4	17		T5	5		T59	3
all_values[42]	3560	1			T4	16		T5	3		T59	4
all_values[43]	3529	1			T4	20		T5	6		T59	2
all_values[44]	3679	1			T4	13		T5	3		T59	3
all_values[45]	3637	1			T4	16		T5	6		T59	2
all_values[46]	3603	1			T4	24		T5	4		T59	2
all_values[47]	3571	1			T4	18		T5	5		T59	4
all_values[48]	3585	1			T4	27		T5	4		T59	3
all_values[49]	3627	1			T4	19		T5	6		T59	1
all_values[50]	3563	1			T4	12		T5	5		T59	3
all_values[51]	3648	1			T4	19		T5	6		T59	4
all_values[52]	3542	1			T4	14		T5	6		T59	2
all_values[53]	3684	1			T4	17		T5	1		T59	3
all_values[54]	3480	1			T4	17		T5	8		T59	4
all_values[55]	3607	1			T4	15		T5	4		T47	16
all_values[56]	3628	1			T4	24		T5	5		T59	4
all_values[57]	3604	1			T4	18		T5	9		T59	3
all_values[58]	3610	1			T4	18		T5	8		T59	2
all_values[59]	3658	1			T4	10		T5	3		T59	5
all_values[60]	3564	1			T4	14		T5	9		T59	2
all_values[61]	3630	1			T4	16		T5	10		T59	1
all_values[62]	3622	1			T4	13		T5	3		T59	3
all_values[63]	3580	1			T4	13		T59	4		T47	16