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 LINE       31976
 SUB-EXPRESSION (addr_hit[132] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T83
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[133] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T61
1	1	Covered	T5,T46,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[134] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T83
1	1	Covered	T5,T60,T141

 LINE       31976
 SUB-EXPRESSION (addr_hit[135] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T42
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[136] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T148
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[137] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T89
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[138] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T42
1	1	Covered	T5,T59,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[139] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T5,T42,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[140] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T86
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[141] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T47
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[142] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T86,T47
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[143] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T4,T5,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[144] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T42
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[145] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T5,T6,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[146] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T59,T60,T47
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[147] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T82
1	1	Covered	T5,T42,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[148] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T42,T202
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[149] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T5,T61,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[150] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T82,T47,T48
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[151] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T42,T46
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[152] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T5,T6,T89

 LINE       31976
 SUB-EXPRESSION (addr_hit[153] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T89
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[154] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T82
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[155] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T5,T42,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[156] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T59
1	1	Covered	T5,T42,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[157] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T60,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[158] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T46,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[159] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[160] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[161] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T60
1	1	Covered	T5,T46,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[162] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T82
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[163] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T48
1	1	Covered	T42,T59,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[164] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T60
1	1	Covered	T5,T46,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[165] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[166] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T61
1	1	Covered	T5,T59,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[167] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T4,T5,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[168] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T42
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[169] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T46
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[170] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T5,T61,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[171] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T48
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[172] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T82
1	1	Covered	T46,T61,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[173] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T89
1	1	Covered	T5,T46,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[174] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T83,T47
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[175] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T148
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[176] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[177] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T46
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[178] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T82
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[179] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[180] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T60
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[181] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T42
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[182] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T58,T82
1	1	Covered	T5,T46,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[183] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T60
1	1	Covered	T5,T42,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[184] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T83,T47
1	1	Covered	T5,T46,T58

 LINE       31976
 SUB-EXPRESSION (addr_hit[185] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T89,T47
1	1	Covered	T59,T60,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[186] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T5,T6,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[187] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T5,T6,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[188] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T58,T148
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[189] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T82
1	1	Covered	T5,T42,T58

 LINE       31976
 SUB-EXPRESSION (addr_hit[190] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T48
1	1	Covered	T5,T42,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[191] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T61
1	1	Covered	T5,T6,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[192] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[193] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T83
1	1	Covered	T59,T60,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[194] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T82
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[195] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T47
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[196] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T46,T61
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[197] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T48
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[198] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T82
1	1	Covered	T6,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[199] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T60
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[200] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T60
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[201] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T89,T47
1	1	Covered	T4,T5,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[202] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T47
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[203] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T61
1	1	Covered	T5,T86,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[204] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T4,T5,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[205] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T82,T47
1	1	Covered	T5,T42,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[206] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T83,T47,T48
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[207] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T83
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[208] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T86
1	1	Covered	T5,T60,T86

 LINE       31976
 SUB-EXPRESSION (addr_hit[209] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T86
1	1	Covered	T4,T5,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[210] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T202
1	1	Covered	T42,T59,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[211] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[212] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T5,T42,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[213] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T60
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[214] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T82
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[215] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T5,T6,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[216] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T48
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[217] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T42
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[218] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T4,T5,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[219] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T61,T148
1	1	Covered	T5,T42,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[220] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T5,T59,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[221] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T60
1	1	Covered	T5,T6,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[222] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T86
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[223] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T48
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[224] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T82
1	1	Covered	T4,T5,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[225] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[226] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T48
1	1	Covered	T42,T59,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[227] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T42
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[228] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T83
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[229] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T4,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[230] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T42,T60
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[231] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[232] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T61,T47
1	1	Covered	T5,T59,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[233] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T5,T6,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[234] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T83
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[235] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T47
1	1	Covered	T5,T6,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[236] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[237] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T42,T46
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[238] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T82,T47
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[239] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T82
1	1	Covered	T5,T46,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[240] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T4,T5,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[241] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T83,T47
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[242] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[243] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T82
1	1	Covered	T42,T46,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[244] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T4,T5,T86

 LINE       31976
 SUB-EXPRESSION (addr_hit[245] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[246] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T46
1	1	Covered	T4,T5,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[247] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T61
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[248] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T83
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[249] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T82
1	1	Covered	T5,T59,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[250] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T47
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[251] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T61
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[252] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T83,T148
1	1	Covered	T5,T6,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[253] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T82,T83
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[254] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T83
1	1	Covered	T4,T46,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[255] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T4,T5,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[256] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T60,T148
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[257] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T204
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[258] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T48,T148
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[259] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T48,T148
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[260] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T203
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[261] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T48,T148
1	1	Covered	T5,T59,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[262] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T204,T1
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[263] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T61,T48
1	1	Covered	T6,T42,T59