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 LINE       31976
 SUB-EXPRESSION (addr_hit[264] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T148
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[265] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T48,T148
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[266] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T47
1	1	Covered	T5,T42,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[267] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T148,T204,T1
1	1	Covered	T42,T47,T48

 LINE       31976
 SUB-EXPRESSION (addr_hit[268] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T148
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[269] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T148
1	1	Covered	T5,T46,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[270] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T148,T84,T204
1	1	Covered	T5,T82,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[271] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T89,T148
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[272] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T148
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[273] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T47
1	1	Covered	T5,T42,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[274] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T47
1	1	Covered	T5,T60,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[275] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T148,T206
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[276] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T46,T60,T48
1	1	Covered	T5,T46,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[277] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T204
1	1	Covered	T42,T61,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[278] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T60
1	1	Covered	T5,T6,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[279] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T47,T148
1	1	Covered	T5,T82,T89

 LINE       31976
 SUB-EXPRESSION (addr_hit[280] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T59,T89,T148
1	1	Covered	T5,T82,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[281] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T148
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[282] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T46,T148,T204
1	1	Covered	T5,T59,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[283] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T83,T148,T203
1	1	Covered	T5,T6,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[284] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T89,T203
1	1	Covered	T5,T59,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[285] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T89,T148
1	1	Covered	T5,T42,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[286] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T59
1	1	Covered	T5,T46,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[287] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T82
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[288] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T148,T204,T1
1	1	Covered	T5,T46,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[289] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T59,T89
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[290] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T48,T148
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[291] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T59,T83,T148
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[292] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T148
1	1	Covered	T5,T46,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[293] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T203
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[294] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T82,T47,T148
1	1	Covered	T5,T59,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[295] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T1
1	1	Covered	T5,T82,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[296] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T42,T82
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[297] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T148
1	1	Covered	T5,T60,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[298] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T203,T204
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[299] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T203
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[300] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T148
1	1	Covered	T5,T42,T58

 LINE       31976
 SUB-EXPRESSION (addr_hit[301] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T61,T148
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[302] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T47
1	1	Covered	T42,T60,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[303] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T83,T47
1	1	Covered	T5,T42,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[304] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T42
1	1	Covered	T5,T61,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[305] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T60
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[306] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T4,T5,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[307] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T5,T46,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[308] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T47,T48,T148
1	1	Covered	T59,T83,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[309] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[310] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T148
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[311] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T5,T47,T48

 LINE       31976
 SUB-EXPRESSION (addr_hit[312] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T61,T148
1	1	Covered	T5,T42,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[313] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T83
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[314] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T47,T48
1	1	Covered	T4,T5,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[315] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T83
1	1	Covered	T4,T5,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[316] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T42
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[317] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T59,T47,T148
1	1	Covered	T5,T46,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[318] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T83
1	1	Covered	T5,T46,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[319] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T203
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[320] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T148
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[321] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T83
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[322] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T83
1	1	Covered	T5,T82,T141

 LINE       31976
 SUB-EXPRESSION (addr_hit[323] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T48
1	1	Covered	T59,T61,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[324] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T203
1	1	Covered	T5,T42,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[325] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T148,T203,T204
1	1	Covered	T5,T6,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[326] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T203
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[327] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T148
1	1	Covered	T42,T47,T48

 LINE       31976
 SUB-EXPRESSION (addr_hit[328] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T47,T148,T204
1	1	Covered	T5,T46,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[329] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T83,T148
1	1	Covered	T5,T42,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[330] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T61,T204
1	1	Covered	T5,T83,T89

 LINE       31976
 SUB-EXPRESSION (addr_hit[331] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T148
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[332] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T148,T203
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[333] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T59,T82,T148
1	1	Covered	T5,T6,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[334] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T42,T61
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[335] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T60,T48,T148
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[336] & ((|(4'b0011 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T5,T42,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[337] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T89
1	1	Covered	T5,T46,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[338] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T48
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[339] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T48
1	1	Covered	T5,T46,T89

 LINE       31976
 SUB-EXPRESSION (addr_hit[340] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T148
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[341] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T60
1	1	Covered	T5,T59,T148

 LINE       31976
 SUB-EXPRESSION (addr_hit[342] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T89
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[343] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T47
1	1	Covered	T42,T47,T148

 LINE       31976
 SUB-EXPRESSION (addr_hit[344] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T148
1	1	Covered	T5,T61,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[345] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T86
1	1	Covered	T5,T47,T48

 LINE       31976
 SUB-EXPRESSION (addr_hit[346] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T47
1	1	Covered	T5,T60,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[347] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T58
1	1	Covered	T6,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[348] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T47
1	1	Covered	T4,T5,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[349] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T83
1	1	Covered	T5,T42,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[350] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T82,T47
1	1	Covered	T46,T82,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[351] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T83
1	1	Covered	T5,T42,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[352] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T148,T204,T1
1	1	Covered	T5,T59,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[353] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T47
1	1	Covered	T46,T83,T148

 LINE       31976
 SUB-EXPRESSION (addr_hit[354] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T48
1	1	Covered	T4,T5,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[355] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T48
1	1	Covered	T5,T59,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[356] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T46,T148,T203
1	1	Covered	T5,T148,T204

 LINE       31976
 SUB-EXPRESSION (addr_hit[357] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T6,T42,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[358] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T47
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[359] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T203
1	1	Covered	T5,T59,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[360] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T42
1	1	Covered	T5,T42,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[361] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T148
1	1	Covered	T4,T59,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[362] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T5,T61,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[363] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[364] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T89,T148
1	1	Covered	T5,T6,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[365] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T89
1	1	Covered	T5,T46,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[366] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T148
1	1	Covered	T5,T59,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[367] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T86,T47
1	1	Covered	T5,T61,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[368] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T47,T48
1	1	Covered	T5,T61,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[369] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T60,T148
1	1	Covered	T5,T6,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[370] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T47
1	1	Covered	T5,T47,T48

 LINE       31976
 SUB-EXPRESSION (addr_hit[371] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T148
1	1	Covered	T59,T61,T86

 LINE       31976
 SUB-EXPRESSION (addr_hit[372] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T82
1	1	Covered	T46,T58,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[373] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T59
1	1	Covered	T42,T60,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[374] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T42,T148
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[375] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[376] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T6,T59,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[377] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T5,T46,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[378] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T59,T47
1	1	Covered	T42,T59,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[379] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T5,T60,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[380] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T48,T148
1	1	Covered	T5,T58,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[381] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T42,T60
1	1	Covered	T4,T60,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[382] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T89
1	1	Covered	T5,T6,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[383] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T86
1	1	Covered	T42,T83,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[384] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T48
1	1	Covered	T42,T82,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[385] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T47
1	1	Covered	T60,T89,T148

 LINE       31976
 SUB-EXPRESSION (addr_hit[386] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T59,T61
1	1	Covered	T5,T42,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[387] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T60
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[388] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T203,T204
1	1	Covered	T4,T5,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[389] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T89
1	1	Covered	T5,T42,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[390] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T82
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[391] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T58,T82
1	1	Covered	T5,T83,T89

 LINE       31976
 SUB-EXPRESSION (addr_hit[392] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T82
1	1	Covered	T4,T5,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[393] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T47
1	1	Covered	T5,T60,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[394] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T148
1	1	Covered	T5,T59,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[395] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T5,T42,T59