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 LINE       31976
 SUB-EXPRESSION (addr_hit[396] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T203
1	1	Covered	T42,T46,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[397] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T61
1	1	Covered	T5,T42,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[398] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T89,T47
1	1	Covered	T5,T42,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[399] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T60
1	1	Covered	T5,T59,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[400] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T47,T148
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[401] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T47
1	1	Covered	T5,T82,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[402] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T89,T204
1	1	Covered	T5,T42,T89

 LINE       31976
 SUB-EXPRESSION (addr_hit[403] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T47
1	1	Covered	T5,T42,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[404] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T42,T148
1	1	Covered	T5,T82,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[405] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T48,T148
1	1	Covered	T5,T6,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[406] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T83,T48
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[407] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T61
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[408] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T82,T83
1	1	Covered	T5,T42,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[409] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T61,T47
1	1	Covered	T5,T59,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[410] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T59,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[411] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T61,T82
1	1	Covered	T6,T83,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[412] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[413] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T83,T47
1	1	Covered	T59,T83,T141

 LINE       31976
 SUB-EXPRESSION (addr_hit[414] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T203
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[415] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T203
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[416] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T48
1	1	Covered	T4,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[417] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T48
1	1	Covered	T5,T46,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[418] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T148,T203
1	1	Covered	T5,T58,T48

 LINE       31976
 SUB-EXPRESSION (addr_hit[419] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T58,T83
1	1	Covered	T5,T42,T58

 LINE       31976
 SUB-EXPRESSION (addr_hit[420] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T83,T48
1	1	Covered	T4,T5,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[421] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T48,T148
1	1	Covered	T42,T46,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[422] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T48
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[423] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T61,T83
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[424] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[425] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T82
1	1	Covered	T4,T83,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[426] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T60,T47
1	1	Covered	T42,T46,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[427] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T5,T61,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[428] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T148
1	1	Covered	T5,T47,T48

 LINE       31976
 SUB-EXPRESSION (addr_hit[429] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T148
1	1	Covered	T5,T46,T58

 LINE       31976
 SUB-EXPRESSION (addr_hit[430] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T58,T148
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[431] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T83,T89
1	1	Covered	T5,T42,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[432] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T61
1	1	Covered	T5,T42,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[433] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T48
1	1	Covered	T5,T59,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[434] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T89,T48
1	1	Covered	T5,T42,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[435] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T59
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[436] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T5,T42,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[437] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[438] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T47
1	1	Covered	T5,T46,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[439] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T4,T5,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[440] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T82
1	1	Covered	T4,T42,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[441] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T60
1	1	Covered	T4,T5,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[442] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T5,T47,T48

 LINE       31976
 SUB-EXPRESSION (addr_hit[443] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T82
1	1	Covered	T5,T46,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[444] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T60
1	1	Covered	T4,T5,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[445] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T47
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[446] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T48,T148,T203
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[447] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T89,T48,T148
1	1	Covered	T5,T48,T148

 LINE       31976
 SUB-EXPRESSION (addr_hit[448] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T48
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[449] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T47
1	1	Covered	T5,T6,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[450] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T58,T47
1	1	Covered	T5,T46,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[451] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T48,T148
1	1	Covered	T5,T46,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[452] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T48
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[453] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[454] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T5,T59,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[455] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T61
1	1	Covered	T5,T6,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[456] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T86
1	1	Covered	T60,T82,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[457] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T61
1	1	Covered	T5,T59,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[458] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T60
1	1	Covered	T5,T6,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[459] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T48
1	1	Covered	T5,T60,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[460] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T48,T203
1	1	Covered	T5,T46,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[461] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T83,T47,T203
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[462] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[463] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T5,T42,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[464] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T83,T48,T148
1	1	Covered	T5,T61,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[465] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T48
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[466] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T47,T48
1	1	Covered	T4,T46,T86

 LINE       31976
 SUB-EXPRESSION (addr_hit[467] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T86
1	1	Covered	T5,T60,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[468] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T48
1	1	Covered	T5,T82,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[469] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T47
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[470] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T42,T60
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[471] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T148
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[472] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T47
1	1	Covered	T5,T42,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[473] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T148
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[474] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T86
1	1	Covered	T5,T86,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[475] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T82
1	1	Covered	T5,T60,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[476] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T59,T148
1	1	Covered	T5,T61,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[477] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T59,T47
1	1	Covered	T5,T42,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[478] & ((|(4'b0011 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T4,T5,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[479] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T83,T47,T148
1	1	Covered	T4,T5,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[480] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T5,T59,T86

 LINE       31976
 SUB-EXPRESSION (addr_hit[481] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T83
1	1	Covered	T59,T82,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[482] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T89,T47,T48
1	1	Covered	T5,T42,T48

 LINE       31976
 SUB-EXPRESSION (addr_hit[483] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T83,T148
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[484] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T46
1	1	Covered	T5,T6,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[485] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T204
1	1	Covered	T6,T46,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[486] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T47
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[487] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T89
1	1	Covered	T4,T5,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[488] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T203
1	1	Covered	T5,T6,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[489] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T86,T141
1	1	Covered	T5,T86,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[490] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T5,T82,T48

 LINE       31976
 SUB-EXPRESSION (addr_hit[491] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T42,T46
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[492] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T47
1	1	Covered	T5,T42,T58

 LINE       31976
 SUB-EXPRESSION (addr_hit[493] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T58,T47
1	1	Covered	T5,T59,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[494] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T203
1	1	Covered	T5,T42,T89

 LINE       31976
 SUB-EXPRESSION (addr_hit[495] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T60,T47
1	1	Covered	T5,T6,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[496] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T48,T148
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[497] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T59,T60
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[498] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T59
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[499] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T86,T47
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[500] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T148,T204
1	1	Covered	T5,T82,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[501] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T46
1	1	Covered	T5,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[502] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T83
1	1	Covered	T5,T42,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[503] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T89
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[504] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T4,T5,T58

 LINE       31976
 SUB-EXPRESSION (addr_hit[505] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T82
1	1	Covered	T4,T5,T46

 LINE       31976
 SUB-EXPRESSION (addr_hit[506] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T47,T48
1	1	Covered	T42,T61,T82

 LINE       31976
 SUB-EXPRESSION (addr_hit[507] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T48
1	1	Covered	T5,T42,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[508] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T4,T5,T6

 LINE       31976
 SUB-EXPRESSION (addr_hit[509] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T47
1	1	Covered	T59,T83,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[510] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T1
1	1	Covered	T5,T47,T48

 LINE       31976
 SUB-EXPRESSION (addr_hit[511] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T60,T48
1	1	Covered	T42,T46,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[512] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T203
1	1	Covered	T5,T46,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[513] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T47,T48,T1
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[514] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T82,T47
1	1	Covered	T4,T82,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[515] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T47
1	1	Covered	T5,T60,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[516] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T47
1	1	Covered	T4,T6,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[517] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T46,T59
1	1	Covered	T5,T42,T86

 LINE       31976
 SUB-EXPRESSION (addr_hit[518] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T48,T203
1	1	Covered	T5,T60,T48

 LINE       31976
 SUB-EXPRESSION (addr_hit[519] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T47
1	1	Covered	T5,T6,T83

 LINE       31976
 SUB-EXPRESSION (addr_hit[520] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T6,T46,T148
1	1	Covered	T5,T46,T60

 LINE       31976
 SUB-EXPRESSION (addr_hit[521] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T46
1	1	Covered	T5,T46,T59

 LINE       31976
 SUB-EXPRESSION (addr_hit[522] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T42
1	1	Covered	T4,T5,T42

 LINE       31976
 SUB-EXPRESSION (addr_hit[523] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T60
1	1	Covered	T82,T86,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[524] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T148,T204,T1
1	1	Covered	T5,T82,T86

 LINE       31976
 SUB-EXPRESSION (addr_hit[525] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T148,T84,T206
1	1	Covered	T5,T83,T48

 LINE       31976
 SUB-EXPRESSION (addr_hit[526] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T148,T203
1	1	Covered	T58,T89,T47

 LINE       31976
 SUB-EXPRESSION (addr_hit[527] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T148,T204
1	1	Covered	T5,T60,T47