Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
85.67 85.42 86.01 69.87 86.69 87.22 98.79


Total test records in report: 1922
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T1756 /workspace/coverage/cover_reg_top/53.xbar_stress_all.3562267580 Jan 03 02:10:22 PM PST 24 Jan 03 02:13:15 PM PST 24 1733681051 ps
T1757 /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.2788091722 Jan 03 02:08:58 PM PST 24 Jan 03 02:09:31 PM PST 24 379184599 ps
T1758 /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1963507966 Jan 03 02:11:03 PM PST 24 Jan 03 02:12:28 PM PST 24 4217594857 ps
T1759 /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.1169995941 Jan 03 02:09:10 PM PST 24 Jan 03 02:10:35 PM PST 24 4769696690 ps
T1760 /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.2133392096 Jan 03 02:10:52 PM PST 24 Jan 03 02:17:17 PM PST 24 2762376723 ps
T1761 /workspace/coverage/cover_reg_top/45.xbar_access_same_device.305873431 Jan 03 02:10:01 PM PST 24 Jan 03 02:10:35 PM PST 24 380844433 ps
T1762 /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.3401016813 Jan 03 02:07:37 PM PST 24 Jan 03 02:08:08 PM PST 24 455489754 ps
T1763 /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2118096518 Jan 03 02:11:31 PM PST 24 Jan 03 02:13:01 PM PST 24 175291222 ps
T1764 /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.869988463 Jan 03 02:09:33 PM PST 24 Jan 03 02:10:13 PM PST 24 355245993 ps
T1765 /workspace/coverage/cover_reg_top/2.xbar_access_same_device.2534112905 Jan 03 02:07:16 PM PST 24 Jan 03 02:08:00 PM PST 24 609980098 ps
T1766 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.356341193 Jan 03 02:08:18 PM PST 24 Jan 03 02:09:15 PM PST 24 1347783445 ps
T1767 /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.711118190 Jan 03 02:12:30 PM PST 24 Jan 03 02:25:28 PM PST 24 74754258622 ps
T1768 /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2191547049 Jan 03 02:10:11 PM PST 24 Jan 03 02:10:35 PM PST 24 52615377 ps
T1769 /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.4043841872 Jan 03 02:11:44 PM PST 24 Jan 03 02:13:04 PM PST 24 1924232601 ps
T1770 /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3694308504 Jan 03 02:07:22 PM PST 24 Jan 03 02:07:46 PM PST 24 93778749 ps
T1771 /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.2520762637 Jan 03 02:08:15 PM PST 24 Jan 03 02:09:24 PM PST 24 5680256936 ps
T1772 /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.603704203 Jan 03 02:11:19 PM PST 24 Jan 03 02:12:03 PM PST 24 723028074 ps
T1773 /workspace/coverage/cover_reg_top/27.xbar_smoke.432039059 Jan 03 02:09:39 PM PST 24 Jan 03 02:09:52 PM PST 24 40094008 ps
T1774 /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3412783690 Jan 03 02:12:59 PM PST 24 Jan 03 02:13:58 PM PST 24 1071891253 ps
T1775 /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2465344771 Jan 03 02:10:44 PM PST 24 Jan 03 02:12:47 PM PST 24 5816378073 ps
T1776 /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.3810175062 Jan 03 02:10:49 PM PST 24 Jan 03 02:16:47 PM PST 24 9865521393 ps
T1777 /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.1324922546 Jan 03 02:09:23 PM PST 24 Jan 03 02:09:45 PM PST 24 260350347 ps
T1778 /workspace/coverage/cover_reg_top/14.xbar_access_same_device.2374111151 Jan 03 02:07:36 PM PST 24 Jan 03 02:09:43 PM PST 24 2833687554 ps
T1779 /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3807969259 Jan 03 02:08:57 PM PST 24 Jan 03 02:09:14 PM PST 24 88668481 ps
T1780 /workspace/coverage/cover_reg_top/72.xbar_same_source.3243272546 Jan 03 02:11:57 PM PST 24 Jan 03 02:13:25 PM PST 24 2645163524 ps
T1781 /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1911298487 Jan 03 02:10:33 PM PST 24 Jan 03 02:12:31 PM PST 24 5986349099 ps
T1782 /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.188301097 Jan 03 02:07:36 PM PST 24 Jan 03 02:09:05 PM PST 24 1023991181 ps
T1783 /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.3965044840 Jan 03 02:11:37 PM PST 24 Jan 03 02:12:13 PM PST 24 289524709 ps
T1784 /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.1966990544 Jan 03 02:13:15 PM PST 24 Jan 03 02:15:04 PM PST 24 7905348261 ps
T1785 /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3271755412 Jan 03 02:13:01 PM PST 24 Jan 03 02:13:28 PM PST 24 117584704 ps
T1786 /workspace/coverage/cover_reg_top/34.xbar_random.3392903543 Jan 03 02:09:39 PM PST 24 Jan 03 02:10:48 PM PST 24 1646006208 ps
T1787 /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.262203470 Jan 03 02:08:53 PM PST 24 Jan 03 02:09:28 PM PST 24 729308122 ps
T1788 /workspace/coverage/cover_reg_top/38.xbar_stress_all.3317237820 Jan 03 02:10:39 PM PST 24 Jan 03 02:16:48 PM PST 24 11042309385 ps
T1789 /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.2556551269 Jan 03 02:12:38 PM PST 24 Jan 03 02:20:54 PM PST 24 42953909029 ps
T1790 /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.2423265567 Jan 03 02:09:21 PM PST 24 Jan 03 02:17:12 PM PST 24 41824565559 ps
T1791 /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2307356113 Jan 03 02:13:01 PM PST 24 Jan 03 02:23:02 PM PST 24 38923256922 ps
T1792 /workspace/coverage/cover_reg_top/97.xbar_access_same_device.3028756773 Jan 03 02:13:31 PM PST 24 Jan 03 02:14:09 PM PST 24 127748699 ps
T1793 /workspace/coverage/cover_reg_top/17.xbar_stress_all.437495674 Jan 03 02:07:31 PM PST 24 Jan 03 02:10:54 PM PST 24 5835920985 ps
T1794 /workspace/coverage/cover_reg_top/3.chip_csr_rw.3811531685 Jan 03 02:08:25 PM PST 24 Jan 03 02:16:19 PM PST 24 4894418575 ps
T1795 /workspace/coverage/cover_reg_top/86.xbar_random.4271133208 Jan 03 02:13:00 PM PST 24 Jan 03 02:14:03 PM PST 24 1303679990 ps
T1796 /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.269495431 Jan 03 02:09:14 PM PST 24 Jan 03 02:09:23 PM PST 24 39021481 ps
T1797 /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.2005076278 Jan 03 02:12:18 PM PST 24 Jan 03 02:18:12 PM PST 24 32023091302 ps
T1798 /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.3470085813 Jan 03 02:11:23 PM PST 24 Jan 03 02:24:05 PM PST 24 70121850817 ps
T254 /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.4057919327 Jan 03 02:09:36 PM PST 24 Jan 03 02:14:05 PM PST 24 7878072574 ps
T1799 /workspace/coverage/cover_reg_top/6.xbar_access_same_device.3925178319 Jan 03 02:07:33 PM PST 24 Jan 03 02:08:57 PM PST 24 1020560286 ps
T1800 /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.2267085175 Jan 03 02:11:00 PM PST 24 Jan 03 02:12:26 PM PST 24 1272813209 ps
T1801 /workspace/coverage/cover_reg_top/41.xbar_smoke.3916778712 Jan 03 02:09:49 PM PST 24 Jan 03 02:09:59 PM PST 24 52282106 ps
T1802 /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3773449670 Jan 03 02:07:21 PM PST 24 Jan 03 02:12:22 PM PST 24 8450560741 ps
T1803 /workspace/coverage/cover_reg_top/11.xbar_smoke.1821167557 Jan 03 02:08:22 PM PST 24 Jan 03 02:08:37 PM PST 24 133547254 ps
T1804 /workspace/coverage/cover_reg_top/68.xbar_access_same_device.181646391 Jan 03 02:11:36 PM PST 24 Jan 03 02:13:58 PM PST 24 3155615958 ps
T1805 /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.3470854222 Jan 03 02:09:56 PM PST 24 Jan 03 02:17:35 PM PST 24 4970641593 ps
T1806 /workspace/coverage/cover_reg_top/41.xbar_random.594833683 Jan 03 02:10:01 PM PST 24 Jan 03 02:10:29 PM PST 24 164515567 ps
T1807 /workspace/coverage/cover_reg_top/78.xbar_stress_all.2280739205 Jan 03 02:12:38 PM PST 24 Jan 03 02:19:16 PM PST 24 10839180765 ps
T1808 /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1229288181 Jan 03 02:12:30 PM PST 24 Jan 03 02:47:50 PM PST 24 124221462126 ps
T1809 /workspace/coverage/cover_reg_top/30.xbar_stress_all.2453182819 Jan 03 02:09:25 PM PST 24 Jan 03 02:09:43 PM PST 24 69539148 ps
T1810 /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1748364473 Jan 03 02:11:33 PM PST 24 Jan 03 02:11:49 PM PST 24 82753957 ps
T1811 /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2139231396 Jan 03 02:09:59 PM PST 24 Jan 03 02:10:12 PM PST 24 57961326 ps
T1812 /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.3601738124 Jan 03 02:09:59 PM PST 24 Jan 03 02:17:09 PM PST 24 25631315062 ps
T1813 /workspace/coverage/cover_reg_top/41.xbar_stress_all.3320543027 Jan 03 02:10:01 PM PST 24 Jan 03 02:16:18 PM PST 24 12224439093 ps
T1814 /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.147363068 Jan 03 02:11:43 PM PST 24 Jan 03 02:21:07 PM PST 24 53982013400 ps
T1815 /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.831764147 Jan 03 02:10:39 PM PST 24 Jan 03 02:12:17 PM PST 24 7725820642 ps
T1816 /workspace/coverage/cover_reg_top/59.xbar_random.2296652618 Jan 03 02:10:41 PM PST 24 Jan 03 02:11:24 PM PST 24 319495479 ps
T1817 /workspace/coverage/cover_reg_top/29.xbar_stress_all.3628383658 Jan 03 02:09:52 PM PST 24 Jan 03 02:16:55 PM PST 24 11386227919 ps
T1818 /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.2569991823 Jan 03 02:10:39 PM PST 24 Jan 03 02:46:47 PM PST 24 136263556150 ps
T1819 /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.98834420 Jan 03 02:11:40 PM PST 24 Jan 03 02:23:57 PM PST 24 70954411975 ps
T1820 /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2551451064 Jan 03 02:10:52 PM PST 24 Jan 03 02:13:01 PM PST 24 6160873060 ps
T1821 /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3083743729 Jan 03 02:12:33 PM PST 24 Jan 03 02:22:12 PM PST 24 4120753541 ps
T1822 /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1173759108 Jan 03 02:08:54 PM PST 24 Jan 03 02:26:56 PM PST 24 64939384344 ps
T1823 /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.712258038 Jan 03 02:12:21 PM PST 24 Jan 03 02:12:53 PM PST 24 256203884 ps
T1824 /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3814888608 Jan 03 02:11:17 PM PST 24 Jan 03 02:14:45 PM PST 24 590826500 ps
T1825 /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2597087839 Jan 03 02:11:16 PM PST 24 Jan 03 02:24:55 PM PST 24 44121488964 ps
T1826 /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.335632874 Jan 03 02:12:37 PM PST 24 Jan 03 02:14:23 PM PST 24 5117398535 ps
T1827 /workspace/coverage/cover_reg_top/72.xbar_stress_all.3704541975 Jan 03 02:11:31 PM PST 24 Jan 03 02:22:07 PM PST 24 18928000480 ps
T1828 /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.4011800552 Jan 03 02:07:03 PM PST 24 Jan 03 04:41:30 PM PST 24 70070554500 ps
T21 /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.263733564 Jan 03 02:07:22 PM PST 24 Jan 03 02:13:50 PM PST 24 5764371729 ps
T1829 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1678101560 Jan 03 02:08:13 PM PST 24 Jan 03 02:10:08 PM PST 24 3823651487 ps
T1830 /workspace/coverage/cover_reg_top/71.xbar_smoke.3522110759 Jan 03 02:11:36 PM PST 24 Jan 03 02:11:56 PM PST 24 191093106 ps
T1831 /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3890258118 Jan 03 02:07:14 PM PST 24 Jan 03 02:12:17 PM PST 24 782080411 ps
T1832 /workspace/coverage/cover_reg_top/24.xbar_random.3386708071 Jan 03 02:08:59 PM PST 24 Jan 03 02:09:19 PM PST 24 427388089 ps
T1833 /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1016383848 Jan 03 02:07:29 PM PST 24 Jan 03 02:08:04 PM PST 24 679422194 ps
T1834 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.125760903 Jan 03 02:08:19 PM PST 24 Jan 03 02:08:44 PM PST 24 9406490 ps
T1835 /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3651524655 Jan 03 02:07:21 PM PST 24 Jan 03 02:07:56 PM PST 24 541088480 ps
T1836 /workspace/coverage/cover_reg_top/99.xbar_stress_all.3845310919 Jan 03 02:13:14 PM PST 24 Jan 03 02:16:43 PM PST 24 4943303163 ps
T1837 /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1857512932 Jan 03 02:07:17 PM PST 24 Jan 03 02:08:45 PM PST 24 8457861324 ps
T1838 /workspace/coverage/cover_reg_top/31.xbar_stress_all.2412097652 Jan 03 02:09:35 PM PST 24 Jan 03 02:12:15 PM PST 24 4198748794 ps
T1839 /workspace/coverage/cover_reg_top/50.xbar_access_same_device.4209944308 Jan 03 02:11:01 PM PST 24 Jan 03 02:12:56 PM PST 24 2392029338 ps
T1840 /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.2569363448 Jan 03 02:13:02 PM PST 24 Jan 03 02:25:10 PM PST 24 71630585551 ps
T1841 /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.408574279 Jan 03 02:10:53 PM PST 24 Jan 03 02:12:42 PM PST 24 199650464 ps
T1842 /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.2863690881 Jan 03 02:07:26 PM PST 24 Jan 03 02:09:30 PM PST 24 265705898 ps
T1843 /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1624839786 Jan 03 02:07:47 PM PST 24 Jan 03 02:08:05 PM PST 24 57427920 ps
T1844 /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.2328412840 Jan 03 02:12:19 PM PST 24 Jan 03 02:23:56 PM PST 24 70983228077 ps
T1845 /workspace/coverage/cover_reg_top/92.xbar_stress_all.4047906176 Jan 03 02:12:38 PM PST 24 Jan 03 02:16:53 PM PST 24 3301154682 ps
T1846 /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.3883967601 Jan 03 02:13:29 PM PST 24 Jan 03 02:15:49 PM PST 24 11125174955 ps
T1847 /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.16054822 Jan 03 02:09:47 PM PST 24 Jan 03 02:16:56 PM PST 24 26116418239 ps
T1848 /workspace/coverage/cover_reg_top/1.chip_csr_rw.1198224267 Jan 03 02:07:07 PM PST 24 Jan 03 02:12:10 PM PST 24 4367680835 ps
T1849 /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.210349366 Jan 03 02:12:32 PM PST 24 Jan 03 02:12:49 PM PST 24 25102212 ps
T1850 /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.1165586059 Jan 03 02:10:56 PM PST 24 Jan 03 02:11:54 PM PST 24 409936097 ps
T1851 /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2402504398 Jan 03 02:07:33 PM PST 24 Jan 03 02:07:49 PM PST 24 39036576 ps
T1852 /workspace/coverage/cover_reg_top/3.xbar_same_source.1188009430 Jan 03 02:08:04 PM PST 24 Jan 03 02:08:35 PM PST 24 348446214 ps
T1853 /workspace/coverage/cover_reg_top/45.xbar_smoke.1454777204 Jan 03 02:10:40 PM PST 24 Jan 03 02:11:04 PM PST 24 201515676 ps
T1854 /workspace/coverage/cover_reg_top/9.xbar_error_random.3315660615 Jan 03 02:08:35 PM PST 24 Jan 03 02:09:15 PM PST 24 933699117 ps
T1855 /workspace/coverage/cover_reg_top/85.xbar_access_same_device.542422264 Jan 03 02:12:38 PM PST 24 Jan 03 02:13:26 PM PST 24 394070841 ps
T1856 /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.632341215 Jan 03 02:08:17 PM PST 24 Jan 03 02:09:19 PM PST 24 1363671714 ps
T1857 /workspace/coverage/cover_reg_top/23.chip_tl_errors.520079769 Jan 03 02:14:49 PM PST 24 Jan 03 02:17:45 PM PST 24 3564267200 ps
T1858 /workspace/coverage/cover_reg_top/17.xbar_error_random.2393155276 Jan 03 02:07:58 PM PST 24 Jan 03 02:08:21 PM PST 24 143710721 ps
T1859 /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.1713333599 Jan 03 02:12:17 PM PST 24 Jan 03 02:13:15 PM PST 24 1354056086 ps
T1860 /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.505118699 Jan 03 02:09:36 PM PST 24 Jan 03 02:09:49 PM PST 24 38032193 ps
T1861 /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.1933981991 Jan 03 02:10:44 PM PST 24 Jan 03 02:22:40 PM PST 24 71560023097 ps
T1862 /workspace/coverage/cover_reg_top/20.xbar_smoke.4259411976 Jan 03 02:08:15 PM PST 24 Jan 03 02:08:26 PM PST 24 46141862 ps
T1863 /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.2632615004 Jan 03 02:09:35 PM PST 24 Jan 03 02:13:28 PM PST 24 2845151216 ps
T1864 /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3937820656 Jan 03 02:10:49 PM PST 24 Jan 03 02:11:55 PM PST 24 1017712432 ps
T1865 /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1716591033 Jan 03 02:07:36 PM PST 24 Jan 03 02:14:36 PM PST 24 8933172507 ps
T1866 /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.32271047 Jan 03 02:07:19 PM PST 24 Jan 03 02:09:01 PM PST 24 5608294256 ps
T1867 /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.1715608343 Jan 03 02:13:03 PM PST 24 Jan 03 02:15:16 PM PST 24 6731746793 ps
T1868 /workspace/coverage/cover_reg_top/39.xbar_random.2696635542 Jan 03 02:10:11 PM PST 24 Jan 03 02:11:02 PM PST 24 411891884 ps
T1869 /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.1953983988 Jan 03 02:10:41 PM PST 24 Jan 03 02:11:08 PM PST 24 105689865 ps
T1870 /workspace/coverage/cover_reg_top/33.xbar_random.716164523 Jan 03 02:09:50 PM PST 24 Jan 03 02:11:01 PM PST 24 2096207439 ps
T1871 /workspace/coverage/cover_reg_top/36.xbar_same_source.3540955108 Jan 03 02:09:28 PM PST 24 Jan 03 02:10:33 PM PST 24 1938612357 ps
T1872 /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.4263287874 Jan 03 02:12:36 PM PST 24 Jan 03 02:21:20 PM PST 24 14368913416 ps
T1873 /workspace/coverage/cover_reg_top/40.xbar_random.3722048866 Jan 03 02:09:18 PM PST 24 Jan 03 02:09:57 PM PST 24 1083733379 ps
T1874 /workspace/coverage/cover_reg_top/65.xbar_stress_all.3936217908 Jan 03 02:11:37 PM PST 24 Jan 03 02:14:20 PM PST 24 3709426673 ps
T1875 /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.966028758 Jan 03 02:13:00 PM PST 24 Jan 03 02:13:56 PM PST 24 1115184110 ps
T1876 /workspace/coverage/cover_reg_top/48.xbar_access_same_device.1431536706 Jan 03 02:09:56 PM PST 24 Jan 03 02:10:56 PM PST 24 1271508756 ps
T1877 /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.4015789150 Jan 03 02:12:59 PM PST 24 Jan 03 02:14:21 PM PST 24 4032094808 ps
T1878 /workspace/coverage/cover_reg_top/40.xbar_same_source.1771899387 Jan 03 02:09:41 PM PST 24 Jan 03 02:09:57 PM PST 24 204129331 ps
T1879 /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1002776410 Jan 03 02:10:49 PM PST 24 Jan 03 02:12:33 PM PST 24 7551130143 ps
T1880 /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.3022404213 Jan 03 02:10:48 PM PST 24 Jan 03 02:11:21 PM PST 24 107304163 ps
T1881 /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.3110166075 Jan 03 02:12:45 PM PST 24 Jan 03 02:14:00 PM PST 24 3529769082 ps
T1882 /workspace/coverage/cover_reg_top/13.xbar_smoke.4161269726 Jan 03 02:08:11 PM PST 24 Jan 03 02:08:20 PM PST 24 40304723 ps
T1883 /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1917432316 Jan 03 02:12:36 PM PST 24 Jan 03 02:13:47 PM PST 24 3304854166 ps
T1884 /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.1352547952 Jan 03 02:13:01 PM PST 24 Jan 03 02:17:40 PM PST 24 1778544298 ps
T1885 /workspace/coverage/cover_reg_top/58.xbar_same_source.4150412215 Jan 03 02:10:58 PM PST 24 Jan 03 02:11:55 PM PST 24 1167548809 ps
T1886 /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2468564474 Jan 03 02:11:37 PM PST 24 Jan 03 02:30:42 PM PST 24 68959955215 ps
T1887 /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1413876351 Jan 03 02:10:50 PM PST 24 Jan 03 02:13:28 PM PST 24 2109196025 ps
T281 /workspace/coverage/cover_reg_top/14.chip_tl_errors.711650312 Jan 03 02:08:43 PM PST 24 Jan 03 02:17:26 PM PST 24 5627424962 ps
T1888 /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2785939073 Jan 03 02:11:15 PM PST 24 Jan 03 02:12:11 PM PST 24 180924194 ps
T1889 /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.1905734549 Jan 03 02:08:17 PM PST 24 Jan 03 02:09:58 PM PST 24 5336707217 ps
T342 /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.277964474 Jan 03 02:12:16 PM PST 24 Jan 03 02:17:50 PM PST 24 956891115 ps
T1890 /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.3914108355 Jan 03 02:12:33 PM PST 24 Jan 03 02:13:32 PM PST 24 1330910181 ps
T1891 /workspace/coverage/cover_reg_top/83.xbar_error_random.4201098760 Jan 03 02:12:43 PM PST 24 Jan 03 02:14:10 PM PST 24 2083111570 ps
T1892 /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.3014445289 Jan 03 02:09:53 PM PST 24 Jan 03 02:20:03 PM PST 24 35502251152 ps
T1893 /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3527063312 Jan 03 02:10:33 PM PST 24 Jan 03 02:12:20 PM PST 24 5250270918 ps
T1894 /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2203800495 Jan 03 02:13:01 PM PST 24 Jan 03 02:18:51 PM PST 24 1666552827 ps
T1895 /workspace/coverage/cover_reg_top/17.chip_csr_rw.1319268319 Jan 03 02:07:54 PM PST 24 Jan 03 02:16:31 PM PST 24 5813388722 ps
T1896 /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.2113873434 Jan 03 02:09:40 PM PST 24 Jan 03 02:10:08 PM PST 24 202280003 ps
T1897 /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.1296322330 Jan 03 02:08:36 PM PST 24 Jan 03 02:08:53 PM PST 24 77366976 ps
T1898 /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.4073122495 Jan 03 02:11:17 PM PST 24 Jan 03 02:14:07 PM PST 24 1516208817 ps
T1899 /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.4222178481 Jan 03 02:12:35 PM PST 24 Jan 03 02:14:37 PM PST 24 10732587306 ps
T1900 /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.2094946320 Jan 03 02:07:45 PM PST 24 Jan 03 02:23:54 PM PST 24 56360616616 ps
T1901 /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3991360719 Jan 03 02:08:06 PM PST 24 Jan 03 02:47:56 PM PST 24 27086370748 ps
T1902 /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.419906425 Jan 03 02:09:20 PM PST 24 Jan 03 02:10:01 PM PST 24 395007319 ps
T1903 /workspace/coverage/cover_reg_top/7.chip_tl_errors.3155775091 Jan 03 02:07:31 PM PST 24 Jan 03 02:11:41 PM PST 24 3851598585 ps
T1904 /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.2488598530 Jan 03 02:12:22 PM PST 24 Jan 03 02:23:53 PM PST 24 62785324384 ps
T1905 /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1423420156 Jan 03 02:07:05 PM PST 24 Jan 03 02:11:21 PM PST 24 4200904144 ps
T1906 /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.4219865125 Jan 03 02:10:54 PM PST 24 Jan 03 02:11:42 PM PST 24 295847544 ps
T1907 /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2621302051 Jan 03 02:12:14 PM PST 24 Jan 03 02:13:29 PM PST 24 6794942209 ps
T1908 /workspace/coverage/cover_reg_top/85.xbar_stress_all.4292433730 Jan 03 02:12:37 PM PST 24 Jan 03 02:22:17 PM PST 24 16525765217 ps
T1909 /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.1141990651 Jan 03 02:09:15 PM PST 24 Jan 03 02:10:29 PM PST 24 2071132228 ps
T1910 /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1668200471 Jan 03 02:07:06 PM PST 24 Jan 03 02:07:27 PM PST 24 221455762 ps
T1911 /workspace/coverage/cover_reg_top/81.xbar_same_source.1003555592 Jan 03 02:12:18 PM PST 24 Jan 03 02:13:08 PM PST 24 600181677 ps
T1912 /workspace/coverage/cover_reg_top/63.xbar_same_source.2053994736 Jan 03 02:11:24 PM PST 24 Jan 03 02:12:33 PM PST 24 1819378283 ps
T1913 /workspace/coverage/cover_reg_top/67.xbar_same_source.1869559257 Jan 03 02:11:17 PM PST 24 Jan 03 02:11:45 PM PST 24 303500568 ps
T1914 /workspace/coverage/cover_reg_top/97.xbar_error_random.2646726313 Jan 03 02:13:34 PM PST 24 Jan 03 02:14:10 PM PST 24 251208491 ps
T279 /workspace/coverage/cover_reg_top/17.chip_tl_errors.1819079537 Jan 03 02:07:53 PM PST 24 Jan 03 02:13:08 PM PST 24 3823765648 ps
T1915 /workspace/coverage/cover_reg_top/59.xbar_error_random.576232250 Jan 03 02:10:42 PM PST 24 Jan 03 02:11:27 PM PST 24 756707121 ps
T1916 /workspace/coverage/cover_reg_top/62.xbar_random.2500270735 Jan 03 02:10:56 PM PST 24 Jan 03 02:12:01 PM PST 24 1227744740 ps
T1917 /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.1244648781 Jan 03 02:11:22 PM PST 24 Jan 03 02:11:44 PM PST 24 56310634 ps
T1918 /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2713142941 Jan 03 02:12:38 PM PST 24 Jan 03 02:34:13 PM PST 24 75990823621 ps
T1919 /workspace/coverage/cover_reg_top/73.xbar_smoke.3311756957 Jan 03 02:11:31 PM PST 24 Jan 03 02:11:48 PM PST 24 173522234 ps
T1920 /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.1118681138 Jan 03 02:10:49 PM PST 24 Jan 03 02:12:07 PM PST 24 5701010318 ps
T1921 /workspace/coverage/cover_reg_top/28.xbar_same_source.1649777348 Jan 03 02:09:31 PM PST 24 Jan 03 02:10:12 PM PST 24 445116027 ps
T1922 /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.2052756725 Jan 03 02:09:40 PM PST 24 Jan 03 02:19:31 PM PST 24 36370691636 ps

Test location /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.1722943884
Short name T1
Test name
Test status
Simulation time 13971362234 ps
CPU time 1258.88 seconds
Started Jan 03 02:07:55 PM PST 24
Finished Jan 03 02:29:04 PM PST 24
Peak memory 579976 kb
Host smart-2cf0b533-e7b0-4e68-a603-f51afec558d3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722943884 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.1722943884
Directory /workspace/19.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.738864668
Short name T5
Test name
Test status
Simulation time 11195384000 ps
CPU time 351.49 seconds
Started Jan 03 02:11:03 PM PST 24
Finished Jan 03 02:17:16 PM PST 24
Peak memory 555344 kb
Host smart-9dead9d5-151d-41d6-8005-c992c252d8e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738864668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.738864668
Directory /workspace/57.xbar_stress_all_with_error/latest

Test location /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3845812802
Short name T14
Test name
Test status
Simulation time 4424428200 ps
CPU time 237.85 seconds
Started Jan 03 02:03:37 PM PST 24
Finished Jan 03 02:08:37 PM PST 24
Peak memory 631208 kb
Host smart-23acbe69-8391-4fb8-8782-1a7d736c65a6
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845812802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 3.chip_padctrl_attributes.3845812802
Directory /workspace/3.chip_padctrl_attributes/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.1973839848
Short name T299
Test name
Test status
Simulation time 81134687252 ps
CPU time 1490.07 seconds
Started Jan 03 02:11:25 PM PST 24
Finished Jan 03 02:36:26 PM PST 24
Peak memory 555256 kb
Host smart-821683d6-13f7-4b92-bdd9-560f190833ba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973839848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_
device_slow_rsp.1973839848
Directory /workspace/64.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2533537857
Short name T206
Test name
Test status
Simulation time 115117124978 ps
CPU time 1798.43 seconds
Started Jan 03 02:10:51 PM PST 24
Finished Jan 03 02:41:12 PM PST 24
Peak memory 555280 kb
Host smart-edf623d8-605f-429f-9e5d-5a473b45cb87
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533537857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_
device_slow_rsp.2533537857
Directory /workspace/44.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3286074553
Short name T134
Test name
Test status
Simulation time 133662442892 ps
CPU time 2145.85 seconds
Started Jan 03 02:08:12 PM PST 24
Finished Jan 03 02:44:01 PM PST 24
Peak memory 555068 kb
Host smart-0449e33e-f3b8-480b-aca4-d85843fc34a7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286074553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_
device_slow_rsp.3286074553
Directory /workspace/13.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.chip_csr_rw.4060006888
Short name T20
Test name
Test status
Simulation time 5266974050 ps
CPU time 451.35 seconds
Started Jan 03 02:07:26 PM PST 24
Finished Jan 03 02:15:08 PM PST 24
Peak memory 579948 kb
Host smart-04280032-96d2-4d5c-a470-dc02ce6fb03b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060006888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.4060006888
Directory /workspace/6.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1728727662
Short name T287
Test name
Test status
Simulation time 139840933994 ps
CPU time 2428.89 seconds
Started Jan 03 02:10:01 PM PST 24
Finished Jan 03 02:50:43 PM PST 24
Peak memory 555456 kb
Host smart-6f8765f5-6a49-4c11-85c2-7abb4c7c3fb9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728727662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_
device_slow_rsp.1728727662
Directory /workspace/41.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.772607918
Short name T77
Test name
Test status
Simulation time 69944588902 ps
CPU time 1118.34 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:26:25 PM PST 24
Peak memory 555044 kb
Host smart-6fde85e7-55ff-4c99-9143-d6c5a035d52a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772607918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_d
evice_slow_rsp.772607918
Directory /workspace/18.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/default/1.chip_jtag_csr_rw.829427223
Short name T19
Test name
Test status
Simulation time 12688667444 ps
CPU time 1165.44 seconds
Started Jan 03 02:05:08 PM PST 24
Finished Jan 03 02:25:01 PM PST 24
Peak memory 596120 kb
Host smart-cdc626b4-1a3a-4c4a-9d85-87ec9b966ba8
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829427223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch
ip_jtag_csr_rw.829427223
Directory /workspace/1.chip_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.chip_tl_errors.827891083
Short name T2
Test name
Test status
Simulation time 3997184294 ps
CPU time 311.83 seconds
Started Jan 03 02:08:22 PM PST 24
Finished Jan 03 02:13:43 PM PST 24
Peak memory 580032 kb
Host smart-8ba7baba-d2eb-4e0b-bbea-3f8626d32a91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827891083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.827891083
Directory /workspace/4.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_same_source.128224371
Short name T59
Test name
Test status
Simulation time 496682617 ps
CPU time 33.51 seconds
Started Jan 03 02:08:43 PM PST 24
Finished Jan 03 02:09:24 PM PST 24
Peak memory 553160 kb
Host smart-6be9a174-a13e-43ac-8157-d4204d8ccfad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128224371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.128224371
Directory /workspace/30.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.937132923
Short name T214
Test name
Test status
Simulation time 159569777685 ps
CPU time 2537.71 seconds
Started Jan 03 02:09:25 PM PST 24
Finished Jan 03 02:51:53 PM PST 24
Peak memory 555356 kb
Host smart-cd010f85-354f-41eb-994c-8c98fbe156c8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937132923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_d
evice_slow_rsp.937132923
Directory /workspace/34.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.875089257
Short name T10
Test name
Test status
Simulation time 4573050088 ps
CPU time 225.26 seconds
Started Jan 03 02:08:36 PM PST 24
Finished Jan 03 02:12:29 PM PST 24
Peak memory 639972 kb
Host smart-c4b3457e-0c49-4c56-a0ae-5d62e050a611
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875089257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_re
set.875089257
Directory /workspace/3.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.1068393569
Short name T772
Test name
Test status
Simulation time 117448855481 ps
CPU time 1849.44 seconds
Started Jan 03 02:13:18 PM PST 24
Finished Jan 03 02:44:34 PM PST 24
Peak memory 555024 kb
Host smart-49330d65-23e5-48b2-a08f-62bb10146f1b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068393569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_
device_slow_rsp.1068393569
Directory /workspace/98.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.1821334920
Short name T149
Test name
Test status
Simulation time 3911812521 ps
CPU time 351.21 seconds
Started Jan 03 02:10:03 PM PST 24
Finished Jan 03 02:16:11 PM PST 24
Peak memory 556708 kb
Host smart-d12f53aa-bb32-4205-b687-488f4922a8f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821334920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.1821334920
Directory /workspace/50.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3789406240
Short name T13
Test name
Test status
Simulation time 7478909592 ps
CPU time 357.54 seconds
Started Jan 03 02:07:04 PM PST 24
Finished Jan 03 02:13:03 PM PST 24
Peak memory 638620 kb
Host smart-6ee64cf3-5d70-4cf7-a847-ae513350701d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789406240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r
eset.3789406240
Directory /workspace/1.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1470043489
Short name T102
Test name
Test status
Simulation time 12783743090 ps
CPU time 1169.12 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:31:54 PM PST 24
Peak memory 567680 kb
Host smart-4b149d26-d6d8-430e-8316-22cd1be4db55
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470043489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all
_with_rand_reset.1470043489
Directory /workspace/79.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1583265139
Short name T305
Test name
Test status
Simulation time 97047066176 ps
CPU time 1596.14 seconds
Started Jan 03 02:11:16 PM PST 24
Finished Jan 03 02:38:08 PM PST 24
Peak memory 553944 kb
Host smart-b96547b0-a34d-4889-84bf-6200b8d5e8c9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583265139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_
device_slow_rsp.1583265139
Directory /workspace/72.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.552678740
Short name T318
Test name
Test status
Simulation time 12560944917 ps
CPU time 429.2 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:19:59 PM PST 24
Peak memory 556236 kb
Host smart-c50bfa9f-7c3a-4893-be60-70cfb7cf6354
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552678740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.552678740
Directory /workspace/88.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.3141699975
Short name T53
Test name
Test status
Simulation time 3994342564 ps
CPU time 203 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:11:09 PM PST 24
Peak memory 623424 kb
Host smart-05ceb571-9bb2-466a-8c8f-b4401db7cc1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141699975 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.3141699975
Directory /workspace/18.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1563916225
Short name T11
Test name
Test status
Simulation time 6244434360 ps
CPU time 314.37 seconds
Started Jan 03 02:07:43 PM PST 24
Finished Jan 03 02:13:09 PM PST 24
Peak memory 640060 kb
Host smart-2d3aa53a-f45c-43c5-a74a-30a6581c9f4f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563916225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r
eset.1563916225
Directory /workspace/0.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.3046304867
Short name T61
Test name
Test status
Simulation time 41769364598 ps
CPU time 414.47 seconds
Started Jan 03 02:07:53 PM PST 24
Finished Jan 03 02:14:58 PM PST 24
Peak memory 554284 kb
Host smart-35165e5d-c681-4c77-ac92-bf6088120790
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046304867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3046304867
Directory /workspace/21.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/11.chip_tl_errors.2248509087
Short name T225
Test name
Test status
Simulation time 4709669636 ps
CPU time 362.04 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:14:26 PM PST 24
Peak memory 580032 kb
Host smart-2b8f517a-6b8c-41bd-8514-daec85ac86a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248509087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.2248509087
Directory /workspace/11.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.2359729375
Short name T34
Test name
Test status
Simulation time 11892864957 ps
CPU time 353.87 seconds
Started Jan 03 02:07:23 PM PST 24
Finished Jan 03 02:13:29 PM PST 24
Peak memory 575664 kb
Host smart-fb109d81-f41e-4429-9c0a-ebba5b912104
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359729375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.chip_prim_tl_access.2359729375
Directory /workspace/2.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1949238564
Short name T12
Test name
Test status
Simulation time 4109247720 ps
CPU time 222.49 seconds
Started Jan 03 02:07:59 PM PST 24
Finished Jan 03 02:11:52 PM PST 24
Peak memory 641164 kb
Host smart-b43da254-ad93-4447-8e1f-a6535ddd53a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949238564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r
eset.1949238564
Directory /workspace/2.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1120297847
Short name T117
Test name
Test status
Simulation time 20858436560 ps
CPU time 810.71 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:26:47 PM PST 24
Peak memory 559092 kb
Host smart-83cf07cc-e14f-4a47-a162-9976a29792cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120297847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all
_with_rand_reset.1120297847
Directory /workspace/75.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all.490913081
Short name T85
Test name
Test status
Simulation time 9610304739 ps
CPU time 328.58 seconds
Started Jan 03 02:11:33 PM PST 24
Finished Jan 03 02:17:11 PM PST 24
Peak memory 554304 kb
Host smart-6cb4cf25-f1ea-4833-af75-e0673e2cd36f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490913081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.490913081
Directory /workspace/63.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.325552747
Short name T48
Test name
Test status
Simulation time 7463427285 ps
CPU time 363.83 seconds
Started Jan 03 02:12:38 PM PST 24
Finished Jan 03 02:18:57 PM PST 24
Peak memory 556396 kb
Host smart-6ee2ceb6-ee32-4416-9dba-ac2759d8f106
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325552747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_
with_rand_reset.325552747
Directory /workspace/82.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.chip_jtag_csr_rw.3893365163
Short name T30
Test name
Test status
Simulation time 9896088994 ps
CPU time 952.91 seconds
Started Jan 03 02:06:45 PM PST 24
Finished Jan 03 02:22:41 PM PST 24
Peak memory 596108 kb
Host smart-41ccfa46-d3f5-4216-82d0-2a0215081d90
User root
Command /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893365163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T
EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c
hip_jtag_csr_rw.3893365163
Directory /workspace/2.chip_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3037181042
Short name T31
Test name
Test status
Simulation time 15398349017 ps
CPU time 1373.63 seconds
Started Jan 03 02:08:14 PM PST 24
Finished Jan 03 02:31:11 PM PST 24
Peak memory 579964 kb
Host smart-27bcd8d7-2a23-466d-b863-1b9772be5233
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037181042 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.3037181042
Directory /workspace/11.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/28.chip_tl_errors.2893282954
Short name T39
Test name
Test status
Simulation time 4054415340 ps
CPU time 301.62 seconds
Started Jan 03 02:08:50 PM PST 24
Finished Jan 03 02:13:56 PM PST 24
Peak memory 580080 kb
Host smart-dbd55159-ea7f-4895-b5e3-e88a51a7d540
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893282954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.2893282954
Directory /workspace/28.chip_tl_errors/latest

Test location /workspace/coverage/default/1.chip_jtag_mem_access.19650827
Short name T18
Test name
Test status
Simulation time 13207734080 ps
CPU time 1099.82 seconds
Started Jan 03 02:05:09 PM PST 24
Finished Jan 03 02:23:55 PM PST 24
Peak memory 596112 kb
Host smart-3ab41a31-61b7-43b1-84b8-721e197e270d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19650827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_me
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.19650827
Directory /workspace/1.chip_jtag_mem_access/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.263733564
Short name T21
Test name
Test status
Simulation time 5764371729 ps
CPU time 376.54 seconds
Started Jan 03 02:07:22 PM PST 24
Finished Jan 03 02:13:50 PM PST 24
Peak memory 640644 kb
Host smart-6bc04b46-c5c4-47d4-b0b8-7c54652aed4b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263733564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_re
set.263733564
Directory /workspace/4.chip_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_access_same_device.3239220792
Short name T161
Test name
Test status
Simulation time 2142829008 ps
CPU time 86.69 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:11:10 PM PST 24
Peak memory 553908 kb
Host smart-bbaff0d0-1724-4aed-b559-244a26e7b8ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239220792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device
.3239220792
Directory /workspace/34.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1599532998
Short name T112
Test name
Test status
Simulation time 10354819089 ps
CPU time 616.1 seconds
Started Jan 03 02:09:17 PM PST 24
Finished Jan 03 02:19:35 PM PST 24
Peak memory 558700 kb
Host smart-0d1650fa-63f7-4a1b-be06-78e735569913
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599532998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all
_with_rand_reset.1599532998
Directory /workspace/28.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.chip_tl_errors.2929242413
Short name T41
Test name
Test status
Simulation time 3800065473 ps
CPU time 286.47 seconds
Started Jan 03 02:07:57 PM PST 24
Finished Jan 03 02:12:54 PM PST 24
Peak memory 580016 kb
Host smart-25f209fd-1d81-4a2c-8b9a-42258a1ad5d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929242413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.2929242413
Directory /workspace/19.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.721135969
Short name T352
Test name
Test status
Simulation time 2314747027 ps
CPU time 350.65 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:19:07 PM PST 24
Peak memory 567264 kb
Host smart-cb0823cb-7f82-48a1-92f4-d5ab64f9f2d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721135969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all
_with_reset_error.721135969
Directory /workspace/85.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2830608182
Short name T4
Test name
Test status
Simulation time 1452761614 ps
CPU time 166.26 seconds
Started Jan 03 02:07:32 PM PST 24
Finished Jan 03 02:10:28 PM PST 24
Peak memory 555324 kb
Host smart-cfc7674c-67fc-42b5-9f16-abde969b2491
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830608182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_
with_rand_reset.2830608182
Directory /workspace/2.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3449817205
Short name T354
Test name
Test status
Simulation time 19787390493 ps
CPU time 848.96 seconds
Started Jan 03 02:07:26 PM PST 24
Finished Jan 03 02:21:46 PM PST 24
Peak memory 567104 kb
Host smart-b5966552-eff2-4dbc-bea5-bdddacafe32d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449817205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al
l_with_reset_error.3449817205
Directory /workspace/14.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2843786702
Short name T198
Test name
Test status
Simulation time 7043343754 ps
CPU time 382.82 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:19:46 PM PST 24
Peak memory 556800 kb
Host smart-1e620acd-0f33-4863-89da-1babb2db015e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843786702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all
_with_rand_reset.2843786702
Directory /workspace/89.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.chip_tl_errors.946421848
Short name T212
Test name
Test status
Simulation time 3134700342 ps
CPU time 117.45 seconds
Started Jan 03 02:07:21 PM PST 24
Finished Jan 03 02:09:30 PM PST 24
Peak memory 580044 kb
Host smart-389c24cb-b30a-4497-a6c7-8566f6e8df1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946421848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.946421848
Directory /workspace/8.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.3018860076
Short name T45
Test name
Test status
Simulation time 32419451517 ps
CPU time 2957.02 seconds
Started Jan 03 02:07:47 PM PST 24
Finished Jan 03 02:57:16 PM PST 24
Peak memory 579996 kb
Host smart-a26d975d-1be2-4c42-884c-5602c613c1c2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018860076 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.3018860076
Directory /workspace/8.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3125417460
Short name T253
Test name
Test status
Simulation time 15774779141 ps
CPU time 617.81 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:23:34 PM PST 24
Peak memory 558364 kb
Host smart-52c6328a-4f8d-4ac6-b5ef-429f40e643d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125417460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al
l_with_reset_error.3125417460
Directory /workspace/88.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3868761189
Short name T25
Test name
Test status
Simulation time 5162702969 ps
CPU time 266.61 seconds
Started Jan 03 02:03:19 PM PST 24
Finished Jan 03 02:08:07 PM PST 24
Peak memory 631292 kb
Host smart-c75d5666-089d-4a41-999c-0e6c6dace7cb
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868761189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 2.chip_padctrl_attributes.3868761189
Directory /workspace/2.chip_padctrl_attributes/latest

Test location /workspace/coverage/cover_reg_top/6.chip_tl_errors.3262234757
Short name T271
Test name
Test status
Simulation time 3497603427 ps
CPU time 238.58 seconds
Started Jan 03 02:07:35 PM PST 24
Finished Jan 03 02:11:44 PM PST 24
Peak memory 580092 kb
Host smart-b7f65f0d-b486-4467-9954-f2d9b5940be7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262234757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.3262234757
Directory /workspace/6.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2988612491
Short name T340
Test name
Test status
Simulation time 762720626 ps
CPU time 272.7 seconds
Started Jan 03 02:07:38 PM PST 24
Finished Jan 03 02:12:23 PM PST 24
Peak memory 557404 kb
Host smart-3a458d24-3b63-4dc1-b3b4-26fb8d49abba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988612491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all
_with_rand_reset.2988612491
Directory /workspace/14.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.1599762825
Short name T148
Test name
Test status
Simulation time 19150775493 ps
CPU time 661.16 seconds
Started Jan 03 02:10:12 PM PST 24
Finished Jan 03 02:21:30 PM PST 24
Peak memory 555356 kb
Host smart-330de172-f78b-461d-b4ff-c642f214978f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599762825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.1599762825
Directory /workspace/54.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/9.chip_tl_errors.1455221275
Short name T274
Test name
Test status
Simulation time 2942128948 ps
CPU time 165.21 seconds
Started Jan 03 02:08:23 PM PST 24
Finished Jan 03 02:11:17 PM PST 24
Peak memory 580068 kb
Host smart-9b43f52c-5851-4ea9-a6dd-c52c8764f7d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455221275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.1455221275
Directory /workspace/9.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.924717987
Short name T570
Test name
Test status
Simulation time 7220557215 ps
CPU time 290.56 seconds
Started Jan 03 02:07:48 PM PST 24
Finished Jan 03 02:12:49 PM PST 24
Peak memory 623072 kb
Host smart-5d86b2ba-bcc7-4844-a77d-6e947c5c78de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924717987 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.924717987
Directory /workspace/10.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1234999744
Short name T200
Test name
Test status
Simulation time 851978498 ps
CPU time 286.66 seconds
Started Jan 03 02:07:43 PM PST 24
Finished Jan 03 02:12:42 PM PST 24
Peak memory 558336 kb
Host smart-30d8a55a-027a-42a0-be37-7db52c992166
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234999744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all
_with_rand_reset.1234999744
Directory /workspace/10.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3555123595
Short name T349
Test name
Test status
Simulation time 120828965 ps
CPU time 96.84 seconds
Started Jan 03 02:08:13 PM PST 24
Finished Jan 03 02:09:53 PM PST 24
Peak memory 555380 kb
Host smart-ec6ce116-296d-45c4-a7cb-70b6c7ed86db
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555123595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al
l_with_reset_error.3555123595
Directory /workspace/22.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.3472652034
Short name T285
Test name
Test status
Simulation time 3214301988 ps
CPU time 224.52 seconds
Started Jan 03 02:10:59 PM PST 24
Finished Jan 03 02:15:05 PM PST 24
Peak memory 556144 kb
Host smart-62730696-238e-4510-9595-222029c9aaf3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472652034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al
l_with_reset_error.3472652034
Directory /workspace/58.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_access_same_device.1221700782
Short name T232
Test name
Test status
Simulation time 3177555847 ps
CPU time 133.13 seconds
Started Jan 03 02:07:43 PM PST 24
Finished Jan 03 02:10:08 PM PST 24
Peak memory 554020 kb
Host smart-d20a5b9b-5717-4b63-a3ad-57f6434bda32
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221700782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device
.1221700782
Directory /workspace/17.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/2.chip_tl_errors.465745676
Short name T221
Test name
Test status
Simulation time 3260364000 ps
CPU time 116.45 seconds
Started Jan 03 02:07:27 PM PST 24
Finished Jan 03 02:09:34 PM PST 24
Peak memory 580044 kb
Host smart-0221375c-f513-4b4c-a3f2-f551d0baba7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465745676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.465745676
Directory /workspace/2.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.chip_tl_errors.3205945158
Short name T272
Test name
Test status
Simulation time 3301349290 ps
CPU time 195.18 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:11:38 PM PST 24
Peak memory 580056 kb
Host smart-017b7bbf-5dae-4239-b99f-bd9ab012124c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205945158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3205945158
Directory /workspace/20.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3488300992
Short name T28
Test name
Test status
Simulation time 31770399001 ps
CPU time 3139.88 seconds
Started Jan 03 02:08:07 PM PST 24
Finished Jan 03 03:00:33 PM PST 24
Peak memory 580036 kb
Host smart-d2ca9707-9668-4a6e-aae4-6de94086d3d0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488300992 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3488300992
Directory /workspace/15.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2015315308
Short name T969
Test name
Test status
Simulation time 66560521134 ps
CPU time 7923.98 seconds
Started Jan 03 02:07:56 PM PST 24
Finished Jan 03 04:20:12 PM PST 24
Peak memory 624208 kb
Host smart-b74c7552-6f91-4c86-9f37-1759b1d63c38
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015315308 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.chip_csr_aliasing.2015315308
Directory /workspace/1.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.918997978
Short name T247
Test name
Test status
Simulation time 4668489939 ps
CPU time 168.58 seconds
Started Jan 03 02:07:55 PM PST 24
Finished Jan 03 02:10:54 PM PST 24
Peak memory 555344 kb
Host smart-1d7a4073-fca7-4d98-aa42-26ccacda5774
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918997978 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.918997978
Directory /workspace/17.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.4057919327
Short name T254
Test name
Test status
Simulation time 7878072574 ps
CPU time 262.03 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:14:05 PM PST 24
Peak memory 555404 kb
Host smart-98cf5065-6b97-4650-a990-d71e789507ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057919327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.4057919327
Directory /workspace/34.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_error_random.1792314741
Short name T251
Test name
Test status
Simulation time 2113535415 ps
CPU time 69.43 seconds
Started Jan 03 02:10:32 PM PST 24
Finished Jan 03 02:11:55 PM PST 24
Peak memory 554120 kb
Host smart-891c898e-8888-4fd7-98a7-fee14a12e5f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792314741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1792314741
Directory /workspace/36.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3015421688
Short name T252
Test name
Test status
Simulation time 16004532222 ps
CPU time 690.78 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:24:23 PM PST 24
Peak memory 559100 kb
Host smart-51b3715c-a09a-4464-ac5d-722b14cc04ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015421688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al
l_with_reset_error.3015421688
Directory /workspace/76.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2628322683
Short name T16
Test name
Test status
Simulation time 5636027940 ps
CPU time 240.27 seconds
Started Jan 03 02:03:20 PM PST 24
Finished Jan 03 02:07:43 PM PST 24
Peak memory 629892 kb
Host smart-41fab753-fa44-44bb-9e48-fa3bd1de6781
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628322683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 0.chip_padctrl_attributes.2628322683
Directory /workspace/0.chip_padctrl_attributes/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.4011800552
Short name T1828
Test name
Test status
Simulation time 70070554500 ps
CPU time 9264.19 seconds
Started Jan 03 02:07:03 PM PST 24
Finished Jan 03 04:41:30 PM PST 24
Peak memory 626152 kb
Host smart-f28953a3-d51f-4f09-87ba-972554b47708
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011800552 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.chip_csr_aliasing.4011800552
Directory /workspace/0.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1423420156
Short name T1905
Test name
Test status
Simulation time 4200904144 ps
CPU time 254.33 seconds
Started Jan 03 02:07:05 PM PST 24
Finished Jan 03 02:11:21 PM PST 24
Peak memory 580032 kb
Host smart-41bfd472-3615-4fe3-8d2d-cf020ba6c6c5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423420156 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.1423420156
Directory /workspace/0.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1007259996
Short name T52
Test name
Test status
Simulation time 8225944710 ps
CPU time 377.3 seconds
Started Jan 03 02:07:43 PM PST 24
Finished Jan 03 02:14:12 PM PST 24
Peak memory 621000 kb
Host smart-e61999ac-686e-475e-9f7c-25922deee8e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007259996 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.1007259996
Directory /workspace/0.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.chip_csr_rw.4094060335
Short name T1289
Test name
Test status
Simulation time 5490351382 ps
CPU time 514.36 seconds
Started Jan 03 02:07:22 PM PST 24
Finished Jan 03 02:16:08 PM PST 24
Peak memory 579984 kb
Host smart-5dc696c7-8f85-4af4-b3ab-9d41531ac107
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094060335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.4094060335
Directory /workspace/0.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.737968570
Short name T36
Test name
Test status
Simulation time 14490028846 ps
CPU time 528.38 seconds
Started Jan 03 02:07:17 PM PST 24
Finished Jan 03 02:16:11 PM PST 24
Peak memory 575996 kb
Host smart-41de44e2-841b-4f16-8482-218381368f6f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737968570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ
=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.chip_prim_tl_access.737968570
Directory /workspace/0.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2734319519
Short name T35
Test name
Test status
Simulation time 14703591155 ps
CPU time 446.59 seconds
Started Jan 03 02:07:34 PM PST 24
Finished Jan 03 02:15:11 PM PST 24
Peak memory 577328 kb
Host smart-0f36fdf2-b717-4dd2-b0be-4303705564fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734319519 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.chip_rv_dm_lc_disabled.2734319519
Directory /workspace/0.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3510724433
Short name T49
Test name
Test status
Simulation time 30900628956 ps
CPU time 2897.09 seconds
Started Jan 03 02:07:03 PM PST 24
Finished Jan 03 02:55:22 PM PST 24
Peak memory 580012 kb
Host smart-d2a2d9d9-af86-47e8-a062-ce1e1cc2000c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510724433 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.3510724433
Directory /workspace/0.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.chip_tl_errors.1278017282
Short name T217
Test name
Test status
Simulation time 3490207798 ps
CPU time 187.73 seconds
Started Jan 03 02:07:05 PM PST 24
Finished Jan 03 02:10:14 PM PST 24
Peak memory 580008 kb
Host smart-2819ae6d-5e60-4557-84ad-dd2a2b84b6eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278017282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1278017282
Directory /workspace/0.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_access_same_device.1215314410
Short name T154
Test name
Test status
Simulation time 1337410438 ps
CPU time 55.04 seconds
Started Jan 03 02:07:19 PM PST 24
Finished Jan 03 02:08:22 PM PST 24
Peak memory 554184 kb
Host smart-601cd33f-04e2-4b5a-84b4-c84e61f41337
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215314410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.
1215314410
Directory /workspace/0.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2878618362
Short name T667
Test name
Test status
Simulation time 81872767381 ps
CPU time 1280.86 seconds
Started Jan 03 02:07:31 PM PST 24
Finished Jan 03 02:29:02 PM PST 24
Peak memory 555228 kb
Host smart-22eab958-0c80-40fb-a49e-5074468a2692
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878618362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d
evice_slow_rsp.2878618362
Directory /workspace/0.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1552937251
Short name T1590
Test name
Test status
Simulation time 334853201 ps
CPU time 15.11 seconds
Started Jan 03 02:07:53 PM PST 24
Finished Jan 03 02:08:19 PM PST 24
Peak memory 553844 kb
Host smart-4aeeb397-a348-4a1b-9202-d82f14d13d0f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552937251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr
.1552937251
Directory /workspace/0.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_error_random.2747347890
Short name T1565
Test name
Test status
Simulation time 549074651 ps
CPU time 17.51 seconds
Started Jan 03 02:07:18 PM PST 24
Finished Jan 03 02:07:41 PM PST 24
Peak memory 554096 kb
Host smart-d53b4d20-e722-4824-b949-c2917940681c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747347890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2747347890
Directory /workspace/0.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random.3963178858
Short name T1527
Test name
Test status
Simulation time 512820571 ps
CPU time 39.3 seconds
Started Jan 03 02:07:23 PM PST 24
Finished Jan 03 02:08:15 PM PST 24
Peak memory 553064 kb
Host smart-0492aa1f-f2a0-454c-a426-8a8aabe4bcdb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963178858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3963178858
Directory /workspace/0.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2733466308
Short name T1000
Test name
Test status
Simulation time 72531423256 ps
CPU time 761.94 seconds
Started Jan 03 02:07:27 PM PST 24
Finished Jan 03 02:20:19 PM PST 24
Peak memory 553132 kb
Host smart-27ef9914-ba07-4ce7-9da9-ac001065f3e2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733466308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2733466308
Directory /workspace/0.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2408171450
Short name T626
Test name
Test status
Simulation time 29100394994 ps
CPU time 474.11 seconds
Started Jan 03 02:07:47 PM PST 24
Finished Jan 03 02:15:53 PM PST 24
Peak memory 554204 kb
Host smart-a414d1de-62c6-49c4-b656-29628409fc0a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408171450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2408171450
Directory /workspace/0.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1668200471
Short name T1910
Test name
Test status
Simulation time 221455762 ps
CPU time 20.29 seconds
Started Jan 03 02:07:06 PM PST 24
Finished Jan 03 02:07:27 PM PST 24
Peak memory 553844 kb
Host smart-0e5a16e7-3b0c-4fc6-b36f-0197a17c8caf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668200471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela
ys.1668200471
Directory /workspace/0.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_same_source.3559624898
Short name T1188
Test name
Test status
Simulation time 248982703 ps
CPU time 18.95 seconds
Started Jan 03 02:07:25 PM PST 24
Finished Jan 03 02:07:55 PM PST 24
Peak memory 554112 kb
Host smart-cca4fbab-dde6-4529-9234-9fec5ac09a2e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559624898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3559624898
Directory /workspace/0.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke.1952759135
Short name T1698
Test name
Test status
Simulation time 38636428 ps
CPU time 5.23 seconds
Started Jan 03 02:07:19 PM PST 24
Finished Jan 03 02:07:35 PM PST 24
Peak memory 552024 kb
Host smart-78a0b438-8629-40bc-bb6f-35124c020cef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952759135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1952759135
Directory /workspace/0.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1622261132
Short name T561
Test name
Test status
Simulation time 6852499895 ps
CPU time 70.14 seconds
Started Jan 03 02:07:08 PM PST 24
Finished Jan 03 02:08:19 PM PST 24
Peak memory 551880 kb
Host smart-7ef59ad6-4a4f-4ec8-b860-e2966ec3dd45
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622261132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1622261132
Directory /workspace/0.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.32271047
Short name T1866
Test name
Test status
Simulation time 5608294256 ps
CPU time 90.51 seconds
Started Jan 03 02:07:19 PM PST 24
Finished Jan 03 02:09:01 PM PST 24
Peak memory 551868 kb
Host smart-18fae357-607a-4b7b-9167-ff38eab1ec7c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32271047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.32271047
Directory /workspace/0.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1560244656
Short name T685
Test name
Test status
Simulation time 56836781 ps
CPU time 5.9 seconds
Started Jan 03 02:07:18 PM PST 24
Finished Jan 03 02:07:31 PM PST 24
Peak memory 552076 kb
Host smart-a5057f72-db98-4746-823d-6c1df1750b72
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560244656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays
.1560244656
Directory /workspace/0.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all.3591537931
Short name T856
Test name
Test status
Simulation time 7123807148 ps
CPU time 263.1 seconds
Started Jan 03 02:07:32 PM PST 24
Finished Jan 03 02:12:04 PM PST 24
Peak memory 555344 kb
Host smart-8218a5b2-eee5-4407-9c8a-7cad45703e3d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591537931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3591537931
Directory /workspace/0.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3773449670
Short name T1802
Test name
Test status
Simulation time 8450560741 ps
CPU time 289.37 seconds
Started Jan 03 02:07:21 PM PST 24
Finished Jan 03 02:12:22 PM PST 24
Peak memory 555024 kb
Host smart-dbcaa7c5-7e0a-4bab-9ac7-8ed4d27af8dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773449670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3773449670
Directory /workspace/0.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3766078965
Short name T142
Test name
Test status
Simulation time 420746798 ps
CPU time 229.03 seconds
Started Jan 03 02:08:05 PM PST 24
Finished Jan 03 02:12:02 PM PST 24
Peak memory 555660 kb
Host smart-efafac59-f507-4548-860f-6fd1affc8791
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766078965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_
with_rand_reset.3766078965
Directory /workspace/0.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3872068417
Short name T1076
Test name
Test status
Simulation time 341499739 ps
CPU time 108.7 seconds
Started Jan 03 02:07:59 PM PST 24
Finished Jan 03 02:09:58 PM PST 24
Peak memory 555588 kb
Host smart-82489f3f-291f-40bd-a3e7-92a483dfb9e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872068417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all
_with_reset_error.3872068417
Directory /workspace/0.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3694308504
Short name T1770
Test name
Test status
Simulation time 93778749 ps
CPU time 11.74 seconds
Started Jan 03 02:07:22 PM PST 24
Finished Jan 03 02:07:46 PM PST 24
Peak memory 553868 kb
Host smart-7e48ca08-70c8-4be5-adc0-4bdcf0bdd257
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694308504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3694308504
Directory /workspace/0.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1687801237
Short name T910
Test name
Test status
Simulation time 9457489997 ps
CPU time 875.9 seconds
Started Jan 03 02:07:54 PM PST 24
Finished Jan 03 02:22:40 PM PST 24
Peak memory 579728 kb
Host smart-edfa3e28-3013-4a96-99ac-e8d0f2fa9615
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687801237 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.1687801237
Directory /workspace/1.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3250704774
Short name T54
Test name
Test status
Simulation time 4968568408 ps
CPU time 185 seconds
Started Jan 03 02:07:03 PM PST 24
Finished Jan 03 02:10:10 PM PST 24
Peak memory 613612 kb
Host smart-291bea9f-a94b-4fe7-b14a-52fd21d23997
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250704774 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.3250704774
Directory /workspace/1.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.chip_csr_rw.1198224267
Short name T1848
Test name
Test status
Simulation time 4367680835 ps
CPU time 301.88 seconds
Started Jan 03 02:07:07 PM PST 24
Finished Jan 03 02:12:10 PM PST 24
Peak memory 580004 kb
Host smart-a495f127-8b3a-4b62-832c-aa84d7a62137
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198224267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.1198224267
Directory /workspace/1.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1069725629
Short name T33
Test name
Test status
Simulation time 9952206576 ps
CPU time 317.42 seconds
Started Jan 03 02:07:54 PM PST 24
Finished Jan 03 02:13:22 PM PST 24
Peak memory 575968 kb
Host smart-69f3c017-f176-4793-89a8-e096e156ac68
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069725629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE
Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.chip_prim_tl_access.1069725629
Directory /workspace/1.chip_prim_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2350600693
Short name T38
Test name
Test status
Simulation time 5774209422 ps
CPU time 279.8 seconds
Started Jan 03 02:07:40 PM PST 24
Finished Jan 03 02:12:32 PM PST 24
Peak memory 577248 kb
Host smart-824c826c-37c5-498e-a3ca-6c4ea01e82ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350600693 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.chip_rv_dm_lc_disabled.2350600693
Directory /workspace/1.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3991360719
Short name T1901
Test name
Test status
Simulation time 27086370748 ps
CPU time 2382.27 seconds
Started Jan 03 02:08:06 PM PST 24
Finished Jan 03 02:47:56 PM PST 24
Peak memory 579996 kb
Host smart-b2ae78ee-bb67-46ac-bde9-f8796be03a42
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991360719 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.3991360719
Directory /workspace/1.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.chip_tl_errors.3287058979
Short name T276
Test name
Test status
Simulation time 3248326078 ps
CPU time 157.7 seconds
Started Jan 03 02:08:07 PM PST 24
Finished Jan 03 02:10:51 PM PST 24
Peak memory 580056 kb
Host smart-4211be0f-bda6-42ee-ac6a-7e0f2ebd14f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287058979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3287058979
Directory /workspace/1.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_access_same_device.1809893826
Short name T1117
Test name
Test status
Simulation time 830154017 ps
CPU time 61.95 seconds
Started Jan 03 02:07:52 PM PST 24
Finished Jan 03 02:09:04 PM PST 24
Peak memory 554952 kb
Host smart-36ac0995-8048-4947-babe-d4109a788d20
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809893826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.
1809893826
Directory /workspace/1.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2981047588
Short name T877
Test name
Test status
Simulation time 83201336128 ps
CPU time 1314.88 seconds
Started Jan 03 02:06:51 PM PST 24
Finished Jan 03 02:28:48 PM PST 24
Peak memory 554332 kb
Host smart-39b74903-d72c-4d6e-8419-37d943bc51cd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981047588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d
evice_slow_rsp.2981047588
Directory /workspace/1.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2572498951
Short name T1451
Test name
Test status
Simulation time 216470236 ps
CPU time 22.4 seconds
Started Jan 03 02:08:19 PM PST 24
Finished Jan 03 02:08:49 PM PST 24
Peak memory 554168 kb
Host smart-3d2cf792-126b-403c-8b70-45dbf9dca08e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572498951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr
.2572498951
Directory /workspace/1.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_error_random.693627520
Short name T1033
Test name
Test status
Simulation time 96984896 ps
CPU time 9.77 seconds
Started Jan 03 02:07:18 PM PST 24
Finished Jan 03 02:07:34 PM PST 24
Peak memory 553824 kb
Host smart-1ec3af31-751c-44f9-a718-9b313f5f317d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693627520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.693627520
Directory /workspace/1.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random.3360970985
Short name T896
Test name
Test status
Simulation time 34868428 ps
CPU time 5.65 seconds
Started Jan 03 02:07:39 PM PST 24
Finished Jan 03 02:07:57 PM PST 24
Peak memory 552064 kb
Host smart-dd84b0eb-852f-483e-ab4e-c01421ccec80
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360970985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.3360970985
Directory /workspace/1.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.4285885701
Short name T1704
Test name
Test status
Simulation time 107060867705 ps
CPU time 1056.56 seconds
Started Jan 03 02:08:05 PM PST 24
Finished Jan 03 02:25:49 PM PST 24
Peak memory 554216 kb
Host smart-f88e0125-916d-47ad-95db-e312d07ba237
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285885701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.4285885701
Directory /workspace/1.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3323421284
Short name T1569
Test name
Test status
Simulation time 54548118810 ps
CPU time 908.56 seconds
Started Jan 03 02:08:04 PM PST 24
Finished Jan 03 02:23:21 PM PST 24
Peak memory 553904 kb
Host smart-4473af34-f657-4d06-b122-d4205ebeee6e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323421284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3323421284
Directory /workspace/1.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.909632858
Short name T620
Test name
Test status
Simulation time 237635955 ps
CPU time 19.52 seconds
Started Jan 03 02:08:05 PM PST 24
Finished Jan 03 02:08:32 PM PST 24
Peak memory 554120 kb
Host smart-84e318e3-c626-42bf-b377-f94a6aa06a86
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909632858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delay
s.909632858
Directory /workspace/1.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_same_source.2049076306
Short name T1030
Test name
Test status
Simulation time 2023917581 ps
CPU time 54.35 seconds
Started Jan 03 02:07:18 PM PST 24
Finished Jan 03 02:08:20 PM PST 24
Peak memory 553844 kb
Host smart-b3faedbc-a46f-427f-9e52-abe06755fe4f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049076306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2049076306
Directory /workspace/1.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke.2585526293
Short name T141
Test name
Test status
Simulation time 42068677 ps
CPU time 5.48 seconds
Started Jan 03 02:08:02 PM PST 24
Finished Jan 03 02:08:17 PM PST 24
Peak memory 552036 kb
Host smart-ebe63f92-500b-4838-a58f-b6f17df95e92
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585526293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.2585526293
Directory /workspace/1.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1412343573
Short name T432
Test name
Test status
Simulation time 5989719762 ps
CPU time 68.78 seconds
Started Jan 03 02:07:42 PM PST 24
Finished Jan 03 02:09:02 PM PST 24
Peak memory 551896 kb
Host smart-d9dd8b85-78d0-474d-a1f8-190f2fb5e513
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412343573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1412343573
Directory /workspace/1.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3112453806
Short name T1378
Test name
Test status
Simulation time 3561622543 ps
CPU time 57.88 seconds
Started Jan 03 02:08:02 PM PST 24
Finished Jan 03 02:09:09 PM PST 24
Peak memory 551808 kb
Host smart-2fbcb8f0-8748-4439-97a6-4d81926656e5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112453806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3112453806
Directory /workspace/1.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2288775942
Short name T535
Test name
Test status
Simulation time 39788654 ps
CPU time 5.38 seconds
Started Jan 03 02:08:03 PM PST 24
Finished Jan 03 02:08:17 PM PST 24
Peak memory 551612 kb
Host smart-de19bd98-af0b-4ba4-9f51-1314d8ad1ebe
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288775942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays
.2288775942
Directory /workspace/1.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all.2496673049
Short name T388
Test name
Test status
Simulation time 245212077 ps
CPU time 10.13 seconds
Started Jan 03 02:07:56 PM PST 24
Finished Jan 03 02:08:17 PM PST 24
Peak memory 551744 kb
Host smart-b656e0c2-f3e1-4dfc-b9df-5a351ec21081
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496673049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2496673049
Directory /workspace/1.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1708973961
Short name T491
Test name
Test status
Simulation time 960382632 ps
CPU time 67.25 seconds
Started Jan 03 02:07:14 PM PST 24
Finished Jan 03 02:08:28 PM PST 24
Peak memory 554936 kb
Host smart-87529475-98b3-4bcf-8a6a-74f947aef8b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708973961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1708973961
Directory /workspace/1.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3967633641
Short name T1625
Test name
Test status
Simulation time 1220461371 ps
CPU time 353.77 seconds
Started Jan 03 02:07:57 PM PST 24
Finished Jan 03 02:14:01 PM PST 24
Peak memory 557396 kb
Host smart-8cd6fe94-f1a9-45e3-985c-b6d71e9c8d42
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967633641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_
with_rand_reset.3967633641
Directory /workspace/1.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3890258118
Short name T1831
Test name
Test status
Simulation time 782080411 ps
CPU time 296.29 seconds
Started Jan 03 02:07:14 PM PST 24
Finished Jan 03 02:12:17 PM PST 24
Peak memory 559004 kb
Host smart-1ae86580-1095-4adc-b90c-ca72943d09b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890258118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all
_with_reset_error.3890258118
Directory /workspace/1.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3876368033
Short name T880
Test name
Test status
Simulation time 166172426 ps
CPU time 19.86 seconds
Started Jan 03 02:07:52 PM PST 24
Finished Jan 03 02:08:23 PM PST 24
Peak memory 554044 kb
Host smart-8534a409-54c5-49a5-8b3a-411855c27880
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876368033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3876368033
Directory /workspace/1.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/10.chip_csr_rw.4195671954
Short name T763
Test name
Test status
Simulation time 4333256437 ps
CPU time 376.17 seconds
Started Jan 03 02:07:57 PM PST 24
Finished Jan 03 02:14:24 PM PST 24
Peak memory 579948 kb
Host smart-b10b58ff-f93b-4a34-b4f2-413b168c3919
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195671954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.4195671954
Directory /workspace/10.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.815187993
Short name T29
Test name
Test status
Simulation time 32205479934 ps
CPU time 2687.13 seconds
Started Jan 03 02:08:05 PM PST 24
Finished Jan 03 02:53:00 PM PST 24
Peak memory 580008 kb
Host smart-5fda61d9-e6ff-410e-96a6-9521c9392c1e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815187993 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.chip_same_csr_outstanding.815187993
Directory /workspace/10.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.chip_tl_errors.2168682480
Short name T280
Test name
Test status
Simulation time 3639636272 ps
CPU time 157.78 seconds
Started Jan 03 02:08:05 PM PST 24
Finished Jan 03 02:10:50 PM PST 24
Peak memory 579988 kb
Host smart-decb3e3c-c6ec-48d7-873e-ad24f47ae893
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168682480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.2168682480
Directory /workspace/10.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_access_same_device.3269606062
Short name T1031
Test name
Test status
Simulation time 712358484 ps
CPU time 31.65 seconds
Started Jan 03 02:07:37 PM PST 24
Finished Jan 03 02:08:20 PM PST 24
Peak memory 553168 kb
Host smart-6b07e8d4-6834-45f1-bd09-10de5916a207
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269606062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device
.3269606062
Directory /workspace/10.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.210358562
Short name T1557
Test name
Test status
Simulation time 92966358617 ps
CPU time 1438.43 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:32:07 PM PST 24
Peak memory 554280 kb
Host smart-8edcbc98-ba9f-4238-af6a-8dfc872dcb6b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210358562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_d
evice_slow_rsp.210358562
Directory /workspace/10.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3565267667
Short name T1576
Test name
Test status
Simulation time 81972750 ps
CPU time 6.4 seconds
Started Jan 03 02:07:20 PM PST 24
Finished Jan 03 02:07:39 PM PST 24
Peak memory 552076 kb
Host smart-09de21d4-ee29-4b67-8299-4f888ed5dc6a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565267667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add
r.3565267667
Directory /workspace/10.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_error_random.4105484903
Short name T1423
Test name
Test status
Simulation time 570459101 ps
CPU time 23.22 seconds
Started Jan 03 02:07:17 PM PST 24
Finished Jan 03 02:07:46 PM PST 24
Peak memory 552968 kb
Host smart-769362f3-b925-4386-ad13-8303565cceec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105484903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4105484903
Directory /workspace/10.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random.2285406461
Short name T981
Test name
Test status
Simulation time 1247397652 ps
CPU time 40.91 seconds
Started Jan 03 02:07:31 PM PST 24
Finished Jan 03 02:08:21 PM PST 24
Peak memory 553820 kb
Host smart-b0a1c24a-4e21-4693-9258-70a9eeac0154
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285406461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.2285406461
Directory /workspace/10.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2764298416
Short name T75
Test name
Test status
Simulation time 63337013679 ps
CPU time 603.88 seconds
Started Jan 03 02:07:16 PM PST 24
Finished Jan 03 02:17:25 PM PST 24
Peak memory 553920 kb
Host smart-5d5f92cc-0341-4c06-92ca-ed3701fcd706
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764298416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2764298416
Directory /workspace/10.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1621238758
Short name T941
Test name
Test status
Simulation time 20262685465 ps
CPU time 354.22 seconds
Started Jan 03 02:07:26 PM PST 24
Finished Jan 03 02:13:31 PM PST 24
Peak memory 554220 kb
Host smart-2be48a18-fb5f-4bf8-a8b4-a2c8e3c333e4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621238758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1621238758
Directory /workspace/10.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.269874253
Short name T151
Test name
Test status
Simulation time 472839898 ps
CPU time 36.74 seconds
Started Jan 03 02:07:42 PM PST 24
Finished Jan 03 02:08:30 PM PST 24
Peak memory 553040 kb
Host smart-773d102f-ad96-4c10-8c3c-8ba271363706
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269874253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_dela
ys.269874253
Directory /workspace/10.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_same_source.2817082646
Short name T169
Test name
Test status
Simulation time 357935049 ps
CPU time 26.42 seconds
Started Jan 03 02:07:35 PM PST 24
Finished Jan 03 02:08:11 PM PST 24
Peak memory 554288 kb
Host smart-677d72b6-1b6f-4ca7-bb58-742eba459b0f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817082646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2817082646
Directory /workspace/10.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke.2340345867
Short name T416
Test name
Test status
Simulation time 206076101 ps
CPU time 8.67 seconds
Started Jan 03 02:08:02 PM PST 24
Finished Jan 03 02:08:20 PM PST 24
Peak memory 551788 kb
Host smart-aa8e0ec1-cdac-4385-86cb-2ca05e4cf6a7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340345867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2340345867
Directory /workspace/10.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2113069429
Short name T1356
Test name
Test status
Simulation time 9054890932 ps
CPU time 89.24 seconds
Started Jan 03 02:08:01 PM PST 24
Finished Jan 03 02:09:40 PM PST 24
Peak memory 551712 kb
Host smart-d9724c59-bcb5-480a-b45b-1a7cdb817227
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113069429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2113069429
Directory /workspace/10.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.507244163
Short name T396
Test name
Test status
Simulation time 5386962169 ps
CPU time 92.05 seconds
Started Jan 03 02:07:25 PM PST 24
Finished Jan 03 02:09:08 PM PST 24
Peak memory 552064 kb
Host smart-0c439497-6323-4d49-a086-6426e66f14ff
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507244163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.507244163
Directory /workspace/10.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.143131793
Short name T1336
Test name
Test status
Simulation time 44345091 ps
CPU time 5.8 seconds
Started Jan 03 02:08:15 PM PST 24
Finished Jan 03 02:08:26 PM PST 24
Peak memory 552044 kb
Host smart-4a8827dd-d7bc-4cc3-9860-e682cd436c78
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143131793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays
.143131793
Directory /workspace/10.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all.1178593295
Short name T1601
Test name
Test status
Simulation time 9151953589 ps
CPU time 291.75 seconds
Started Jan 03 02:07:57 PM PST 24
Finished Jan 03 02:12:59 PM PST 24
Peak memory 555164 kb
Host smart-803b3303-d2c9-4ec4-8869-c9ac279c61ac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178593295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1178593295
Directory /workspace/10.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2434566240
Short name T628
Test name
Test status
Simulation time 10177051506 ps
CPU time 327.25 seconds
Started Jan 03 02:07:26 PM PST 24
Finished Jan 03 02:13:04 PM PST 24
Peak memory 554924 kb
Host smart-d86bddc5-fb6c-4b00-9063-c95b858d04eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434566240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2434566240
Directory /workspace/10.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1951934514
Short name T575
Test name
Test status
Simulation time 47236768 ps
CPU time 12.03 seconds
Started Jan 03 02:07:31 PM PST 24
Finished Jan 03 02:07:52 PM PST 24
Peak memory 552848 kb
Host smart-b9e6ec9f-3348-4889-ac3b-18a86c16dcce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951934514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al
l_with_reset_error.1951934514
Directory /workspace/10.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3541848861
Short name T481
Test name
Test status
Simulation time 246994172 ps
CPU time 27.12 seconds
Started Jan 03 02:08:08 PM PST 24
Finished Jan 03 02:08:40 PM PST 24
Peak memory 553888 kb
Host smart-013d3141-10fb-459c-9376-68ee81daf614
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541848861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3541848861
Directory /workspace/10.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2980469667
Short name T721
Test name
Test status
Simulation time 9892303528 ps
CPU time 397.81 seconds
Started Jan 03 02:08:57 PM PST 24
Finished Jan 03 02:15:37 PM PST 24
Peak memory 621964 kb
Host smart-25e8357b-9593-45d7-9099-5c792191f971
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980469667 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.2980469667
Directory /workspace/11.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.chip_csr_rw.489515296
Short name T62
Test name
Test status
Simulation time 4197235889 ps
CPU time 304.25 seconds
Started Jan 03 02:08:58 PM PST 24
Finished Jan 03 02:14:04 PM PST 24
Peak memory 579896 kb
Host smart-8e80dffe-b4a9-44f3-a5ef-e46f12475f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489515296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.489515296
Directory /workspace/11.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_access_same_device.515779283
Short name T1383
Test name
Test status
Simulation time 509158728 ps
CPU time 35.76 seconds
Started Jan 03 02:08:41 PM PST 24
Finished Jan 03 02:09:24 PM PST 24
Peak memory 553940 kb
Host smart-ae8d6093-c071-4930-8b11-87861c1d6fa8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515779283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.
515779283
Directory /workspace/11.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1706732929
Short name T1417
Test name
Test status
Simulation time 5321568551 ps
CPU time 97.62 seconds
Started Jan 03 02:08:23 PM PST 24
Finished Jan 03 02:10:09 PM PST 24
Peak memory 551896 kb
Host smart-4840410c-1e2b-493a-ada3-0645e772e83e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706732929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_
device_slow_rsp.1706732929
Directory /workspace/11.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3394591431
Short name T618
Test name
Test status
Simulation time 305246237 ps
CPU time 32.48 seconds
Started Jan 03 02:09:03 PM PST 24
Finished Jan 03 02:09:41 PM PST 24
Peak memory 554244 kb
Host smart-88c30bdb-25cf-4025-a267-7ceeddf728d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394591431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add
r.3394591431
Directory /workspace/11.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_error_random.3230510578
Short name T1519
Test name
Test status
Simulation time 413558268 ps
CPU time 32.29 seconds
Started Jan 03 02:08:25 PM PST 24
Finished Jan 03 02:09:06 PM PST 24
Peak memory 553864 kb
Host smart-9c872607-3813-40c3-ba1e-17f7ea7c5832
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230510578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.3230510578
Directory /workspace/11.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random.3537828672
Short name T86
Test name
Test status
Simulation time 574371507 ps
CPU time 20.89 seconds
Started Jan 03 02:08:13 PM PST 24
Finished Jan 03 02:08:36 PM PST 24
Peak memory 554124 kb
Host smart-c564e6a7-d2ee-4441-88a4-bdcccac5b0c2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537828672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.3537828672
Directory /workspace/11.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.408983226
Short name T429
Test name
Test status
Simulation time 21678235398 ps
CPU time 221.35 seconds
Started Jan 03 02:08:20 PM PST 24
Finished Jan 03 02:12:10 PM PST 24
Peak memory 554164 kb
Host smart-2051cbee-c466-4916-8fd9-e9d58ea7dc3c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408983226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.408983226
Directory /workspace/11.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1995723063
Short name T895
Test name
Test status
Simulation time 46316751805 ps
CPU time 755.92 seconds
Started Jan 03 02:08:35 PM PST 24
Finished Jan 03 02:21:18 PM PST 24
Peak memory 553980 kb
Host smart-1dfa232b-7b46-4750-9062-2ef8319eec90
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995723063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1995723063
Directory /workspace/11.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3439659964
Short name T1249
Test name
Test status
Simulation time 317856103 ps
CPU time 28.14 seconds
Started Jan 03 02:08:11 PM PST 24
Finished Jan 03 02:08:42 PM PST 24
Peak memory 553908 kb
Host smart-fc6cae83-6e4c-4cd1-a977-d30785450dce
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439659964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del
ays.3439659964
Directory /workspace/11.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_same_source.1932860224
Short name T1251
Test name
Test status
Simulation time 1694888556 ps
CPU time 47.4 seconds
Started Jan 03 02:08:20 PM PST 24
Finished Jan 03 02:09:16 PM PST 24
Peak memory 554108 kb
Host smart-3307f21f-e008-4859-8379-8e8a34e35c3f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932860224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1932860224
Directory /workspace/11.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke.1821167557
Short name T1803
Test name
Test status
Simulation time 133547254 ps
CPU time 6.82 seconds
Started Jan 03 02:08:22 PM PST 24
Finished Jan 03 02:08:37 PM PST 24
Peak memory 552084 kb
Host smart-42a11e2a-af6c-4931-92c5-17469c75adf2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821167557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1821167557
Directory /workspace/11.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.822387156
Short name T940
Test name
Test status
Simulation time 9491148447 ps
CPU time 101.89 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:10:06 PM PST 24
Peak memory 552044 kb
Host smart-e98ecd18-cae7-4da3-abb1-1eaa38466934
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822387156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.822387156
Directory /workspace/11.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3585288444
Short name T696
Test name
Test status
Simulation time 5421497642 ps
CPU time 89.3 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:09:53 PM PST 24
Peak memory 551652 kb
Host smart-7baee65f-650f-4879-a9bb-b8f1d4447ab1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585288444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3585288444
Directory /workspace/11.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2688199845
Short name T143
Test name
Test status
Simulation time 40804236 ps
CPU time 5.55 seconds
Started Jan 03 02:08:12 PM PST 24
Finished Jan 03 02:08:21 PM PST 24
Peak memory 551736 kb
Host smart-e6c80ca4-3af1-4c99-8f45-608bb10c2710
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688199845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay
s.2688199845
Directory /workspace/11.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all.1828000721
Short name T1746
Test name
Test status
Simulation time 6953942402 ps
CPU time 263.33 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:12:46 PM PST 24
Peak memory 555332 kb
Host smart-d7cbe42d-0c78-41d7-9b3a-5ee9f1a504d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828000721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1828000721
Directory /workspace/11.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.701703722
Short name T1231
Test name
Test status
Simulation time 1280082964 ps
CPU time 97.11 seconds
Started Jan 03 02:08:46 PM PST 24
Finished Jan 03 02:10:29 PM PST 24
Peak memory 555020 kb
Host smart-e6670964-d4ac-42d9-beb3-ec8b892e5edd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701703722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.701703722
Directory /workspace/11.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1630303952
Short name T113
Test name
Test status
Simulation time 10347405568 ps
CPU time 702.68 seconds
Started Jan 03 02:08:52 PM PST 24
Finished Jan 03 02:20:39 PM PST 24
Peak memory 559060 kb
Host smart-52c580f1-7f6e-48e6-9d46-9f2f886a4b17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630303952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all
_with_rand_reset.1630303952
Directory /workspace/11.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.4029026284
Short name T857
Test name
Test status
Simulation time 4820464989 ps
CPU time 315.47 seconds
Started Jan 03 02:08:56 PM PST 24
Finished Jan 03 02:14:14 PM PST 24
Peak memory 558252 kb
Host smart-3c5c37ce-5bc9-4c4d-ba7c-1df77102df6d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029026284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al
l_with_reset_error.4029026284
Directory /workspace/11.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1531806544
Short name T1429
Test name
Test status
Simulation time 214006975 ps
CPU time 28.71 seconds
Started Jan 03 02:08:24 PM PST 24
Finished Jan 03 02:09:00 PM PST 24
Peak memory 553912 kb
Host smart-5ae2e582-f324-4604-883a-36cb51064483
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531806544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1531806544
Directory /workspace/11.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3112901269
Short name T852
Test name
Test status
Simulation time 5499665250 ps
CPU time 184.82 seconds
Started Jan 03 02:07:31 PM PST 24
Finished Jan 03 02:10:45 PM PST 24
Peak memory 611796 kb
Host smart-76d9c0f5-fc8e-4cb9-b1ec-2966602dc43c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112901269 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.3112901269
Directory /workspace/12.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.chip_csr_rw.5444930
Short name T1326
Test name
Test status
Simulation time 5504230385 ps
CPU time 467.9 seconds
Started Jan 03 02:07:39 PM PST 24
Finished Jan 03 02:15:39 PM PST 24
Peak memory 579984 kb
Host smart-c8be517e-85ec-422c-bd11-ac40a77eb827
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5444930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.5444930
Directory /workspace/12.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3085597735
Short name T989
Test name
Test status
Simulation time 14906396369 ps
CPU time 1456.9 seconds
Started Jan 03 02:08:04 PM PST 24
Finished Jan 03 02:32:29 PM PST 24
Peak memory 579956 kb
Host smart-42f0a9d3-c3bf-4ae1-88f6-362a04ed2af1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085597735 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.3085597735
Directory /workspace/12.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.chip_tl_errors.2704156398
Short name T273
Test name
Test status
Simulation time 3665403326 ps
CPU time 187.89 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:10:56 PM PST 24
Peak memory 580012 kb
Host smart-4d06dab7-e32d-4058-b201-940b46f9404c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704156398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.2704156398
Directory /workspace/12.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_access_same_device.3436965058
Short name T1084
Test name
Test status
Simulation time 3025756738 ps
CPU time 118.42 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:09:46 PM PST 24
Peak memory 553932 kb
Host smart-c280d46e-063b-4323-8720-fd911eb130cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436965058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device
.3436965058
Directory /workspace/12.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3375220202
Short name T854
Test name
Test status
Simulation time 59604990705 ps
CPU time 918.04 seconds
Started Jan 03 02:08:08 PM PST 24
Finished Jan 03 02:23:31 PM PST 24
Peak memory 555240 kb
Host smart-cbdca8f6-f61c-43d4-9f07-257b54ae7a66
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375220202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_
device_slow_rsp.3375220202
Directory /workspace/12.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2268567106
Short name T426
Test name
Test status
Simulation time 231413672 ps
CPU time 24.66 seconds
Started Jan 03 02:07:39 PM PST 24
Finished Jan 03 02:08:16 PM PST 24
Peak memory 553976 kb
Host smart-fbf0b3ab-7bac-4e9d-9df9-012bff61e305
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268567106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add
r.2268567106
Directory /workspace/12.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_error_random.959690905
Short name T962
Test name
Test status
Simulation time 1425087904 ps
CPU time 49.52 seconds
Started Jan 03 02:07:27 PM PST 24
Finished Jan 03 02:08:27 PM PST 24
Peak memory 554060 kb
Host smart-341e58cf-d179-4864-a4ff-978ae8cfe6aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959690905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.959690905
Directory /workspace/12.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random.595649013
Short name T231
Test name
Test status
Simulation time 1887061140 ps
CPU time 58.93 seconds
Started Jan 03 02:08:03 PM PST 24
Finished Jan 03 02:09:11 PM PST 24
Peak memory 554116 kb
Host smart-70dfbfe2-1e7d-4397-a31d-3f1068c217e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595649013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.595649013
Directory /workspace/12.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2129846952
Short name T1734
Test name
Test status
Simulation time 10798327373 ps
CPU time 108.92 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:09:37 PM PST 24
Peak memory 553152 kb
Host smart-9687676e-062b-45d6-b423-18b76fdc7c92
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129846952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2129846952
Directory /workspace/12.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.140486536
Short name T757
Test name
Test status
Simulation time 45811352034 ps
CPU time 781.08 seconds
Started Jan 03 02:07:37 PM PST 24
Finished Jan 03 02:20:49 PM PST 24
Peak memory 554184 kb
Host smart-95ccbed8-a326-421b-89c5-838e1fc9bab1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140486536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.140486536
Directory /workspace/12.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2402504398
Short name T1851
Test name
Test status
Simulation time 39036576 ps
CPU time 6.17 seconds
Started Jan 03 02:07:33 PM PST 24
Finished Jan 03 02:07:49 PM PST 24
Peak memory 552040 kb
Host smart-4f4482a9-1fd1-480a-a927-0c1bad28b62d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402504398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del
ays.2402504398
Directory /workspace/12.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_same_source.3713209985
Short name T1662
Test name
Test status
Simulation time 1373366359 ps
CPU time 37.88 seconds
Started Jan 03 02:07:44 PM PST 24
Finished Jan 03 02:08:34 PM PST 24
Peak memory 554208 kb
Host smart-66c802f7-b9b3-48a6-8c3a-7c188795c5bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713209985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3713209985
Directory /workspace/12.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke.3635141712
Short name T968
Test name
Test status
Simulation time 189424327 ps
CPU time 7.75 seconds
Started Jan 03 02:07:44 PM PST 24
Finished Jan 03 02:08:04 PM PST 24
Peak memory 551704 kb
Host smart-4154e503-a150-405f-8d59-ebad2984958d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635141712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3635141712
Directory /workspace/12.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.109747015
Short name T1058
Test name
Test status
Simulation time 7336142053 ps
CPU time 77.43 seconds
Started Jan 03 02:07:16 PM PST 24
Finished Jan 03 02:08:38 PM PST 24
Peak memory 552112 kb
Host smart-6c24b71f-9075-497f-8e95-61f5502618af
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109747015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.109747015
Directory /workspace/12.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.481946976
Short name T1723
Test name
Test status
Simulation time 4431002515 ps
CPU time 74.71 seconds
Started Jan 03 02:07:20 PM PST 24
Finished Jan 03 02:08:47 PM PST 24
Peak memory 552132 kb
Host smart-da7f6538-d5d3-4ee9-8f35-5705fc43b7fc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481946976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.481946976
Directory /workspace/12.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3525429314
Short name T1182
Test name
Test status
Simulation time 47568733 ps
CPU time 5.92 seconds
Started Jan 03 02:07:17 PM PST 24
Finished Jan 03 02:07:27 PM PST 24
Peak memory 551820 kb
Host smart-c4a9c788-2482-48f2-8f36-df99d2418f4e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525429314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay
s.3525429314
Directory /workspace/12.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all.4047732397
Short name T1007
Test name
Test status
Simulation time 8683799039 ps
CPU time 328 seconds
Started Jan 03 02:08:01 PM PST 24
Finished Jan 03 02:13:38 PM PST 24
Peak memory 555352 kb
Host smart-e521f0cb-de31-47e6-9e4a-2274b4aaa492
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047732397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.4047732397
Directory /workspace/12.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2701207858
Short name T1653
Test name
Test status
Simulation time 298125576 ps
CPU time 25.44 seconds
Started Jan 03 02:08:04 PM PST 24
Finished Jan 03 02:08:37 PM PST 24
Peak memory 553888 kb
Host smart-8cf2cf27-44e2-4f97-85cc-75ebce8f4321
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701207858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2701207858
Directory /workspace/12.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2124200028
Short name T351
Test name
Test status
Simulation time 32218345988 ps
CPU time 1304.84 seconds
Started Jan 03 02:07:32 PM PST 24
Finished Jan 03 02:29:26 PM PST 24
Peak memory 557472 kb
Host smart-ad49ca56-57e9-449a-84a0-8c7b55cd5cc8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124200028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all
_with_rand_reset.2124200028
Directory /workspace/12.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2238918397
Short name T531
Test name
Test status
Simulation time 144056660 ps
CPU time 55.13 seconds
Started Jan 03 02:07:55 PM PST 24
Finished Jan 03 02:09:00 PM PST 24
Peak memory 555288 kb
Host smart-f05df107-578c-4d6b-8116-26667db8da82
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238918397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al
l_with_reset_error.2238918397
Directory /workspace/12.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.727005189
Short name T1206
Test name
Test status
Simulation time 266014671 ps
CPU time 28.91 seconds
Started Jan 03 02:07:48 PM PST 24
Finished Jan 03 02:08:28 PM PST 24
Peak memory 553956 kb
Host smart-79b3d1b7-5003-46ad-a4c7-d396b703fe57
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727005189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.727005189
Directory /workspace/12.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1980136774
Short name T350
Test name
Test status
Simulation time 9700452232 ps
CPU time 402.84 seconds
Started Jan 03 02:08:40 PM PST 24
Finished Jan 03 02:15:30 PM PST 24
Peak memory 619792 kb
Host smart-25b2747b-9ad2-4a85-b88a-8ccbd292c552
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980136774 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.1980136774
Directory /workspace/13.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.chip_csr_rw.1333488086
Short name T1079
Test name
Test status
Simulation time 6016214469 ps
CPU time 655.99 seconds
Started Jan 03 02:08:25 PM PST 24
Finished Jan 03 02:19:30 PM PST 24
Peak memory 579992 kb
Host smart-b2d90193-a66b-4c23-88fc-1737c48cea85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333488086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.1333488086
Directory /workspace/13.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2596271966
Short name T1062
Test name
Test status
Simulation time 31338194956 ps
CPU time 3450.43 seconds
Started Jan 03 02:07:59 PM PST 24
Finished Jan 03 03:05:40 PM PST 24
Peak memory 580052 kb
Host smart-00b7ad2b-7199-4697-bc00-b2056788e3a4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596271966 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.2596271966
Directory /workspace/13.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.chip_tl_errors.732092045
Short name T269
Test name
Test status
Simulation time 3749694936 ps
CPU time 311.57 seconds
Started Jan 03 02:08:02 PM PST 24
Finished Jan 03 02:13:23 PM PST 24
Peak memory 580048 kb
Host smart-f511fdff-7937-4868-8c76-65225a7f8b2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732092045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.732092045
Directory /workspace/13.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_access_same_device.2801978953
Short name T670
Test name
Test status
Simulation time 749970732 ps
CPU time 56.6 seconds
Started Jan 03 02:08:14 PM PST 24
Finished Jan 03 02:09:13 PM PST 24
Peak memory 554100 kb
Host smart-ec0ebd00-cebc-48b3-a6cd-23dfa6e3c32e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801978953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device
.2801978953
Directory /workspace/13.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1181339447
Short name T375
Test name
Test status
Simulation time 308160996 ps
CPU time 13.3 seconds
Started Jan 03 02:08:19 PM PST 24
Finished Jan 03 02:08:40 PM PST 24
Peak memory 554092 kb
Host smart-2fd75d6b-d4ea-4cf4-b361-9c44a0c807e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181339447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add
r.1181339447
Directory /workspace/13.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_error_random.3816800784
Short name T994
Test name
Test status
Simulation time 864142051 ps
CPU time 29.04 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:08:51 PM PST 24
Peak memory 554116 kb
Host smart-c4b70a82-1f7a-4218-b4d1-976fd02b57ac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816800784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3816800784
Directory /workspace/13.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random.3550576484
Short name T400
Test name
Test status
Simulation time 130868433 ps
CPU time 7.44 seconds
Started Jan 03 02:08:14 PM PST 24
Finished Jan 03 02:08:24 PM PST 24
Peak memory 552044 kb
Host smart-49d37831-09af-42b6-8645-8028ec0d0be2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550576484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.3550576484
Directory /workspace/13.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3325946962
Short name T1528
Test name
Test status
Simulation time 59190337958 ps
CPU time 631.65 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:18:56 PM PST 24
Peak memory 554080 kb
Host smart-8b1bbbb3-d266-4d57-b8a9-5b523d00f928
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325946962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.3325946962
Directory /workspace/13.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2818472130
Short name T101
Test name
Test status
Simulation time 26013657115 ps
CPU time 455.08 seconds
Started Jan 03 02:08:03 PM PST 24
Finished Jan 03 02:15:47 PM PST 24
Peak memory 554188 kb
Host smart-9a2c3aaa-664e-4c75-aeef-97fab31c585b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818472130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2818472130
Directory /workspace/13.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1523056534
Short name T1574
Test name
Test status
Simulation time 280824703 ps
CPU time 25.09 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:08:49 PM PST 24
Peak memory 554136 kb
Host smart-947c8cd1-ff3c-4061-bbc8-116be3e27ed7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523056534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del
ays.1523056534
Directory /workspace/13.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_same_source.145892661
Short name T908
Test name
Test status
Simulation time 124473875 ps
CPU time 11.03 seconds
Started Jan 03 02:08:35 PM PST 24
Finished Jan 03 02:08:53 PM PST 24
Peak memory 553084 kb
Host smart-60e33140-8bfe-43f1-b619-e32c982feafc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145892661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.145892661
Directory /workspace/13.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke.4161269726
Short name T1882
Test name
Test status
Simulation time 40304723 ps
CPU time 5.42 seconds
Started Jan 03 02:08:11 PM PST 24
Finished Jan 03 02:08:20 PM PST 24
Peak memory 552052 kb
Host smart-b2ea42b5-8992-4932-9bfd-2eb6021daf26
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161269726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.4161269726
Directory /workspace/13.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2894877274
Short name T1520
Test name
Test status
Simulation time 6555721617 ps
CPU time 69 seconds
Started Jan 03 02:07:43 PM PST 24
Finished Jan 03 02:09:04 PM PST 24
Peak memory 552116 kb
Host smart-beb87fca-6981-4bfb-92b3-62686e98c954
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894877274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2894877274
Directory /workspace/13.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1114511708
Short name T1268
Test name
Test status
Simulation time 5292527451 ps
CPU time 86.19 seconds
Started Jan 03 02:08:03 PM PST 24
Finished Jan 03 02:09:38 PM PST 24
Peak memory 551700 kb
Host smart-af8eb240-8a58-4da0-9f05-5c81f807cede
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114511708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1114511708
Directory /workspace/13.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2174514969
Short name T487
Test name
Test status
Simulation time 54148997 ps
CPU time 6.47 seconds
Started Jan 03 02:07:25 PM PST 24
Finished Jan 03 02:07:43 PM PST 24
Peak memory 551996 kb
Host smart-5cb71f20-f345-4480-b345-7d400b343966
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174514969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay
s.2174514969
Directory /workspace/13.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all.112949067
Short name T408
Test name
Test status
Simulation time 5848646 ps
CPU time 3.5 seconds
Started Jan 03 02:08:25 PM PST 24
Finished Jan 03 02:08:37 PM PST 24
Peak memory 543284 kb
Host smart-e52ff3a3-a95f-412a-8899-d5ff007d08bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112949067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.112949067
Directory /workspace/13.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1678101560
Short name T1829
Test name
Test status
Simulation time 3823651487 ps
CPU time 111.65 seconds
Started Jan 03 02:08:13 PM PST 24
Finished Jan 03 02:10:08 PM PST 24
Peak memory 555000 kb
Host smart-ee840e4f-9ab6-4a13-9f94-5473227b1e50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678101560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1678101560
Directory /workspace/13.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1306790054
Short name T788
Test name
Test status
Simulation time 495756499 ps
CPU time 176.94 seconds
Started Jan 03 02:08:08 PM PST 24
Finished Jan 03 02:11:10 PM PST 24
Peak memory 556084 kb
Host smart-347b19f6-4fab-4cce-aa1b-1561cd90f733
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306790054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all
_with_rand_reset.1306790054
Directory /workspace/13.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.125760903
Short name T1834
Test name
Test status
Simulation time 9406490 ps
CPU time 17.79 seconds
Started Jan 03 02:08:19 PM PST 24
Finished Jan 03 02:08:44 PM PST 24
Peak memory 553080 kb
Host smart-20a1ba33-a739-4fff-8651-1a14885598cd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125760903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all
_with_reset_error.125760903
Directory /workspace/13.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2699467320
Short name T996
Test name
Test status
Simulation time 865046666 ps
CPU time 32.41 seconds
Started Jan 03 02:08:14 PM PST 24
Finished Jan 03 02:08:51 PM PST 24
Peak memory 554276 kb
Host smart-e6c37dfc-324c-4881-a98a-89b6d36d8240
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699467320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2699467320
Directory /workspace/13.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.1758221367
Short name T81
Test name
Test status
Simulation time 7304003696 ps
CPU time 290.25 seconds
Started Jan 03 02:07:59 PM PST 24
Finished Jan 03 02:12:59 PM PST 24
Peak memory 628316 kb
Host smart-121a9cf4-4132-4411-a19a-a5ce4de61c86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758221367 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.1758221367
Directory /workspace/14.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.chip_csr_rw.2384280599
Short name T1135
Test name
Test status
Simulation time 6095063674 ps
CPU time 540.57 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:17:09 PM PST 24
Peak memory 580024 kb
Host smart-56223e67-524a-4ede-be1d-05bd690d5a18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384280599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.2384280599
Directory /workspace/14.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2913075948
Short name T1264
Test name
Test status
Simulation time 15637303267 ps
CPU time 1357.56 seconds
Started Jan 03 02:08:35 PM PST 24
Finished Jan 03 02:31:20 PM PST 24
Peak memory 580040 kb
Host smart-38b35817-f4b4-449d-8a8a-1b9ef6467971
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913075948 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.2913075948
Directory /workspace/14.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.chip_tl_errors.711650312
Short name T281
Test name
Test status
Simulation time 5627424962 ps
CPU time 515.89 seconds
Started Jan 03 02:08:43 PM PST 24
Finished Jan 03 02:17:26 PM PST 24
Peak memory 580008 kb
Host smart-b3333dd3-d4f3-4c85-9055-6646d60c910e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711650312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.711650312
Directory /workspace/14.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_access_same_device.2374111151
Short name T1778
Test name
Test status
Simulation time 2833687554 ps
CPU time 116.47 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:09:43 PM PST 24
Peak memory 554324 kb
Host smart-cd129dc8-d6b8-4842-b736-edcda15d5719
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374111151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device
.2374111151
Directory /workspace/14.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.4022642654
Short name T988
Test name
Test status
Simulation time 131893836247 ps
CPU time 1990.78 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:41:19 PM PST 24
Peak memory 555248 kb
Host smart-e3e5ce9a-7e9e-45d1-adef-01d86003ef0d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022642654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_
device_slow_rsp.4022642654
Directory /workspace/14.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.4150211313
Short name T959
Test name
Test status
Simulation time 1047350512 ps
CPU time 39.34 seconds
Started Jan 03 02:07:39 PM PST 24
Finished Jan 03 02:08:30 PM PST 24
Peak memory 552888 kb
Host smart-bec9ce54-4341-4bce-8612-f4cc4b357a30
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150211313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add
r.4150211313
Directory /workspace/14.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_error_random.1122501609
Short name T868
Test name
Test status
Simulation time 1348806039 ps
CPU time 42.9 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:08:29 PM PST 24
Peak memory 554100 kb
Host smart-ee48e2a8-78ee-4c67-944c-107990d23609
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122501609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1122501609
Directory /workspace/14.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random.78880408
Short name T180
Test name
Test status
Simulation time 612301063 ps
CPU time 51.27 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:08:37 PM PST 24
Peak memory 553968 kb
Host smart-fa086e0d-1831-4b85-af4b-04dc9feabe43
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78880408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.78880408
Directory /workspace/14.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1375808464
Short name T1029
Test name
Test status
Simulation time 80276426228 ps
CPU time 865.31 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:22:11 PM PST 24
Peak memory 554020 kb
Host smart-4a06e8a8-1324-4728-83ec-6cf8326ea08c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375808464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1375808464
Directory /workspace/14.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1758888369
Short name T1195
Test name
Test status
Simulation time 59076483453 ps
CPU time 917.03 seconds
Started Jan 03 02:07:44 PM PST 24
Finished Jan 03 02:23:13 PM PST 24
Peak memory 553976 kb
Host smart-7f057ccf-c51d-42a6-892a-4795ca7277ed
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758888369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1758888369
Directory /workspace/14.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3518487609
Short name T1658
Test name
Test status
Simulation time 520551330 ps
CPU time 42.18 seconds
Started Jan 03 02:07:43 PM PST 24
Finished Jan 03 02:08:37 PM PST 24
Peak memory 553876 kb
Host smart-712fcc17-e1e9-4176-9b68-1504ea1c4570
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518487609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del
ays.3518487609
Directory /workspace/14.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_same_source.2822477505
Short name T268
Test name
Test status
Simulation time 568928448 ps
CPU time 36.07 seconds
Started Jan 03 02:07:29 PM PST 24
Finished Jan 03 02:08:15 PM PST 24
Peak memory 554180 kb
Host smart-50063292-f44a-449e-bb1c-1b05781992f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822477505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2822477505
Directory /workspace/14.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke.3210223026
Short name T1111
Test name
Test status
Simulation time 48469144 ps
CPU time 6.15 seconds
Started Jan 03 02:08:19 PM PST 24
Finished Jan 03 02:08:32 PM PST 24
Peak memory 551832 kb
Host smart-86361f33-7f9a-43b8-8598-deabb093765e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210223026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3210223026
Directory /workspace/14.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.583362754
Short name T479
Test name
Test status
Simulation time 9277644063 ps
CPU time 91.77 seconds
Started Jan 03 02:08:53 PM PST 24
Finished Jan 03 02:10:28 PM PST 24
Peak memory 551888 kb
Host smart-5e007257-7a06-400e-93e4-9c5156a5d121
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583362754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.583362754
Directory /workspace/14.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.3423996633
Short name T1754
Test name
Test status
Simulation time 6056198196 ps
CPU time 107.76 seconds
Started Jan 03 02:08:54 PM PST 24
Finished Jan 03 02:10:45 PM PST 24
Peak memory 552096 kb
Host smart-c8a57a09-429a-45a9-bff2-ea56f733c6db
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423996633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3423996633
Directory /workspace/14.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3958185564
Short name T1344
Test name
Test status
Simulation time 45806583 ps
CPU time 5.76 seconds
Started Jan 03 02:08:47 PM PST 24
Finished Jan 03 02:08:58 PM PST 24
Peak memory 551660 kb
Host smart-706108b5-a778-4ac7-8cbb-064495d5002e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958185564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay
s.3958185564
Directory /workspace/14.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all.34338296
Short name T125
Test name
Test status
Simulation time 6834802927 ps
CPU time 256.47 seconds
Started Jan 03 02:07:55 PM PST 24
Finished Jan 03 02:12:22 PM PST 24
Peak memory 554212 kb
Host smart-c2e740a7-ea49-4599-a62e-ca3ac5ddf433
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34338296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.34338296
Directory /workspace/14.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3829771089
Short name T1624
Test name
Test status
Simulation time 1426937383 ps
CPU time 41.43 seconds
Started Jan 03 02:07:48 PM PST 24
Finished Jan 03 02:08:40 PM PST 24
Peak memory 552872 kb
Host smart-207ce4ec-251c-4f8c-bbe0-d0bd40b4a072
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829771089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3829771089
Directory /workspace/14.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.309253375
Short name T943
Test name
Test status
Simulation time 870645063 ps
CPU time 39.77 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:08:27 PM PST 24
Peak memory 553968 kb
Host smart-79d16009-e145-476f-9bee-ce7ebcd1f12f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309253375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.309253375
Directory /workspace/14.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3870711233
Short name T1303
Test name
Test status
Simulation time 5670175572 ps
CPU time 207.48 seconds
Started Jan 03 02:08:18 PM PST 24
Finished Jan 03 02:11:53 PM PST 24
Peak memory 612752 kb
Host smart-bf71f705-608e-441f-91de-71bc75d8d0e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870711233 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.3870711233
Directory /workspace/15.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.chip_csr_rw.1581006184
Short name T976
Test name
Test status
Simulation time 5336775776 ps
CPU time 408.77 seconds
Started Jan 03 02:08:15 PM PST 24
Finished Jan 03 02:15:09 PM PST 24
Peak memory 579948 kb
Host smart-87cf9dc8-3b3c-42f8-ac29-f3471274e431
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581006184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.1581006184
Directory /workspace/15.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.chip_tl_errors.2266668405
Short name T1609
Test name
Test status
Simulation time 3332966567 ps
CPU time 122.95 seconds
Started Jan 03 02:07:22 PM PST 24
Finished Jan 03 02:09:37 PM PST 24
Peak memory 580060 kb
Host smart-03ae0155-2baf-4506-9e42-8a7d8599eb80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266668405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.2266668405
Directory /workspace/15.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_access_same_device.2219230180
Short name T298
Test name
Test status
Simulation time 1010690332 ps
CPU time 40.76 seconds
Started Jan 03 02:08:24 PM PST 24
Finished Jan 03 02:09:13 PM PST 24
Peak memory 554140 kb
Host smart-d8ac1a13-3878-48ea-b117-f981c98b8fb6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219230180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device
.2219230180
Directory /workspace/15.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.1414418213
Short name T290
Test name
Test status
Simulation time 81903237874 ps
CPU time 1360.88 seconds
Started Jan 03 02:08:14 PM PST 24
Finished Jan 03 02:30:58 PM PST 24
Peak memory 554988 kb
Host smart-e33968aa-b126-4fe9-99a4-d845d6201c98
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414418213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_
device_slow_rsp.1414418213
Directory /workspace/15.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.632341215
Short name T1856
Test name
Test status
Simulation time 1363671714 ps
CPU time 55.62 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:09:19 PM PST 24
Peak memory 553872 kb
Host smart-07b9b03e-89ad-441c-a7f1-aedaebbb57c7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632341215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr
.632341215
Directory /workspace/15.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_error_random.1952735596
Short name T395
Test name
Test status
Simulation time 526149869 ps
CPU time 20.08 seconds
Started Jan 03 02:08:22 PM PST 24
Finished Jan 03 02:08:51 PM PST 24
Peak memory 552876 kb
Host smart-7bf85347-8fe7-4044-86fc-100858272e7c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952735596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1952735596
Directory /workspace/15.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random.678177092
Short name T393
Test name
Test status
Simulation time 579814151 ps
CPU time 19.99 seconds
Started Jan 03 02:08:02 PM PST 24
Finished Jan 03 02:08:31 PM PST 24
Peak memory 553852 kb
Host smart-e19fabb0-bb83-45dc-aa14-d962909eb015
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678177092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.678177092
Directory /workspace/15.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.1274108619
Short name T1402
Test name
Test status
Simulation time 5430701568 ps
CPU time 58.83 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:09:20 PM PST 24
Peak memory 551860 kb
Host smart-081379a6-c3f7-4700-b0ac-06a10b90aab9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274108619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1274108619
Directory /workspace/15.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1256965392
Short name T634
Test name
Test status
Simulation time 28661069510 ps
CPU time 504.06 seconds
Started Jan 03 02:07:53 PM PST 24
Finished Jan 03 02:16:27 PM PST 24
Peak memory 553824 kb
Host smart-fa637a10-9ab7-420d-8163-4274dc87fda5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256965392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1256965392
Directory /workspace/15.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.511224838
Short name T1376
Test name
Test status
Simulation time 165599519 ps
CPU time 16.17 seconds
Started Jan 03 02:07:57 PM PST 24
Finished Jan 03 02:08:24 PM PST 24
Peak memory 553876 kb
Host smart-1d2e3c37-f216-478a-82de-e4641c93b22a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511224838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_dela
ys.511224838
Directory /workspace/15.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_same_source.380830800
Short name T924
Test name
Test status
Simulation time 2313184701 ps
CPU time 62.43 seconds
Started Jan 03 02:08:20 PM PST 24
Finished Jan 03 02:09:31 PM PST 24
Peak memory 554268 kb
Host smart-45856e9b-b224-439a-94f7-5fe651ce9df7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380830800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.380830800
Directory /workspace/15.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke.220113222
Short name T527
Test name
Test status
Simulation time 48171581 ps
CPU time 5.98 seconds
Started Jan 03 02:08:07 PM PST 24
Finished Jan 03 02:08:19 PM PST 24
Peak memory 552056 kb
Host smart-46d59cc3-1785-4996-8c4e-dc92f9e4da95
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220113222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.220113222
Directory /workspace/15.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.953086706
Short name T582
Test name
Test status
Simulation time 5421978355 ps
CPU time 57.02 seconds
Started Jan 03 02:07:59 PM PST 24
Finished Jan 03 02:09:06 PM PST 24
Peak memory 552144 kb
Host smart-658a8101-f35e-4b29-9a3f-ee8763ec64aa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953086706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.953086706
Directory /workspace/15.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.456758826
Short name T1074
Test name
Test status
Simulation time 6910172806 ps
CPU time 112.97 seconds
Started Jan 03 02:07:56 PM PST 24
Finished Jan 03 02:10:00 PM PST 24
Peak memory 551860 kb
Host smart-5246f953-020c-4ef0-a2f8-bf9b728f147f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456758826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.456758826
Directory /workspace/15.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.880781354
Short name T922
Test name
Test status
Simulation time 43233435 ps
CPU time 5.71 seconds
Started Jan 03 02:07:42 PM PST 24
Finished Jan 03 02:07:59 PM PST 24
Peak memory 552164 kb
Host smart-8ea1e4b4-5adb-4491-996f-b42e16e11f17
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880781354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays
.880781354
Directory /workspace/15.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all.3578329751
Short name T729
Test name
Test status
Simulation time 371674613 ps
CPU time 36.89 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:09:01 PM PST 24
Peak memory 555044 kb
Host smart-bdefd541-2a43-4948-8a2b-65f3e99ab87c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578329751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3578329751
Directory /workspace/15.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.4191788904
Short name T1450
Test name
Test status
Simulation time 2877365177 ps
CPU time 111.29 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:10:14 PM PST 24
Peak memory 555336 kb
Host smart-beae6f26-3994-4cd1-957d-632b945c46eb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191788904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.4191788904
Directory /workspace/15.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3949010529
Short name T1584
Test name
Test status
Simulation time 101634652 ps
CPU time 21.02 seconds
Started Jan 03 02:07:51 PM PST 24
Finished Jan 03 02:08:22 PM PST 24
Peak memory 553860 kb
Host smart-ad2ef39b-435d-46f2-8146-2f235c645226
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949010529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all
_with_rand_reset.3949010529
Directory /workspace/15.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3760874758
Short name T1726
Test name
Test status
Simulation time 130586210 ps
CPU time 38.51 seconds
Started Jan 03 02:08:19 PM PST 24
Finished Jan 03 02:09:05 PM PST 24
Peak memory 554984 kb
Host smart-48de15de-5783-41cd-8c81-00c7e3b20902
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760874758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al
l_with_reset_error.3760874758
Directory /workspace/15.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.231819349
Short name T1055
Test name
Test status
Simulation time 1400606655 ps
CPU time 56.44 seconds
Started Jan 03 02:07:56 PM PST 24
Finished Jan 03 02:09:03 PM PST 24
Peak memory 553100 kb
Host smart-97757fbb-48db-439b-94b7-a299397703f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231819349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.231819349
Directory /workspace/15.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.2253871184
Short name T51
Test name
Test status
Simulation time 5076268240 ps
CPU time 203.64 seconds
Started Jan 03 02:07:29 PM PST 24
Finished Jan 03 02:11:02 PM PST 24
Peak memory 613800 kb
Host smart-7ee754aa-c79b-49ff-b16f-c79eb8471adb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253871184 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.2253871184
Directory /workspace/16.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.chip_csr_rw.152944441
Short name T22
Test name
Test status
Simulation time 3596696288 ps
CPU time 270.57 seconds
Started Jan 03 02:07:59 PM PST 24
Finished Jan 03 02:12:40 PM PST 24
Peak memory 580004 kb
Host smart-7eeba849-6946-46ae-b17d-b380365b1702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152944441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.152944441
Directory /workspace/16.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.3386394267
Short name T1295
Test name
Test status
Simulation time 16123280150 ps
CPU time 1552.26 seconds
Started Jan 03 02:08:34 PM PST 24
Finished Jan 03 02:34:34 PM PST 24
Peak memory 580032 kb
Host smart-35c32b91-f905-4bc3-81e2-6b72df929b59
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386394267 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.3386394267
Directory /workspace/16.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.chip_tl_errors.1800888683
Short name T227
Test name
Test status
Simulation time 2328735590 ps
CPU time 116.53 seconds
Started Jan 03 02:08:36 PM PST 24
Finished Jan 03 02:10:40 PM PST 24
Peak memory 578052 kb
Host smart-1d94bf0e-a707-4cb0-aeed-0e0f55abe6eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800888683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.1800888683
Directory /workspace/16.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_access_same_device.1067563705
Short name T1023
Test name
Test status
Simulation time 317570411 ps
CPU time 23.02 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:08:32 PM PST 24
Peak memory 554136 kb
Host smart-79fc2068-b818-43e0-a543-eef0c70c9eda
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067563705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device
.1067563705
Directory /workspace/16.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.792630922
Short name T1352
Test name
Test status
Simulation time 166513972838 ps
CPU time 2772.3 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:54:37 PM PST 24
Peak memory 554980 kb
Host smart-66f6612d-453e-41cb-a8bd-ada5235e3631
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792630922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_d
evice_slow_rsp.792630922
Directory /workspace/16.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1491774248
Short name T380
Test name
Test status
Simulation time 338124862 ps
CPU time 14.42 seconds
Started Jan 03 02:07:34 PM PST 24
Finished Jan 03 02:07:59 PM PST 24
Peak memory 552856 kb
Host smart-332fea1d-17c1-459a-bbb3-628ef273369b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491774248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add
r.1491774248
Directory /workspace/16.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_error_random.2351740552
Short name T1446
Test name
Test status
Simulation time 575893928 ps
CPU time 20.69 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:08:29 PM PST 24
Peak memory 554136 kb
Host smart-8d409f3a-e165-4931-9901-9e8758cb6f64
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351740552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2351740552
Directory /workspace/16.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random.3665024608
Short name T1290
Test name
Test status
Simulation time 353221113 ps
CPU time 29.16 seconds
Started Jan 03 02:08:24 PM PST 24
Finished Jan 03 02:09:02 PM PST 24
Peak memory 553904 kb
Host smart-9f8df354-116a-4b40-850d-06348b5813e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665024608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.3665024608
Directory /workspace/16.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.3654217551
Short name T93
Test name
Test status
Simulation time 100707050352 ps
CPU time 1060.13 seconds
Started Jan 03 02:08:30 PM PST 24
Finished Jan 03 02:26:19 PM PST 24
Peak memory 554260 kb
Host smart-a665cf91-c378-4fef-b89b-68babe894fc8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654217551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3654217551
Directory /workspace/16.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.1416130289
Short name T653
Test name
Test status
Simulation time 45777083364 ps
CPU time 843.67 seconds
Started Jan 03 02:08:58 PM PST 24
Finished Jan 03 02:23:05 PM PST 24
Peak memory 553940 kb
Host smart-a348b735-c1f8-4fea-980e-7fce0adfd3d7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416130289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1416130289
Directory /workspace/16.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.2046272219
Short name T94
Test name
Test status
Simulation time 145935916 ps
CPU time 15.5 seconds
Started Jan 03 02:08:00 PM PST 24
Finished Jan 03 02:08:25 PM PST 24
Peak memory 553872 kb
Host smart-dcd71a54-41dc-40f4-b46d-d58edb12048f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046272219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del
ays.2046272219
Directory /workspace/16.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_same_source.2673964226
Short name T133
Test name
Test status
Simulation time 2126551424 ps
CPU time 61.37 seconds
Started Jan 03 02:07:22 PM PST 24
Finished Jan 03 02:08:35 PM PST 24
Peak memory 553892 kb
Host smart-06da45f3-3201-4346-8394-ec7169510c0f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673964226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2673964226
Directory /workspace/16.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke.1985465563
Short name T1217
Test name
Test status
Simulation time 245699222 ps
CPU time 10.81 seconds
Started Jan 03 02:08:53 PM PST 24
Finished Jan 03 02:09:08 PM PST 24
Peak memory 552016 kb
Host smart-092d79f0-60b9-41a0-bce7-8a3ba3040d47
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985465563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1985465563
Directory /workspace/16.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.2611478009
Short name T833
Test name
Test status
Simulation time 9266015263 ps
CPU time 92.51 seconds
Started Jan 03 02:08:25 PM PST 24
Finished Jan 03 02:10:06 PM PST 24
Peak memory 552072 kb
Host smart-8e4bae86-fa0f-425f-968d-60234cc3c688
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611478009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2611478009
Directory /workspace/16.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2468072288
Short name T331
Test name
Test status
Simulation time 4463425549 ps
CPU time 80.18 seconds
Started Jan 03 02:08:14 PM PST 24
Finished Jan 03 02:09:39 PM PST 24
Peak memory 552084 kb
Host smart-ba4e3cd4-1b57-4c17-a2d4-160097d2ecf5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468072288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2468072288
Directory /workspace/16.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2502387014
Short name T1606
Test name
Test status
Simulation time 58551944 ps
CPU time 6.52 seconds
Started Jan 03 02:08:26 PM PST 24
Finished Jan 03 02:08:41 PM PST 24
Peak memory 552068 kb
Host smart-bfc327e7-920b-407f-bb1c-8d7baf042b75
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502387014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay
s.2502387014
Directory /workspace/16.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all.943509030
Short name T816
Test name
Test status
Simulation time 7400409733 ps
CPU time 243.07 seconds
Started Jan 03 02:07:20 PM PST 24
Finished Jan 03 02:11:35 PM PST 24
Peak memory 555420 kb
Host smart-b417749c-1284-4130-8a8e-b99b506bf77e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943509030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.943509030
Directory /workspace/16.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1881707105
Short name T647
Test name
Test status
Simulation time 6062732282 ps
CPU time 262.33 seconds
Started Jan 03 02:07:41 PM PST 24
Finished Jan 03 02:12:15 PM PST 24
Peak memory 555120 kb
Host smart-8c7b964b-686c-42b7-af4e-85f159edc673
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881707105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1881707105
Directory /workspace/16.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.820092893
Short name T985
Test name
Test status
Simulation time 8284854 ps
CPU time 4.62 seconds
Started Jan 03 02:07:32 PM PST 24
Finished Jan 03 02:07:46 PM PST 24
Peak memory 551648 kb
Host smart-1fae4b33-7784-4cd7-8623-b66828c54900
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820092893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_
with_rand_reset.820092893
Directory /workspace/16.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3095492846
Short name T1443
Test name
Test status
Simulation time 2709439146 ps
CPU time 375.6 seconds
Started Jan 03 02:07:37 PM PST 24
Finished Jan 03 02:14:04 PM PST 24
Peak memory 559108 kb
Host smart-4b33707f-a2ea-40dc-a09d-ccb1c5167989
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095492846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al
l_with_reset_error.3095492846
Directory /workspace/16.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1016383848
Short name T1833
Test name
Test status
Simulation time 679422194 ps
CPU time 25.68 seconds
Started Jan 03 02:07:29 PM PST 24
Finished Jan 03 02:08:04 PM PST 24
Peak memory 554144 kb
Host smart-51683e54-1ef9-4578-ab47-8b96d604b7f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016383848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1016383848
Directory /workspace/16.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3396440106
Short name T1538
Test name
Test status
Simulation time 5020142084 ps
CPU time 233.37 seconds
Started Jan 03 02:07:56 PM PST 24
Finished Jan 03 02:12:00 PM PST 24
Peak memory 611704 kb
Host smart-6845f38d-f595-440f-bab8-043952639d9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396440106 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.3396440106
Directory /workspace/17.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.chip_csr_rw.1319268319
Short name T1895
Test name
Test status
Simulation time 5813388722 ps
CPU time 507.21 seconds
Started Jan 03 02:07:54 PM PST 24
Finished Jan 03 02:16:31 PM PST 24
Peak memory 579948 kb
Host smart-b71935cb-53fe-418b-8ff5-f5eefdc3ed4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319268319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.1319268319
Directory /workspace/17.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1245155962
Short name T64
Test name
Test status
Simulation time 27824828789 ps
CPU time 2766.64 seconds
Started Jan 03 02:07:31 PM PST 24
Finished Jan 03 02:53:47 PM PST 24
Peak memory 579960 kb
Host smart-6940db14-c063-47ff-96bc-6601bbbc605a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245155962 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.1245155962
Directory /workspace/17.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.chip_tl_errors.1819079537
Short name T279
Test name
Test status
Simulation time 3823765648 ps
CPU time 304.46 seconds
Started Jan 03 02:07:53 PM PST 24
Finished Jan 03 02:13:08 PM PST 24
Peak memory 580052 kb
Host smart-340d41b7-2927-4c71-986c-dc8c26691857
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819079537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.1819079537
Directory /workspace/17.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3604367490
Short name T1053
Test name
Test status
Simulation time 129052387630 ps
CPU time 1875.74 seconds
Started Jan 03 02:07:27 PM PST 24
Finished Jan 03 02:38:54 PM PST 24
Peak memory 555304 kb
Host smart-5c77fbc4-6d62-4575-8836-9f82155731af
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604367490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_
device_slow_rsp.3604367490
Directory /workspace/17.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3651524655
Short name T1835
Test name
Test status
Simulation time 541088480 ps
CPU time 22.75 seconds
Started Jan 03 02:07:21 PM PST 24
Finished Jan 03 02:07:56 PM PST 24
Peak memory 553892 kb
Host smart-18e9f3ff-6aa5-4606-ac59-5460e43cfd04
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651524655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add
r.3651524655
Directory /workspace/17.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_error_random.2393155276
Short name T1858
Test name
Test status
Simulation time 143710721 ps
CPU time 13.11 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:08:21 PM PST 24
Peak memory 554200 kb
Host smart-01f43fc6-8006-4a0f-90bd-b1f5b7981c28
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393155276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2393155276
Directory /workspace/17.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random.579895163
Short name T1676
Test name
Test status
Simulation time 356806040 ps
CPU time 29.75 seconds
Started Jan 03 02:08:02 PM PST 24
Finished Jan 03 02:08:41 PM PST 24
Peak memory 553880 kb
Host smart-429aba01-353a-4847-855e-ee7fde70256a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579895163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.579895163
Directory /workspace/17.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.3117540612
Short name T1094
Test name
Test status
Simulation time 82308020233 ps
CPU time 767.51 seconds
Started Jan 03 02:07:33 PM PST 24
Finished Jan 03 02:20:30 PM PST 24
Peak memory 554296 kb
Host smart-a84cae6f-4867-4ff5-85d3-5396f5deae3d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117540612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3117540612
Directory /workspace/17.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1502251889
Short name T1248
Test name
Test status
Simulation time 46721780677 ps
CPU time 738.77 seconds
Started Jan 03 02:07:35 PM PST 24
Finished Jan 03 02:20:03 PM PST 24
Peak memory 554292 kb
Host smart-1434acaf-c7bc-4715-a42c-47ea7bb6fefa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502251889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1502251889
Directory /workspace/17.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.3612016668
Short name T109
Test name
Test status
Simulation time 366185798 ps
CPU time 30.74 seconds
Started Jan 03 02:07:32 PM PST 24
Finished Jan 03 02:08:12 PM PST 24
Peak memory 553864 kb
Host smart-dd5a881d-d09a-4233-adb1-13e0f6ca2a45
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612016668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del
ays.3612016668
Directory /workspace/17.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_same_source.2394852767
Short name T726
Test name
Test status
Simulation time 1156697907 ps
CPU time 30.08 seconds
Started Jan 03 02:07:24 PM PST 24
Finished Jan 03 02:08:06 PM PST 24
Peak memory 553900 kb
Host smart-e66b72b7-9dfd-4edd-a68c-41cbd7defc4e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394852767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2394852767
Directory /workspace/17.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke.2960574621
Short name T712
Test name
Test status
Simulation time 194481688 ps
CPU time 8.28 seconds
Started Jan 03 02:07:54 PM PST 24
Finished Jan 03 02:08:13 PM PST 24
Peak memory 551660 kb
Host smart-a165cc11-78f0-4ba7-a6f7-f6bf2a780d3f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960574621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2960574621
Directory /workspace/17.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1041368438
Short name T1714
Test name
Test status
Simulation time 7363391416 ps
CPU time 75.21 seconds
Started Jan 03 02:07:31 PM PST 24
Finished Jan 03 02:08:55 PM PST 24
Peak memory 551708 kb
Host smart-2695f99d-8891-4589-a1c4-d0e19971506c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041368438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1041368438
Directory /workspace/17.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.4097498346
Short name T1169
Test name
Test status
Simulation time 6502214455 ps
CPU time 102.36 seconds
Started Jan 03 02:07:47 PM PST 24
Finished Jan 03 02:09:41 PM PST 24
Peak memory 551852 kb
Host smart-897b8240-b4c3-4b5c-8980-789d53395ebb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097498346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.4097498346
Directory /workspace/17.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.4133689567
Short name T1544
Test name
Test status
Simulation time 54998238 ps
CPU time 6.28 seconds
Started Jan 03 02:07:06 PM PST 24
Finished Jan 03 02:07:13 PM PST 24
Peak memory 552088 kb
Host smart-80ffc6b1-7318-43da-8a30-3cb1eccf858b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133689567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay
s.4133689567
Directory /workspace/17.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all.437495674
Short name T1793
Test name
Test status
Simulation time 5835920985 ps
CPU time 193.26 seconds
Started Jan 03 02:07:31 PM PST 24
Finished Jan 03 02:10:54 PM PST 24
Peak memory 555396 kb
Host smart-155de058-1daf-442c-96c7-34cd443d1584
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437495674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.437495674
Directory /workspace/17.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.2863690881
Short name T1842
Test name
Test status
Simulation time 265705898 ps
CPU time 112.62 seconds
Started Jan 03 02:07:26 PM PST 24
Finished Jan 03 02:09:30 PM PST 24
Peak memory 554560 kb
Host smart-9bd3b67e-4c39-4eaa-aef4-57ced5b48cb7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863690881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all
_with_rand_reset.2863690881
Directory /workspace/17.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.526759604
Short name T204
Test name
Test status
Simulation time 2255113801 ps
CPU time 171.99 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:10:38 PM PST 24
Peak memory 556016 kb
Host smart-70c7db56-50d8-4c5f-8826-c16b3d2fe6fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526759604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all
_with_reset_error.526759604
Directory /workspace/17.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.3225505314
Short name T106
Test name
Test status
Simulation time 978805833 ps
CPU time 41.92 seconds
Started Jan 03 02:07:31 PM PST 24
Finished Jan 03 02:08:22 PM PST 24
Peak memory 553096 kb
Host smart-ce95b946-c57d-48d7-848f-f93b529cd7e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225505314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3225505314
Directory /workspace/17.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/18.chip_csr_rw.1031767741
Short name T44
Test name
Test status
Simulation time 3878453988 ps
CPU time 343.44 seconds
Started Jan 03 02:07:20 PM PST 24
Finished Jan 03 02:13:16 PM PST 24
Peak memory 580112 kb
Host smart-9dcff331-5e34-4c3a-91ba-a69ca6ecc51d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031767741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.1031767741
Directory /workspace/18.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.4045211932
Short name T1433
Test name
Test status
Simulation time 29214655407 ps
CPU time 2716.57 seconds
Started Jan 03 02:07:59 PM PST 24
Finished Jan 03 02:53:26 PM PST 24
Peak memory 579072 kb
Host smart-23fe7e5e-4b99-4d66-a486-99ff539d0ede
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045211932 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.4045211932
Directory /workspace/18.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.chip_tl_errors.106382237
Short name T275
Test name
Test status
Simulation time 3443181800 ps
CPU time 178.5 seconds
Started Jan 03 02:07:21 PM PST 24
Finished Jan 03 02:10:32 PM PST 24
Peak memory 580136 kb
Host smart-eb942e3f-b0bc-4e55-a6a6-346460f66881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106382237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.106382237
Directory /workspace/18.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_access_same_device.4156342952
Short name T1175
Test name
Test status
Simulation time 2541579181 ps
CPU time 104.48 seconds
Started Jan 03 02:07:44 PM PST 24
Finished Jan 03 02:09:40 PM PST 24
Peak memory 554328 kb
Host smart-0e209a53-5cbd-4532-b195-afc8670984ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156342952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device
.4156342952
Directory /workspace/18.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.1744791372
Short name T1044
Test name
Test status
Simulation time 164188471 ps
CPU time 17.57 seconds
Started Jan 03 02:07:55 PM PST 24
Finished Jan 03 02:08:22 PM PST 24
Peak memory 554116 kb
Host smart-06f094e8-8607-4b2c-9308-9ccef6818529
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744791372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add
r.1744791372
Directory /workspace/18.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_error_random.3181184850
Short name T883
Test name
Test status
Simulation time 1410724446 ps
CPU time 47.12 seconds
Started Jan 03 02:07:32 PM PST 24
Finished Jan 03 02:08:28 PM PST 24
Peak memory 554128 kb
Host smart-360a3892-316e-4278-917b-f82c9d961974
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181184850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3181184850
Directory /workspace/18.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random.3306543223
Short name T702
Test name
Test status
Simulation time 2623000796 ps
CPU time 102.62 seconds
Started Jan 03 02:07:59 PM PST 24
Finished Jan 03 02:09:52 PM PST 24
Peak memory 553948 kb
Host smart-89d6b1b1-713a-4c6d-972f-4fdf5e5ba0e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306543223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.3306543223
Directory /workspace/18.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.366370031
Short name T1430
Test name
Test status
Simulation time 95868221375 ps
CPU time 960.96 seconds
Started Jan 03 02:07:43 PM PST 24
Finished Jan 03 02:23:56 PM PST 24
Peak memory 553944 kb
Host smart-62f0c565-3aed-4097-b4c6-1a24180a1aa4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366370031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.366370031
Directory /workspace/18.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.4267505163
Short name T986
Test name
Test status
Simulation time 17288562460 ps
CPU time 276.11 seconds
Started Jan 03 02:07:23 PM PST 24
Finished Jan 03 02:12:12 PM PST 24
Peak memory 554284 kb
Host smart-e148a03f-7818-4a6c-ae80-4f6fdd4e34c8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267505163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.4267505163
Directory /workspace/18.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3075956518
Short name T1526
Test name
Test status
Simulation time 222220177 ps
CPU time 18.85 seconds
Started Jan 03 02:07:39 PM PST 24
Finished Jan 03 02:08:10 PM PST 24
Peak memory 554180 kb
Host smart-758c545c-42dd-4b63-9a31-a7af2e75d2a2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075956518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del
ays.3075956518
Directory /workspace/18.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_same_source.3246240017
Short name T741
Test name
Test status
Simulation time 532764437 ps
CPU time 34.23 seconds
Started Jan 03 02:07:32 PM PST 24
Finished Jan 03 02:08:15 PM PST 24
Peak memory 553844 kb
Host smart-cc3c8221-75f3-4dc5-a005-ba933c88bc53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246240017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3246240017
Directory /workspace/18.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke.1278096546
Short name T1499
Test name
Test status
Simulation time 180278161 ps
CPU time 7.93 seconds
Started Jan 03 02:07:59 PM PST 24
Finished Jan 03 02:08:17 PM PST 24
Peak memory 552080 kb
Host smart-5e1438f4-9ef8-435f-8479-6efad158d73e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278096546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1278096546
Directory /workspace/18.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.1276798416
Short name T137
Test name
Test status
Simulation time 8138102168 ps
CPU time 82.62 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:09:09 PM PST 24
Peak memory 551832 kb
Host smart-2e6e3b81-7fa8-4d39-bebe-44ec0fe6a096
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276798416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1276798416
Directory /workspace/18.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2837223294
Short name T1495
Test name
Test status
Simulation time 4649557814 ps
CPU time 75.51 seconds
Started Jan 03 02:07:54 PM PST 24
Finished Jan 03 02:09:20 PM PST 24
Peak memory 551708 kb
Host smart-14095b01-3a2d-45fd-bc8d-8662add2b665
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837223294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2837223294
Directory /workspace/18.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1738534109
Short name T1747
Test name
Test status
Simulation time 47771818 ps
CPU time 6.34 seconds
Started Jan 03 02:07:44 PM PST 24
Finished Jan 03 02:08:02 PM PST 24
Peak memory 551804 kb
Host smart-faf7f9be-15d0-418f-ade3-0f24a6bd4915
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738534109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay
s.1738534109
Directory /workspace/18.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all.2086041732
Short name T777
Test name
Test status
Simulation time 8093315708 ps
CPU time 259.27 seconds
Started Jan 03 02:07:59 PM PST 24
Finished Jan 03 02:12:28 PM PST 24
Peak memory 554300 kb
Host smart-6cf8c950-cf4a-480b-8aec-11e77cd81017
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086041732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2086041732
Directory /workspace/18.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.595550211
Short name T694
Test name
Test status
Simulation time 2137574416 ps
CPU time 158.72 seconds
Started Jan 03 02:07:26 PM PST 24
Finished Jan 03 02:10:15 PM PST 24
Peak memory 555332 kb
Host smart-552b71b0-026f-4063-8afa-ae3fed20be55
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595550211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.595550211
Directory /workspace/18.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1348274134
Short name T1600
Test name
Test status
Simulation time 4300934448 ps
CPU time 462.48 seconds
Started Jan 03 02:07:37 PM PST 24
Finished Jan 03 02:15:30 PM PST 24
Peak memory 557568 kb
Host smart-28925fcb-b4de-4e56-a892-43eae2a041b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348274134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all
_with_rand_reset.1348274134
Directory /workspace/18.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1745055781
Short name T759
Test name
Test status
Simulation time 2499243159 ps
CPU time 177.54 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:10:45 PM PST 24
Peak memory 555112 kb
Host smart-e238aba8-22e6-428f-9665-64de9ac6efc9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745055781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al
l_with_reset_error.1745055781
Directory /workspace/18.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.2949358342
Short name T987
Test name
Test status
Simulation time 266200126 ps
CPU time 28.58 seconds
Started Jan 03 02:07:37 PM PST 24
Finished Jan 03 02:08:17 PM PST 24
Peak memory 554228 kb
Host smart-5e8d81ed-0319-4f5f-bf4e-a06f91d15827
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949358342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.2949358342
Directory /workspace/18.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.2894503705
Short name T708
Test name
Test status
Simulation time 4421720713 ps
CPU time 179.98 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:11:24 PM PST 24
Peak memory 617564 kb
Host smart-689f9c00-d443-4cf8-9b84-abc0bcb54d28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894503705 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.2894503705
Directory /workspace/19.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.chip_csr_rw.126976565
Short name T150
Test name
Test status
Simulation time 6009721704 ps
CPU time 498.06 seconds
Started Jan 03 02:08:13 PM PST 24
Finished Jan 03 02:16:34 PM PST 24
Peak memory 579960 kb
Host smart-10248268-aebf-443b-9d2e-c2387e0de396
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126976565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.126976565
Directory /workspace/19.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_access_same_device.1687966327
Short name T1583
Test name
Test status
Simulation time 725004799 ps
CPU time 31.22 seconds
Started Jan 03 02:07:23 PM PST 24
Finished Jan 03 02:08:06 PM PST 24
Peak memory 553900 kb
Host smart-efae9fac-5fa9-4ea5-9fbd-713b8c465ef1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687966327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device
.1687966327
Directory /workspace/19.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.3546429424
Short name T1014
Test name
Test status
Simulation time 110561371335 ps
CPU time 1652.84 seconds
Started Jan 03 02:08:03 PM PST 24
Finished Jan 03 02:35:45 PM PST 24
Peak memory 554004 kb
Host smart-d0283ae8-5751-4cb2-96c9-178ac8973984
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546429424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_
device_slow_rsp.3546429424
Directory /workspace/19.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.4262060171
Short name T1036
Test name
Test status
Simulation time 1221100560 ps
CPU time 40.16 seconds
Started Jan 03 02:07:55 PM PST 24
Finished Jan 03 02:08:45 PM PST 24
Peak memory 552824 kb
Host smart-ced8cab4-9452-45b3-9f26-5cf7e425ce5c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262060171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add
r.4262060171
Directory /workspace/19.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_error_random.2883809721
Short name T738
Test name
Test status
Simulation time 2678194094 ps
CPU time 87.85 seconds
Started Jan 03 02:08:10 PM PST 24
Finished Jan 03 02:09:42 PM PST 24
Peak memory 553836 kb
Host smart-ab93abbb-93ae-4e60-9cbf-13a4d0cab45f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883809721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2883809721
Directory /workspace/19.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random.2434984621
Short name T1309
Test name
Test status
Simulation time 2550466936 ps
CPU time 93.62 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:09:42 PM PST 24
Peak memory 553936 kb
Host smart-33dde25f-2547-429a-9006-e649641d6827
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434984621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.2434984621
Directory /workspace/19.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.2771053755
Short name T1173
Test name
Test status
Simulation time 11269926654 ps
CPU time 123.92 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:10:12 PM PST 24
Peak memory 551884 kb
Host smart-33a354ed-8ea0-4b02-bc1a-df2413fe004a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771053755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2771053755
Directory /workspace/19.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.2176152793
Short name T1500
Test name
Test status
Simulation time 54542365923 ps
CPU time 858.73 seconds
Started Jan 03 02:07:34 PM PST 24
Finished Jan 03 02:22:02 PM PST 24
Peak memory 553120 kb
Host smart-aeed0fc5-d69f-4892-8231-ca5bbd2ad4d0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176152793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2176152793
Directory /workspace/19.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2639219215
Short name T444
Test name
Test status
Simulation time 241959146 ps
CPU time 20.35 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:08:29 PM PST 24
Peak memory 553036 kb
Host smart-fe9633d8-d363-4589-8c5d-9fdda19a4ce7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639219215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del
ays.2639219215
Directory /workspace/19.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_same_source.3336819585
Short name T1511
Test name
Test status
Simulation time 708309502 ps
CPU time 20.32 seconds
Started Jan 03 02:07:35 PM PST 24
Finished Jan 03 02:08:05 PM PST 24
Peak memory 553064 kb
Host smart-bbfc1a4f-de24-4458-a7ea-d3fa4855a520
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336819585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3336819585
Directory /workspace/19.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke.210881673
Short name T248
Test name
Test status
Simulation time 38126211 ps
CPU time 5.42 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:07:53 PM PST 24
Peak memory 551804 kb
Host smart-b773e337-9f61-44c4-8faa-5012126717ba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210881673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.210881673
Directory /workspace/19.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.2226135805
Short name T1398
Test name
Test status
Simulation time 8722556316 ps
CPU time 91.92 seconds
Started Jan 03 02:07:43 PM PST 24
Finished Jan 03 02:09:26 PM PST 24
Peak memory 552144 kb
Host smart-6802881d-9863-44c3-9561-08ac65df3d9d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226135805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2226135805
Directory /workspace/19.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3883395064
Short name T1272
Test name
Test status
Simulation time 4428058390 ps
CPU time 70.86 seconds
Started Jan 03 02:08:06 PM PST 24
Finished Jan 03 02:09:24 PM PST 24
Peak memory 551712 kb
Host smart-973093ff-7593-422e-9c76-674211ae1852
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883395064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3883395064
Directory /workspace/19.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.822026988
Short name T1185
Test name
Test status
Simulation time 44666449 ps
CPU time 5.73 seconds
Started Jan 03 02:07:26 PM PST 24
Finished Jan 03 02:07:43 PM PST 24
Peak memory 551332 kb
Host smart-de5fe805-4971-4179-9065-a902e7e7aab8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822026988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays
.822026988
Directory /workspace/19.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all.3082568173
Short name T115
Test name
Test status
Simulation time 1836166980 ps
CPU time 156.99 seconds
Started Jan 03 02:07:56 PM PST 24
Finished Jan 03 02:10:44 PM PST 24
Peak memory 555080 kb
Host smart-3059d1ad-0956-46c7-8c74-cb1f2d57db7a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082568173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3082568173
Directory /workspace/19.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.356341193
Short name T1766
Test name
Test status
Simulation time 1347783445 ps
CPU time 49.7 seconds
Started Jan 03 02:08:18 PM PST 24
Finished Jan 03 02:09:15 PM PST 24
Peak memory 554896 kb
Host smart-423a4290-5af4-4eca-93f6-f7531d0a6f9f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356341193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.356341193
Directory /workspace/19.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2148335082
Short name T1063
Test name
Test status
Simulation time 276499213 ps
CPU time 112.34 seconds
Started Jan 03 02:08:05 PM PST 24
Finished Jan 03 02:10:05 PM PST 24
Peak memory 555312 kb
Host smart-f8e2bc58-627e-4275-b591-e02d2f64f2b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148335082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all
_with_rand_reset.2148335082
Directory /workspace/19.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.845772850
Short name T335
Test name
Test status
Simulation time 650579654 ps
CPU time 185.58 seconds
Started Jan 03 02:07:50 PM PST 24
Finished Jan 03 02:11:05 PM PST 24
Peak memory 558324 kb
Host smart-771deb2e-06b9-4ee9-9fe9-403065e5ed9a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845772850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all
_with_reset_error.845772850
Directory /workspace/19.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.1534887939
Short name T656
Test name
Test status
Simulation time 482827114 ps
CPU time 21.07 seconds
Started Jan 03 02:08:03 PM PST 24
Finished Jan 03 02:08:33 PM PST 24
Peak memory 554172 kb
Host smart-03c8d802-8203-403c-9424-27179db8add7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534887939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1534887939
Directory /workspace/19.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.928766293
Short name T65
Test name
Test status
Simulation time 55551708830 ps
CPU time 7052.24 seconds
Started Jan 03 02:07:09 PM PST 24
Finished Jan 03 04:04:43 PM PST 24
Peak memory 621912 kb
Host smart-cfec64dd-7d85-4600-acbd-38b8fb3e9fc8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928766293 -assert nopostproc +UVM_TESTNAME=chip_b
ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.chip_csr_aliasing.928766293
Directory /workspace/2.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.1361179776
Short name T1167
Test name
Test status
Simulation time 9272952980 ps
CPU time 811.44 seconds
Started Jan 03 02:07:26 PM PST 24
Finished Jan 03 02:21:08 PM PST 24
Peak memory 580012 kb
Host smart-fc591965-5346-436e-ad58-441edf4ef83d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361179776 -assert nopostproc
+UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.1361179776
Directory /workspace/2.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.2568334439
Short name T1121
Test name
Test status
Simulation time 9817550098 ps
CPU time 406.78 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:14:55 PM PST 24
Peak memory 615880 kb
Host smart-3f6ecffc-60b8-47b3-814f-d315a57a7ab1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568334439 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.2568334439
Directory /workspace/2.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.chip_csr_rw.2350028903
Short name T1250
Test name
Test status
Simulation time 4452909397 ps
CPU time 265.94 seconds
Started Jan 03 02:07:55 PM PST 24
Finished Jan 03 02:12:32 PM PST 24
Peak memory 579952 kb
Host smart-ba4f2e08-180c-43b5-9e57-05ba79da8716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350028903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.2350028903
Directory /workspace/2.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1169427333
Short name T37
Test name
Test status
Simulation time 15009147451 ps
CPU time 390.41 seconds
Started Jan 03 02:07:06 PM PST 24
Finished Jan 03 02:13:38 PM PST 24
Peak memory 577284 kb
Host smart-28924052-9e9d-40d9-9e95-1bc3725b849a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169427333 -assert nopostproc +UVM_TESTNAME=chip_base_t
est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.chip_rv_dm_lc_disabled.1169427333
Directory /workspace/2.chip_rv_dm_lc_disabled/latest

Test location /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.2314506292
Short name T63
Test name
Test status
Simulation time 28294201653 ps
CPU time 3147.72 seconds
Started Jan 03 02:07:08 PM PST 24
Finished Jan 03 02:59:37 PM PST 24
Peak memory 580016 kb
Host smart-917fee00-be25-4749-8818-ed1cf79bcde9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314506292 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.2314506292
Directory /workspace/2.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_access_same_device.2534112905
Short name T1765
Test name
Test status
Simulation time 609980098 ps
CPU time 38.69 seconds
Started Jan 03 02:07:16 PM PST 24
Finished Jan 03 02:08:00 PM PST 24
Peak memory 554952 kb
Host smart-544496d5-11df-4c3a-afb3-891beeb73881
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534112905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.
2534112905
Directory /workspace/2.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.606673206
Short name T1649
Test name
Test status
Simulation time 106238011346 ps
CPU time 1713.04 seconds
Started Jan 03 02:07:33 PM PST 24
Finished Jan 03 02:36:16 PM PST 24
Peak memory 554972 kb
Host smart-e2d99175-0ede-4e9d-8888-07e22d2ff633
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606673206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_de
vice_slow_rsp.606673206
Directory /workspace/2.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1758458377
Short name T450
Test name
Test status
Simulation time 177943899 ps
CPU time 19.89 seconds
Started Jan 03 02:07:55 PM PST 24
Finished Jan 03 02:08:26 PM PST 24
Peak memory 553816 kb
Host smart-26c3b0ea-b6fb-4bdd-a85b-bff476cd4aa9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758458377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr
.1758458377
Directory /workspace/2.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_error_random.4197934890
Short name T1413
Test name
Test status
Simulation time 152007229 ps
CPU time 13.98 seconds
Started Jan 03 02:07:33 PM PST 24
Finished Jan 03 02:07:57 PM PST 24
Peak memory 553804 kb
Host smart-15608543-59bb-4259-81d8-51e35ae25599
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197934890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.4197934890
Directory /workspace/2.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random.2142417178
Short name T1147
Test name
Test status
Simulation time 550502397 ps
CPU time 45.76 seconds
Started Jan 03 02:07:33 PM PST 24
Finished Jan 03 02:08:29 PM PST 24
Peak memory 552760 kb
Host smart-f9324797-e6e3-4c36-bc47-ab64f11b0b3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142417178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.2142417178
Directory /workspace/2.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.2992813634
Short name T1042
Test name
Test status
Simulation time 73360752717 ps
CPU time 721.5 seconds
Started Jan 03 02:07:18 PM PST 24
Finished Jan 03 02:19:28 PM PST 24
Peak memory 553952 kb
Host smart-ea1042a2-401a-4698-a863-e06003a69165
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992813634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2992813634
Directory /workspace/2.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.277489406
Short name T128
Test name
Test status
Simulation time 25390152529 ps
CPU time 419.21 seconds
Started Jan 03 02:07:09 PM PST 24
Finished Jan 03 02:14:10 PM PST 24
Peak memory 554224 kb
Host smart-b1a7be27-2375-4970-a493-18e9f68a3cae
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277489406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.277489406
Directory /workspace/2.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.3305151301
Short name T660
Test name
Test status
Simulation time 360820643 ps
CPU time 28.52 seconds
Started Jan 03 02:07:07 PM PST 24
Finished Jan 03 02:07:37 PM PST 24
Peak memory 553024 kb
Host smart-3cdf0355-cc05-4c12-96ea-11e610d24650
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305151301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela
ys.3305151301
Directory /workspace/2.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_same_source.96690959
Short name T240
Test name
Test status
Simulation time 421027954 ps
CPU time 27.59 seconds
Started Jan 03 02:07:16 PM PST 24
Finished Jan 03 02:07:49 PM PST 24
Peak memory 554196 kb
Host smart-b1c6d885-924c-441c-adc6-1d0c26382337
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96690959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.96690959
Directory /workspace/2.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke.865785802
Short name T488
Test name
Test status
Simulation time 218432707 ps
CPU time 9.16 seconds
Started Jan 03 02:06:58 PM PST 24
Finished Jan 03 02:07:09 PM PST 24
Peak memory 552176 kb
Host smart-82f3a691-df35-4cd3-a004-22841561b24c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865785802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.865785802
Directory /workspace/2.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1857512932
Short name T1837
Test name
Test status
Simulation time 8457861324 ps
CPU time 82.59 seconds
Started Jan 03 02:07:17 PM PST 24
Finished Jan 03 02:08:45 PM PST 24
Peak memory 552180 kb
Host smart-ffcd677c-2284-4e6b-9053-84109c0caf29
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857512932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1857512932
Directory /workspace/2.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.1378784740
Short name T460
Test name
Test status
Simulation time 3231973475 ps
CPU time 58.05 seconds
Started Jan 03 02:07:34 PM PST 24
Finished Jan 03 02:08:42 PM PST 24
Peak memory 551820 kb
Host smart-8b52face-3722-4e06-a96e-e80ef25973f2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378784740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1378784740
Directory /workspace/2.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3600192487
Short name T1317
Test name
Test status
Simulation time 49760188 ps
CPU time 5.83 seconds
Started Jan 03 02:07:18 PM PST 24
Finished Jan 03 02:07:30 PM PST 24
Peak memory 551808 kb
Host smart-f672ef99-bc25-4326-aaed-1e09274b1b14
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600192487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays
.3600192487
Directory /workspace/2.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all.4191847597
Short name T890
Test name
Test status
Simulation time 10004030588 ps
CPU time 352.21 seconds
Started Jan 03 02:07:32 PM PST 24
Finished Jan 03 02:13:34 PM PST 24
Peak memory 555368 kb
Host smart-5c6baaa1-1704-47d5-a644-678182f3f719
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191847597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.4191847597
Directory /workspace/2.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1523428743
Short name T1707
Test name
Test status
Simulation time 1039474793 ps
CPU time 30.93 seconds
Started Jan 03 02:08:05 PM PST 24
Finished Jan 03 02:08:43 PM PST 24
Peak memory 553892 kb
Host smart-d1854e86-8f43-40f9-be5b-be695e15ef9c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523428743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1523428743
Directory /workspace/2.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1896874873
Short name T586
Test name
Test status
Simulation time 313922571 ps
CPU time 80.06 seconds
Started Jan 03 02:07:55 PM PST 24
Finished Jan 03 02:09:26 PM PST 24
Peak memory 555284 kb
Host smart-caa2d929-8de0-4355-a3cf-6d8df8f55d2f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896874873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all
_with_reset_error.1896874873
Directory /workspace/2.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.3662169900
Short name T145
Test name
Test status
Simulation time 855197251 ps
CPU time 37.46 seconds
Started Jan 03 02:07:20 PM PST 24
Finished Jan 03 02:08:10 PM PST 24
Peak memory 553868 kb
Host smart-59278a5a-38a6-40ad-9207-bcb5e26be787
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662169900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3662169900
Directory /workspace/2.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_access_same_device.4246892435
Short name T503
Test name
Test status
Simulation time 3041698716 ps
CPU time 108.27 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:10:10 PM PST 24
Peak memory 554872 kb
Host smart-3d16791c-9129-4d41-9409-3ba4a569612b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246892435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device
.4246892435
Directory /workspace/20.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3864231611
Short name T289
Test name
Test status
Simulation time 90789135377 ps
CPU time 1559.04 seconds
Started Jan 03 02:07:57 PM PST 24
Finished Jan 03 02:34:07 PM PST 24
Peak memory 555384 kb
Host smart-7ffbe1c8-eefb-4665-ae87-f6575a560fdf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864231611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_
device_slow_rsp.3864231611
Directory /workspace/20.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2354315115
Short name T1212
Test name
Test status
Simulation time 845043138 ps
CPU time 30.81 seconds
Started Jan 03 02:08:19 PM PST 24
Finished Jan 03 02:08:57 PM PST 24
Peak memory 554160 kb
Host smart-29aac6a9-82e2-4c0c-b294-8e9891d4d631
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354315115 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add
r.2354315115
Directory /workspace/20.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_error_random.1376417832
Short name T370
Test name
Test status
Simulation time 211015491 ps
CPU time 17.97 seconds
Started Jan 03 02:08:24 PM PST 24
Finished Jan 03 02:08:50 PM PST 24
Peak memory 553840 kb
Host smart-9623f85b-b0a4-4a3b-9648-7680202e26d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376417832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.1376417832
Directory /workspace/20.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random.2832614568
Short name T1589
Test name
Test status
Simulation time 556628827 ps
CPU time 42.74 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:09:04 PM PST 24
Peak memory 554144 kb
Host smart-b990ce30-c9c5-498e-8886-ab525bea0133
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832614568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.2832614568
Directory /workspace/20.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3771294935
Short name T1284
Test name
Test status
Simulation time 40755225369 ps
CPU time 464.48 seconds
Started Jan 03 02:08:18 PM PST 24
Finished Jan 03 02:16:10 PM PST 24
Peak memory 554256 kb
Host smart-1da6f03d-0a3d-44fa-a4d5-39dc7f9490d2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771294935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3771294935
Directory /workspace/20.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.873773173
Short name T977
Test name
Test status
Simulation time 52446949638 ps
CPU time 803.59 seconds
Started Jan 03 02:08:18 PM PST 24
Finished Jan 03 02:21:48 PM PST 24
Peak memory 553872 kb
Host smart-48ee2029-3789-4b6e-8351-b8f011cfdcd3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873773173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.873773173
Directory /workspace/20.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.3006041229
Short name T261
Test name
Test status
Simulation time 570993172 ps
CPU time 52.11 seconds
Started Jan 03 02:08:12 PM PST 24
Finished Jan 03 02:09:07 PM PST 24
Peak memory 554124 kb
Host smart-9f76d3f2-3245-4ab0-86e4-197ccb8db571
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006041229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del
ays.3006041229
Directory /workspace/20.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_same_source.2725144964
Short name T1682
Test name
Test status
Simulation time 982495850 ps
CPU time 30.51 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:08:51 PM PST 24
Peak memory 553996 kb
Host smart-a21b4b65-7347-4650-8c42-3bdfdfe675ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725144964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2725144964
Directory /workspace/20.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke.4259411976
Short name T1862
Test name
Test status
Simulation time 46141862 ps
CPU time 5.83 seconds
Started Jan 03 02:08:15 PM PST 24
Finished Jan 03 02:08:26 PM PST 24
Peak memory 552032 kb
Host smart-ab38130b-a28d-4fd6-b1e5-a7e2dd3fc5fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259411976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.4259411976
Directory /workspace/20.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1166193110
Short name T1445
Test name
Test status
Simulation time 8161767471 ps
CPU time 85.91 seconds
Started Jan 03 02:08:26 PM PST 24
Finished Jan 03 02:10:01 PM PST 24
Peak memory 551872 kb
Host smart-9101c708-a1d2-463a-966a-84e314e80f83
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166193110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1166193110
Directory /workspace/20.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2193419990
Short name T585
Test name
Test status
Simulation time 6259211224 ps
CPU time 103.13 seconds
Started Jan 03 02:08:23 PM PST 24
Finished Jan 03 02:10:15 PM PST 24
Peak memory 551736 kb
Host smart-a3e218f1-fdfe-47a7-aa73-05d66f307d3e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193419990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2193419990
Directory /workspace/20.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3528274515
Short name T601
Test name
Test status
Simulation time 45388022 ps
CPU time 5.55 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:08:30 PM PST 24
Peak memory 552016 kb
Host smart-7f096336-f33f-4cf1-911a-8a54a18c9eae
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528274515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay
s.3528274515
Directory /workspace/20.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all.2673015951
Short name T1427
Test name
Test status
Simulation time 756021149 ps
CPU time 32.22 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:08:56 PM PST 24
Peak memory 553012 kb
Host smart-ad604464-7ac1-4d9a-bf13-f75525dc1305
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673015951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2673015951
Directory /workspace/20.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.1446591485
Short name T935
Test name
Test status
Simulation time 4199024200 ps
CPU time 126.03 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:10:28 PM PST 24
Peak memory 553892 kb
Host smart-8d8a87a5-1e04-4cd7-9e52-f7f30de4a4b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446591485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.1446591485
Directory /workspace/20.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.4178096537
Short name T1456
Test name
Test status
Simulation time 1019012537 ps
CPU time 92.72 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:09:54 PM PST 24
Peak memory 555020 kb
Host smart-face457f-b0b4-476d-a155-4004ab63fd57
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178096537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all
_with_rand_reset.4178096537
Directory /workspace/20.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2560999193
Short name T1232
Test name
Test status
Simulation time 4603356610 ps
CPU time 431.85 seconds
Started Jan 03 02:08:18 PM PST 24
Finished Jan 03 02:15:38 PM PST 24
Peak memory 559132 kb
Host smart-4da5b98d-1f48-4e2f-9bf5-095364bad40a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560999193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al
l_with_reset_error.2560999193
Directory /workspace/20.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.4112284399
Short name T678
Test name
Test status
Simulation time 277499803 ps
CPU time 12.95 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:08:36 PM PST 24
Peak memory 553892 kb
Host smart-a335aa49-034f-46cb-ab7b-134cbe9ac167
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112284399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.4112284399
Directory /workspace/20.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/21.chip_tl_errors.384494106
Short name T3
Test name
Test status
Simulation time 2860051810 ps
CPU time 214.62 seconds
Started Jan 03 02:08:19 PM PST 24
Finished Jan 03 02:12:02 PM PST 24
Peak memory 580096 kb
Host smart-a23a8c31-3de4-41f2-8b66-c605e3a1100a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384494106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.384494106
Directory /workspace/21.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_access_same_device.3464662934
Short name T307
Test name
Test status
Simulation time 1141453010 ps
CPU time 76.16 seconds
Started Jan 03 02:08:14 PM PST 24
Finished Jan 03 02:09:34 PM PST 24
Peak memory 554220 kb
Host smart-5b9d0023-b79f-4ed5-a0e3-ebdc3541fce4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464662934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device
.3464662934
Directory /workspace/21.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.3368333008
Short name T813
Test name
Test status
Simulation time 122715379110 ps
CPU time 2118.85 seconds
Started Jan 03 02:08:13 PM PST 24
Finished Jan 03 02:43:35 PM PST 24
Peak memory 555280 kb
Host smart-12ccf675-fb49-481b-84cd-9111efccc434
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368333008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_
device_slow_rsp.3368333008
Directory /workspace/21.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.159307604
Short name T648
Test name
Test status
Simulation time 1431818705 ps
CPU time 49.2 seconds
Started Jan 03 02:08:12 PM PST 24
Finished Jan 03 02:09:04 PM PST 24
Peak memory 554260 kb
Host smart-c46ac945-a387-4a50-8d00-79976d936c34
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159307604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr
.159307604
Directory /workspace/21.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_error_random.4251808754
Short name T1224
Test name
Test status
Simulation time 1008990799 ps
CPU time 35.76 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:08:57 PM PST 24
Peak memory 553756 kb
Host smart-6ab4efec-15b5-4a7f-84a4-e83860ddb6df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251808754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.4251808754
Directory /workspace/21.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random.3542230881
Short name T1681
Test name
Test status
Simulation time 515190238 ps
CPU time 20.25 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:08:43 PM PST 24
Peak memory 553808 kb
Host smart-a9d35ca4-659d-4325-979d-38508f630795
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542230881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.3542230881
Directory /workspace/21.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.3888145231
Short name T934
Test name
Test status
Simulation time 29722080143 ps
CPU time 505.06 seconds
Started Jan 03 02:08:18 PM PST 24
Finished Jan 03 02:16:50 PM PST 24
Peak memory 553876 kb
Host smart-fb0bcf38-dda0-40a5-9679-8bb3d8d11233
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888145231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3888145231
Directory /workspace/21.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.1611802930
Short name T459
Test name
Test status
Simulation time 220106668 ps
CPU time 20.89 seconds
Started Jan 03 02:08:12 PM PST 24
Finished Jan 03 02:08:36 PM PST 24
Peak memory 553864 kb
Host smart-4632ed36-37e4-450f-a041-370b9b60f2fc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611802930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del
ays.1611802930
Directory /workspace/21.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_same_source.2548684097
Short name T625
Test name
Test status
Simulation time 494163266 ps
CPU time 30.85 seconds
Started Jan 03 02:07:57 PM PST 24
Finished Jan 03 02:08:38 PM PST 24
Peak memory 554144 kb
Host smart-b52452b0-ed2d-4deb-bffe-193a5b656f7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548684097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2548684097
Directory /workspace/21.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke.2157454140
Short name T515
Test name
Test status
Simulation time 149028584 ps
CPU time 7.43 seconds
Started Jan 03 02:08:13 PM PST 24
Finished Jan 03 02:08:23 PM PST 24
Peak memory 551728 kb
Host smart-3916def8-4984-491c-a056-2d44dc82aec8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157454140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2157454140
Directory /workspace/21.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.2794276227
Short name T789
Test name
Test status
Simulation time 8073809061 ps
CPU time 82.59 seconds
Started Jan 03 02:08:23 PM PST 24
Finished Jan 03 02:09:54 PM PST 24
Peak memory 551848 kb
Host smart-048b1bb3-1fcf-4e72-9424-3799b6550799
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794276227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2794276227
Directory /workspace/21.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3594098026
Short name T803
Test name
Test status
Simulation time 3870247527 ps
CPU time 59.32 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:09:21 PM PST 24
Peak memory 552112 kb
Host smart-f8c7462b-8dfa-48c5-afe9-14349144d21e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594098026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3594098026
Directory /workspace/21.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1084262963
Short name T794
Test name
Test status
Simulation time 46962654 ps
CPU time 5.81 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:08:29 PM PST 24
Peak memory 552020 kb
Host smart-1c425720-9a28-40a0-92de-a33c8e07e58a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084262963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay
s.1084262963
Directory /workspace/21.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all.1084028872
Short name T1299
Test name
Test status
Simulation time 2970859689 ps
CPU time 213.43 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:11:55 PM PST 24
Peak memory 555100 kb
Host smart-368b6582-644e-4697-bcbe-3ce27000e39b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084028872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1084028872
Directory /workspace/21.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.1708024252
Short name T482
Test name
Test status
Simulation time 2018341877 ps
CPU time 159.86 seconds
Started Jan 03 02:08:23 PM PST 24
Finished Jan 03 02:11:12 PM PST 24
Peak memory 553936 kb
Host smart-a0cb442a-561c-4dae-a773-b148f118b270
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708024252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1708024252
Directory /workspace/21.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2484943052
Short name T984
Test name
Test status
Simulation time 689972818 ps
CPU time 293.09 seconds
Started Jan 03 02:08:14 PM PST 24
Finished Jan 03 02:13:09 PM PST 24
Peak memory 556416 kb
Host smart-0d0b3ce6-e9d6-4365-bd0b-d8aefd88c317
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484943052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all
_with_rand_reset.2484943052
Directory /workspace/21.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1814854449
Short name T334
Test name
Test status
Simulation time 644991035 ps
CPU time 166.36 seconds
Started Jan 03 02:07:56 PM PST 24
Finished Jan 03 02:10:53 PM PST 24
Peak memory 557312 kb
Host smart-a4d2536b-43ea-4c53-b0c6-b72e04a83b3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814854449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al
l_with_reset_error.1814854449
Directory /workspace/21.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.2871557524
Short name T98
Test name
Test status
Simulation time 260623422 ps
CPU time 28.17 seconds
Started Jan 03 02:08:12 PM PST 24
Finished Jan 03 02:08:43 PM PST 24
Peak memory 554132 kb
Host smart-528c219a-2057-4472-afed-e737ec4b4b20
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871557524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.2871557524
Directory /workspace/21.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/22.chip_tl_errors.441737049
Short name T277
Test name
Test status
Simulation time 3426550676 ps
CPU time 178.39 seconds
Started Jan 03 02:08:14 PM PST 24
Finished Jan 03 02:11:15 PM PST 24
Peak memory 580040 kb
Host smart-f538fb48-2b7a-4f1a-b298-361675d915b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441737049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.441737049
Directory /workspace/22.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_access_same_device.3522870884
Short name T1337
Test name
Test status
Simulation time 2429453485 ps
CPU time 101.36 seconds
Started Jan 03 02:08:12 PM PST 24
Finished Jan 03 02:09:56 PM PST 24
Peak memory 554184 kb
Host smart-8b1945c3-8fcc-4744-acf7-01761cebf98d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522870884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device
.3522870884
Directory /workspace/22.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.959573267
Short name T295
Test name
Test status
Simulation time 65910293561 ps
CPU time 1034.01 seconds
Started Jan 03 02:08:19 PM PST 24
Finished Jan 03 02:25:41 PM PST 24
Peak memory 555244 kb
Host smart-b029e128-db1d-405a-893f-ad903d3972dc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959573267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_d
evice_slow_rsp.959573267
Directory /workspace/22.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1525347779
Short name T1164
Test name
Test status
Simulation time 185083958 ps
CPU time 18.62 seconds
Started Jan 03 02:08:18 PM PST 24
Finished Jan 03 02:08:44 PM PST 24
Peak memory 554104 kb
Host smart-dfa97c3f-e536-487c-936c-37410421237b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525347779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add
r.1525347779
Directory /workspace/22.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_error_random.2647492396
Short name T1131
Test name
Test status
Simulation time 32491331 ps
CPU time 5.35 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:08:29 PM PST 24
Peak memory 552036 kb
Host smart-f0027b14-96bd-4c60-b2f6-7d2230f63f4d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647492396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2647492396
Directory /workspace/22.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random.3853285547
Short name T146
Test name
Test status
Simulation time 1322952678 ps
CPU time 43.7 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:09:07 PM PST 24
Peak memory 554160 kb
Host smart-05af9639-6b91-4ec5-baad-9e1293e878fa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853285547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.3853285547
Directory /workspace/22.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.2520762637
Short name T1771
Test name
Test status
Simulation time 5680256936 ps
CPU time 64.73 seconds
Started Jan 03 02:08:15 PM PST 24
Finished Jan 03 02:09:24 PM PST 24
Peak memory 551840 kb
Host smart-749b71d0-ee20-4587-82a0-4d83484d80fe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520762637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2520762637
Directory /workspace/22.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.1187536981
Short name T826
Test name
Test status
Simulation time 24867789999 ps
CPU time 404.81 seconds
Started Jan 03 02:08:14 PM PST 24
Finished Jan 03 02:15:02 PM PST 24
Peak memory 553884 kb
Host smart-a63faae6-84b8-4983-83a3-10be5aede308
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187536981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1187536981
Directory /workspace/22.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.884317804
Short name T1639
Test name
Test status
Simulation time 558284622 ps
CPU time 44.94 seconds
Started Jan 03 02:08:23 PM PST 24
Finished Jan 03 02:09:16 PM PST 24
Peak memory 554156 kb
Host smart-d0cc6158-a4c3-432f-9c9e-c2a6d040be29
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884317804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_dela
ys.884317804
Directory /workspace/22.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_same_source.3140407239
Short name T241
Test name
Test status
Simulation time 2502295248 ps
CPU time 70.62 seconds
Started Jan 03 02:08:20 PM PST 24
Finished Jan 03 02:09:38 PM PST 24
Peak memory 554252 kb
Host smart-e098d0e6-4004-4231-bacd-260c9383a27e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140407239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3140407239
Directory /workspace/22.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke.2458263863
Short name T1225
Test name
Test status
Simulation time 226983839 ps
CPU time 9.48 seconds
Started Jan 03 02:08:13 PM PST 24
Finished Jan 03 02:08:26 PM PST 24
Peak memory 551904 kb
Host smart-7a4f5f57-f241-49b8-81d1-c7c77e54f57b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458263863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2458263863
Directory /workspace/22.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.4166583087
Short name T202
Test name
Test status
Simulation time 6958603124 ps
CPU time 76.3 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:09:41 PM PST 24
Peak memory 552128 kb
Host smart-447f4526-9d6c-49a8-a552-729a223be5f5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166583087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.4166583087
Directory /workspace/22.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.1905734549
Short name T1889
Test name
Test status
Simulation time 5336707217 ps
CPU time 95 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:09:58 PM PST 24
Peak memory 551656 kb
Host smart-bbc7ed63-752f-4de1-b348-a5ef7918613b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905734549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1905734549
Directory /workspace/22.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.749183098
Short name T1516
Test name
Test status
Simulation time 46595662 ps
CPU time 5.86 seconds
Started Jan 03 02:08:14 PM PST 24
Finished Jan 03 02:08:23 PM PST 24
Peak memory 552108 kb
Host smart-3818bc3d-43c9-4ef1-8aa7-5e7edd3adb5a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749183098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays
.749183098
Directory /workspace/22.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all.613559464
Short name T136
Test name
Test status
Simulation time 14707319176 ps
CPU time 557.36 seconds
Started Jan 03 02:20:46 PM PST 24
Finished Jan 03 02:30:05 PM PST 24
Peak memory 557496 kb
Host smart-b690f1e5-d551-4871-af6f-456b3f89c55e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613559464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.613559464
Directory /workspace/22.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.1104993750
Short name T936
Test name
Test status
Simulation time 3321378058 ps
CPU time 246.6 seconds
Started Jan 03 02:08:00 PM PST 24
Finished Jan 03 02:12:16 PM PST 24
Peak memory 555752 kb
Host smart-4d7c34fd-c9ab-451d-8bc0-c6ac5fe9a538
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104993750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1104993750
Directory /workspace/22.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1106426531
Short name T1362
Test name
Test status
Simulation time 329105558 ps
CPU time 115.08 seconds
Started Jan 03 02:08:43 PM PST 24
Finished Jan 03 02:10:45 PM PST 24
Peak memory 555076 kb
Host smart-14547e23-ed94-4113-a395-e4d3c8cdff56
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106426531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all
_with_rand_reset.1106426531
Directory /workspace/22.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.2729032354
Short name T1635
Test name
Test status
Simulation time 943645239 ps
CPU time 36.72 seconds
Started Jan 03 02:08:25 PM PST 24
Finished Jan 03 02:09:10 PM PST 24
Peak memory 553840 kb
Host smart-9e62b7b8-701f-4877-9f72-1d3a627ca687
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729032354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2729032354
Directory /workspace/22.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/23.chip_tl_errors.520079769
Short name T1857
Test name
Test status
Simulation time 3564267200 ps
CPU time 173.63 seconds
Started Jan 03 02:14:49 PM PST 24
Finished Jan 03 02:17:45 PM PST 24
Peak memory 580092 kb
Host smart-2ff54ce9-f08d-4715-9e79-f24a48817b85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520079769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.520079769
Directory /workspace/23.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_access_same_device.369420780
Short name T1258
Test name
Test status
Simulation time 708531693 ps
CPU time 33.98 seconds
Started Jan 03 02:17:42 PM PST 24
Finished Jan 03 02:18:18 PM PST 24
Peak memory 553864 kb
Host smart-23d64da0-f2b6-406f-8b55-fe0d894fe097
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369420780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.
369420780
Directory /workspace/23.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2483631905
Short name T1354
Test name
Test status
Simulation time 119358346097 ps
CPU time 2112.84 seconds
Started Jan 03 02:09:29 PM PST 24
Finished Jan 03 02:44:50 PM PST 24
Peak memory 555376 kb
Host smart-3a6a8a77-1830-445b-8acb-4a5d67cbb903
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483631905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_
device_slow_rsp.2483631905
Directory /workspace/23.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.886656771
Short name T1141
Test name
Test status
Simulation time 268672253 ps
CPU time 29.07 seconds
Started Jan 03 02:09:48 PM PST 24
Finished Jan 03 02:10:21 PM PST 24
Peak memory 554144 kb
Host smart-71ed5fbf-b802-4f44-bce8-25f25d26f2ca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886656771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr
.886656771
Directory /workspace/23.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_error_random.450720692
Short name T1022
Test name
Test status
Simulation time 2388533893 ps
CPU time 84.07 seconds
Started Jan 03 02:09:27 PM PST 24
Finished Jan 03 02:11:00 PM PST 24
Peak memory 554292 kb
Host smart-6cdb05d1-4f01-4338-83fe-4f823ac23748
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450720692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.450720692
Directory /workspace/23.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random.1715347623
Short name T1410
Test name
Test status
Simulation time 846789198 ps
CPU time 33.28 seconds
Started Jan 03 02:08:35 PM PST 24
Finished Jan 03 02:09:16 PM PST 24
Peak memory 554176 kb
Host smart-f54937c2-2244-4414-8022-8930b45b2166
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715347623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.1715347623
Directory /workspace/23.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.1764825467
Short name T74
Test name
Test status
Simulation time 57031850692 ps
CPU time 622.55 seconds
Started Jan 03 02:09:04 PM PST 24
Finished Jan 03 02:19:32 PM PST 24
Peak memory 554180 kb
Host smart-ef96d9a4-6948-4ab4-8991-8ebce134d440
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764825467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1764825467
Directory /workspace/23.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.1892023419
Short name T836
Test name
Test status
Simulation time 40486743056 ps
CPU time 672 seconds
Started Jan 03 02:15:09 PM PST 24
Finished Jan 03 02:26:28 PM PST 24
Peak memory 553920 kb
Host smart-e2359d15-aa00-458f-8778-5aea8ed01ca1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892023419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1892023419
Directory /workspace/23.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.2788091722
Short name T1757
Test name
Test status
Simulation time 379184599 ps
CPU time 31.41 seconds
Started Jan 03 02:08:58 PM PST 24
Finished Jan 03 02:09:31 PM PST 24
Peak memory 554132 kb
Host smart-4ee9b7d2-1e64-49af-aea8-5c9a266a3bd6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788091722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del
ays.2788091722
Directory /workspace/23.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_same_source.969847763
Short name T193
Test name
Test status
Simulation time 2729008641 ps
CPU time 85.45 seconds
Started Jan 03 02:21:00 PM PST 24
Finished Jan 03 02:22:27 PM PST 24
Peak memory 553876 kb
Host smart-95f5293f-2449-4c3c-a1e0-1e7c57e8ab77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969847763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.969847763
Directory /workspace/23.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke.3940974016
Short name T377
Test name
Test status
Simulation time 240702254 ps
CPU time 9.72 seconds
Started Jan 03 02:23:21 PM PST 24
Finished Jan 03 02:23:32 PM PST 24
Peak memory 552092 kb
Host smart-e8eddfe0-05b1-4b81-b5db-5cf90c42d4e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940974016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3940974016
Directory /workspace/23.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.316735204
Short name T1025
Test name
Test status
Simulation time 6848488282 ps
CPU time 67.66 seconds
Started Jan 03 02:08:53 PM PST 24
Finished Jan 03 02:10:04 PM PST 24
Peak memory 551732 kb
Host smart-bdb8e5f3-c27a-4811-954b-b3a375d7f1c6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316735204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.316735204
Directory /workspace/23.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.3476494549
Short name T1748
Test name
Test status
Simulation time 4689147604 ps
CPU time 81.86 seconds
Started Jan 03 02:08:37 PM PST 24
Finished Jan 03 02:10:07 PM PST 24
Peak memory 551816 kb
Host smart-8a13e0db-2898-4c51-8dfa-1be8fddd2276
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476494549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3476494549
Directory /workspace/23.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.2413249341
Short name T1334
Test name
Test status
Simulation time 42873611 ps
CPU time 6.06 seconds
Started Jan 03 02:08:42 PM PST 24
Finished Jan 03 02:08:55 PM PST 24
Peak memory 552028 kb
Host smart-723015e5-bfd6-453a-bc40-37678060a60e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413249341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay
s.2413249341
Directory /workspace/23.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all.2900559722
Short name T1458
Test name
Test status
Simulation time 9745541055 ps
CPU time 349.67 seconds
Started Jan 03 02:16:20 PM PST 24
Finished Jan 03 02:22:11 PM PST 24
Peak memory 555108 kb
Host smart-06a7790e-5f92-43a5-b894-b1bb3a6236d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900559722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2900559722
Directory /workspace/23.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.3591029521
Short name T588
Test name
Test status
Simulation time 9286449420 ps
CPU time 302.24 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:14:46 PM PST 24
Peak memory 555032 kb
Host smart-f953312c-7bc1-4eaa-9d7b-ca1c9466cecc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591029521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3591029521
Directory /workspace/23.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.888045032
Short name T897
Test name
Test status
Simulation time 123839630 ps
CPU time 48.59 seconds
Started Jan 03 02:12:45 PM PST 24
Finished Jan 03 02:13:49 PM PST 24
Peak memory 555064 kb
Host smart-eed8a8a6-35a5-4e6b-a04b-6d5689f635d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888045032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_
with_rand_reset.888045032
Directory /workspace/23.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.837784321
Short name T1573
Test name
Test status
Simulation time 1371227283 ps
CPU time 202.08 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:13:11 PM PST 24
Peak memory 558504 kb
Host smart-3b7ac3e8-efc9-45ee-9c82-0de886105e9d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837784321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all
_with_reset_error.837784321
Directory /workspace/23.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.4280138080
Short name T607
Test name
Test status
Simulation time 331170986 ps
CPU time 37.85 seconds
Started Jan 03 02:09:54 PM PST 24
Finished Jan 03 02:10:34 PM PST 24
Peak memory 554244 kb
Host smart-aeba6e16-076a-4fe8-87a3-2337cec36c5f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280138080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.4280138080
Directory /workspace/23.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/24.chip_tl_errors.1665419797
Short name T1670
Test name
Test status
Simulation time 2842272704 ps
CPU time 154.89 seconds
Started Jan 03 02:14:21 PM PST 24
Finished Jan 03 02:17:06 PM PST 24
Peak memory 580040 kb
Host smart-8218a8fd-9fb6-409b-bcef-57eb95c9fc27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665419797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.1665419797
Directory /workspace/24.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_access_same_device.835176302
Short name T551
Test name
Test status
Simulation time 129390330 ps
CPU time 13.28 seconds
Started Jan 03 02:09:07 PM PST 24
Finished Jan 03 02:09:25 PM PST 24
Peak memory 552056 kb
Host smart-66e556be-5eec-4e0f-9fb0-4b5da91fbd3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835176302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.
835176302
Directory /workspace/24.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1173759108
Short name T1822
Test name
Test status
Simulation time 64939384344 ps
CPU time 1078.09 seconds
Started Jan 03 02:08:54 PM PST 24
Finished Jan 03 02:26:56 PM PST 24
Peak memory 554272 kb
Host smart-753391d3-9bfb-4880-8468-dcab08d1bea2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173759108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_
device_slow_rsp.1173759108
Directory /workspace/24.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.3674306481
Short name T1236
Test name
Test status
Simulation time 220687392 ps
CPU time 25.75 seconds
Started Jan 03 02:08:56 PM PST 24
Finished Jan 03 02:09:24 PM PST 24
Peak memory 553804 kb
Host smart-51e0cc1a-2404-4303-ba84-4092366b87de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674306481 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add
r.3674306481
Directory /workspace/24.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_error_random.4086951816
Short name T793
Test name
Test status
Simulation time 568359431 ps
CPU time 39.14 seconds
Started Jan 03 02:09:03 PM PST 24
Finished Jan 03 02:09:47 PM PST 24
Peak memory 553832 kb
Host smart-bf4d74de-8eaf-4d2c-8861-153dc2376c90
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086951816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.4086951816
Directory /workspace/24.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random.3386708071
Short name T1832
Test name
Test status
Simulation time 427388089 ps
CPU time 15.93 seconds
Started Jan 03 02:08:59 PM PST 24
Finished Jan 03 02:09:19 PM PST 24
Peak memory 553820 kb
Host smart-cebf3028-03a6-48da-b25d-51cd70aa4b3f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386708071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.3386708071
Directory /workspace/24.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.3922739951
Short name T1432
Test name
Test status
Simulation time 108991894864 ps
CPU time 1124.07 seconds
Started Jan 03 02:08:23 PM PST 24
Finished Jan 03 02:27:16 PM PST 24
Peak memory 554260 kb
Host smart-5bd10bdb-aeb9-46d2-8ee7-f75615522923
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922739951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3922739951
Directory /workspace/24.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.1132828469
Short name T786
Test name
Test status
Simulation time 66358788743 ps
CPU time 1124.91 seconds
Started Jan 03 02:09:07 PM PST 24
Finished Jan 03 02:27:56 PM PST 24
Peak memory 553980 kb
Host smart-09290dd3-c0a2-4304-b006-13d61b55c2cf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132828469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1132828469
Directory /workspace/24.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.2241001413
Short name T600
Test name
Test status
Simulation time 342737904 ps
CPU time 29.05 seconds
Started Jan 03 02:08:43 PM PST 24
Finished Jan 03 02:09:19 PM PST 24
Peak memory 553812 kb
Host smart-b99790f8-0adf-4c86-bf67-54107f4776a2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241001413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del
ays.2241001413
Directory /workspace/24.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_same_source.1841682097
Short name T1181
Test name
Test status
Simulation time 1610671630 ps
CPU time 46.43 seconds
Started Jan 03 02:08:56 PM PST 24
Finished Jan 03 02:09:45 PM PST 24
Peak memory 554080 kb
Host smart-be7c66d9-87f6-4415-ac4d-e36728a35930
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841682097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1841682097
Directory /workspace/24.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke.3100452755
Short name T645
Test name
Test status
Simulation time 48100291 ps
CPU time 5.98 seconds
Started Jan 03 02:09:06 PM PST 24
Finished Jan 03 02:09:16 PM PST 24
Peak memory 552112 kb
Host smart-d4c1d58c-492b-43f6-a3af-d7b976fbcb61
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100452755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3100452755
Directory /workspace/24.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3842909844
Short name T762
Test name
Test status
Simulation time 5606829634 ps
CPU time 61.59 seconds
Started Jan 03 02:08:53 PM PST 24
Finished Jan 03 02:09:57 PM PST 24
Peak memory 552112 kb
Host smart-47d4e060-21c9-46e1-a0a1-c850a1631081
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842909844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3842909844
Directory /workspace/24.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.2257980242
Short name T657
Test name
Test status
Simulation time 4166444081 ps
CPU time 74.92 seconds
Started Jan 03 02:09:04 PM PST 24
Finished Jan 03 02:10:23 PM PST 24
Peak memory 552216 kb
Host smart-8e6f4a55-c436-47b8-b70e-42cd9b0fab0c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257980242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2257980242
Directory /workspace/24.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.360592003
Short name T1642
Test name
Test status
Simulation time 42228723 ps
CPU time 6.16 seconds
Started Jan 03 02:08:43 PM PST 24
Finished Jan 03 02:08:56 PM PST 24
Peak memory 551816 kb
Host smart-fea94569-16f5-4e7d-970b-f24c585bed84
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360592003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays
.360592003
Directory /workspace/24.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all.2779680271
Short name T160
Test name
Test status
Simulation time 916539170 ps
CPU time 72.75 seconds
Started Jan 03 02:09:05 PM PST 24
Finished Jan 03 02:10:22 PM PST 24
Peak memory 555316 kb
Host smart-4c32c788-038b-4210-8414-b8bdd916bd97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779680271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2779680271
Directory /workspace/24.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.1379191162
Short name T911
Test name
Test status
Simulation time 3787448234 ps
CPU time 126.29 seconds
Started Jan 03 02:08:34 PM PST 24
Finished Jan 03 02:10:48 PM PST 24
Peak memory 553988 kb
Host smart-6b2835ca-60ca-44e3-968d-07c845d5e890
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379191162 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1379191162
Directory /workspace/24.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3807969259
Short name T1779
Test name
Test status
Simulation time 88668481 ps
CPU time 15.15 seconds
Started Jan 03 02:08:57 PM PST 24
Finished Jan 03 02:09:14 PM PST 24
Peak memory 553280 kb
Host smart-1caf1c2b-f8ff-4be5-be8e-c294ac159aac
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807969259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all
_with_rand_reset.3807969259
Directory /workspace/24.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2629788158
Short name T1586
Test name
Test status
Simulation time 3077642260 ps
CPU time 362.71 seconds
Started Jan 03 02:08:54 PM PST 24
Finished Jan 03 02:15:00 PM PST 24
Peak memory 559048 kb
Host smart-cfae4ad4-63f6-42b5-9e66-59c5cdc0470d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629788158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al
l_with_reset_error.2629788158
Directory /workspace/24.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.1917194022
Short name T367
Test name
Test status
Simulation time 230142767 ps
CPU time 11.53 seconds
Started Jan 03 02:08:35 PM PST 24
Finished Jan 03 02:08:54 PM PST 24
Peak memory 552900 kb
Host smart-9974f7e6-fa2c-4b55-b939-c4b39ca81170
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917194022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1917194022
Directory /workspace/24.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/25.chip_tl_errors.1469509666
Short name T209
Test name
Test status
Simulation time 3929158568 ps
CPU time 382.46 seconds
Started Jan 03 02:08:42 PM PST 24
Finished Jan 03 02:15:11 PM PST 24
Peak memory 579388 kb
Host smart-0b03fef8-8a67-44cc-87b8-8e3571a916d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469509666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.1469509666
Directory /workspace/25.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_access_same_device.3344821529
Short name T792
Test name
Test status
Simulation time 1313627466 ps
CPU time 49.88 seconds
Started Jan 03 02:09:26 PM PST 24
Finished Jan 03 02:10:25 PM PST 24
Peak memory 553880 kb
Host smart-e7c46c9b-55eb-4f47-862e-a040ce112034
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344821529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device
.3344821529
Directory /workspace/25.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2762953556
Short name T1144
Test name
Test status
Simulation time 64265351619 ps
CPU time 1103.44 seconds
Started Jan 03 02:09:32 PM PST 24
Finished Jan 03 02:28:03 PM PST 24
Peak memory 554236 kb
Host smart-4822f349-de8f-433a-8283-e816523e77b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762953556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_
device_slow_rsp.2762953556
Directory /workspace/25.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.1587457063
Short name T530
Test name
Test status
Simulation time 178461932 ps
CPU time 19.52 seconds
Started Jan 03 02:08:58 PM PST 24
Finished Jan 03 02:09:21 PM PST 24
Peak memory 553876 kb
Host smart-0fd809c7-6d14-4a7e-8083-fb2ec64de411
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587457063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add
r.1587457063
Directory /workspace/25.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_error_random.787048711
Short name T1478
Test name
Test status
Simulation time 1584352416 ps
CPU time 49.2 seconds
Started Jan 03 02:08:30 PM PST 24
Finished Jan 03 02:09:28 PM PST 24
Peak memory 554116 kb
Host smart-59856288-7ef6-4111-bc53-45432aa80d2f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787048711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.787048711
Directory /workspace/25.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random.4163440224
Short name T1341
Test name
Test status
Simulation time 408725514 ps
CPU time 37.83 seconds
Started Jan 03 02:09:06 PM PST 24
Finished Jan 03 02:09:48 PM PST 24
Peak memory 553876 kb
Host smart-87bf37a4-5ab4-4068-b632-16889b84fd5f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163440224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.4163440224
Directory /workspace/25.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.1631130959
Short name T1282
Test name
Test status
Simulation time 61168275986 ps
CPU time 655.1 seconds
Started Jan 03 02:09:10 PM PST 24
Finished Jan 03 02:20:09 PM PST 24
Peak memory 554212 kb
Host smart-e793ba43-58aa-4258-a771-b4a8bd4f9831
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631130959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1631130959
Directory /workspace/25.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.2340247649
Short name T823
Test name
Test status
Simulation time 8608314712 ps
CPU time 132.76 seconds
Started Jan 03 02:08:50 PM PST 24
Finished Jan 03 02:11:08 PM PST 24
Peak memory 553208 kb
Host smart-5bfc11d3-a2e9-4668-ab30-e9aeb3d31567
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340247649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2340247649
Directory /workspace/25.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.3155664680
Short name T127
Test name
Test status
Simulation time 33211655 ps
CPU time 6.25 seconds
Started Jan 03 02:08:35 PM PST 24
Finished Jan 03 02:08:48 PM PST 24
Peak memory 552112 kb
Host smart-38eadc4f-02ae-46ec-89b1-efd44bdfa93a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155664680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del
ays.3155664680
Directory /workspace/25.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_same_source.1212832143
Short name T238
Test name
Test status
Simulation time 1618349493 ps
CPU time 48.82 seconds
Started Jan 03 02:08:57 PM PST 24
Finished Jan 03 02:09:48 PM PST 24
Peak memory 553996 kb
Host smart-1a02ec3f-2c75-4083-b55e-c5c6de08a20e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212832143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1212832143
Directory /workspace/25.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke.1054723327
Short name T1216
Test name
Test status
Simulation time 270448225 ps
CPU time 10.23 seconds
Started Jan 03 02:09:06 PM PST 24
Finished Jan 03 02:09:21 PM PST 24
Peak memory 552176 kb
Host smart-e739f985-3756-4b4b-9e36-e4e6785b50cc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054723327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1054723327
Directory /workspace/25.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.3429143803
Short name T97
Test name
Test status
Simulation time 9812006714 ps
CPU time 98.62 seconds
Started Jan 03 02:08:38 PM PST 24
Finished Jan 03 02:10:24 PM PST 24
Peak memory 552148 kb
Host smart-48bd66dc-d55d-4fcb-a51b-bdaebad553b3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429143803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.3429143803
Directory /workspace/25.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1337474786
Short name T621
Test name
Test status
Simulation time 4516265004 ps
CPU time 81.94 seconds
Started Jan 03 02:09:09 PM PST 24
Finished Jan 03 02:10:35 PM PST 24
Peak memory 552140 kb
Host smart-94ead637-4a22-48b0-9157-5210f542a0ba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337474786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1337474786
Directory /workspace/25.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.51592408
Short name T698
Test name
Test status
Simulation time 52848545 ps
CPU time 6.54 seconds
Started Jan 03 02:08:54 PM PST 24
Finished Jan 03 02:09:04 PM PST 24
Peak memory 552040 kb
Host smart-fdf05688-0248-4ec9-a26a-c25881e4f4e8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51592408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.51592408
Directory /workspace/25.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all.3121548468
Short name T218
Test name
Test status
Simulation time 11876835615 ps
CPU time 405.95 seconds
Started Jan 03 02:09:11 PM PST 24
Finished Jan 03 02:16:00 PM PST 24
Peak memory 555908 kb
Host smart-8ef7c6cd-2ed1-4d15-911d-969a1484e8c2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121548468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3121548468
Directory /workspace/25.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.3924480819
Short name T573
Test name
Test status
Simulation time 9766847421 ps
CPU time 348.83 seconds
Started Jan 03 02:09:31 PM PST 24
Finished Jan 03 02:15:27 PM PST 24
Peak memory 555072 kb
Host smart-80ad579f-1769-4b41-9559-c1483ae32949
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924480819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3924480819
Directory /workspace/25.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.943748870
Short name T1305
Test name
Test status
Simulation time 1071120873 ps
CPU time 264.61 seconds
Started Jan 03 02:09:11 PM PST 24
Finished Jan 03 02:13:39 PM PST 24
Peak memory 557276 kb
Host smart-0cd18100-71a5-4946-9366-f1d2d6f5ef4a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943748870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_
with_rand_reset.943748870
Directory /workspace/25.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.365677376
Short name T1623
Test name
Test status
Simulation time 1924101413 ps
CPU time 130.84 seconds
Started Jan 03 02:09:05 PM PST 24
Finished Jan 03 02:11:21 PM PST 24
Peak memory 555080 kb
Host smart-8a106dff-f270-427e-b4fb-3c6917ea511c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365677376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all
_with_reset_error.365677376
Directory /workspace/25.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.3257863873
Short name T914
Test name
Test status
Simulation time 86426756 ps
CPU time 12.69 seconds
Started Jan 03 02:09:25 PM PST 24
Finished Jan 03 02:09:47 PM PST 24
Peak memory 554188 kb
Host smart-ce76b83a-96a5-4e8c-8b59-8c239480236b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257863873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3257863873
Directory /workspace/25.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/26.chip_tl_errors.3874283893
Short name T278
Test name
Test status
Simulation time 2519882800 ps
CPU time 171.23 seconds
Started Jan 03 02:09:05 PM PST 24
Finished Jan 03 02:12:00 PM PST 24
Peak memory 579908 kb
Host smart-def83248-9d24-413e-a5cb-912f9ab01b09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874283893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.3874283893
Directory /workspace/26.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_access_same_device.868849765
Short name T815
Test name
Test status
Simulation time 2384659248 ps
CPU time 106.37 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:11:30 PM PST 24
Peak memory 554244 kb
Host smart-2882bc9b-ab52-4008-b7c7-359460f44516
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868849765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.
868849765
Directory /workspace/26.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.1300376294
Short name T1671
Test name
Test status
Simulation time 17069493532 ps
CPU time 291.19 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:14:40 PM PST 24
Peak memory 554204 kb
Host smart-cda653a4-3169-415a-b153-e6770b74d87c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300376294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_
device_slow_rsp.1300376294
Directory /workspace/26.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1333688603
Short name T743
Test name
Test status
Simulation time 53761991 ps
CPU time 7.89 seconds
Started Jan 03 02:09:46 PM PST 24
Finished Jan 03 02:09:59 PM PST 24
Peak memory 552872 kb
Host smart-e469aa25-6847-4d09-b65d-59d314b0a4ad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333688603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add
r.1333688603
Directory /workspace/26.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_error_random.4247737961
Short name T903
Test name
Test status
Simulation time 272503690 ps
CPU time 22.98 seconds
Started Jan 03 02:09:20 PM PST 24
Finished Jan 03 02:09:51 PM PST 24
Peak memory 553824 kb
Host smart-7d3b0b03-509b-4f9a-af43-1cc268c2600a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247737961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.4247737961
Directory /workspace/26.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random.1570864700
Short name T664
Test name
Test status
Simulation time 65196612 ps
CPU time 7.98 seconds
Started Jan 03 02:09:39 PM PST 24
Finished Jan 03 02:09:55 PM PST 24
Peak memory 551796 kb
Host smart-84c4a782-2d41-4322-bcc1-80c3a679f945
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570864700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1570864700
Directory /workspace/26.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.1434803343
Short name T1556
Test name
Test status
Simulation time 15872814583 ps
CPU time 172.94 seconds
Started Jan 03 02:09:20 PM PST 24
Finished Jan 03 02:12:20 PM PST 24
Peak memory 554180 kb
Host smart-bcc5ea1a-4268-4e64-a9f2-902b52b04770
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434803343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1434803343
Directory /workspace/26.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.2052756725
Short name T1922
Test name
Test status
Simulation time 36370691636 ps
CPU time 583.38 seconds
Started Jan 03 02:09:40 PM PST 24
Finished Jan 03 02:19:31 PM PST 24
Peak memory 554284 kb
Host smart-30181e3e-f7fe-4563-b76b-c12aefc6a0b2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052756725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2052756725
Directory /workspace/26.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.4239249043
Short name T130
Test name
Test status
Simulation time 389268102 ps
CPU time 32.53 seconds
Started Jan 03 02:09:35 PM PST 24
Finished Jan 03 02:10:15 PM PST 24
Peak memory 554156 kb
Host smart-792490f5-9f3d-4bf3-b64e-09784dcb7636
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239249043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del
ays.4239249043
Directory /workspace/26.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_same_source.3649226001
Short name T912
Test name
Test status
Simulation time 243605281 ps
CPU time 20.04 seconds
Started Jan 03 02:09:09 PM PST 24
Finished Jan 03 02:09:33 PM PST 24
Peak memory 553076 kb
Host smart-5befa103-de00-40fd-b608-3a2fb8989abc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649226001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3649226001
Directory /workspace/26.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke.1553739194
Short name T1674
Test name
Test status
Simulation time 201263413 ps
CPU time 8.42 seconds
Started Jan 03 02:09:17 PM PST 24
Finished Jan 03 02:09:27 PM PST 24
Peak memory 551884 kb
Host smart-2d65ad9d-a079-471d-8a45-0c7d5f9e5f99
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553739194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1553739194
Directory /workspace/26.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.4220033423
Short name T428
Test name
Test status
Simulation time 7396899371 ps
CPU time 81.85 seconds
Started Jan 03 02:09:40 PM PST 24
Finished Jan 03 02:11:09 PM PST 24
Peak memory 551884 kb
Host smart-a842bbd3-460c-4a62-9530-28af05e93707
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220033423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.4220033423
Directory /workspace/26.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1663532120
Short name T552
Test name
Test status
Simulation time 4710276843 ps
CPU time 81 seconds
Started Jan 03 02:09:38 PM PST 24
Finished Jan 03 02:11:07 PM PST 24
Peak memory 552132 kb
Host smart-674143ec-fe3b-46e5-b2b0-c2430f97f63e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663532120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1663532120
Directory /workspace/26.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.269495431
Short name T1796
Test name
Test status
Simulation time 39021481 ps
CPU time 5.59 seconds
Started Jan 03 02:09:14 PM PST 24
Finished Jan 03 02:09:23 PM PST 24
Peak memory 551636 kb
Host smart-ad7db202-6176-4d56-98b9-7899c3be1d95
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269495431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays
.269495431
Directory /workspace/26.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all.1256251259
Short name T201
Test name
Test status
Simulation time 18767628791 ps
CPU time 649.46 seconds
Started Jan 03 02:09:38 PM PST 24
Finished Jan 03 02:20:35 PM PST 24
Peak memory 555424 kb
Host smart-c48499b3-c01c-49e1-b011-5edae7f9f07f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256251259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1256251259
Directory /workspace/26.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.1109622313
Short name T513
Test name
Test status
Simulation time 3998713845 ps
CPU time 146.95 seconds
Started Jan 03 02:09:53 PM PST 24
Finished Jan 03 02:12:22 PM PST 24
Peak memory 554028 kb
Host smart-ddc965b2-2dba-4ac2-8f86-e02a089856c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109622313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1109622313
Directory /workspace/26.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1975582599
Short name T707
Test name
Test status
Simulation time 5632425748 ps
CPU time 265.47 seconds
Started Jan 03 02:09:48 PM PST 24
Finished Jan 03 02:14:17 PM PST 24
Peak memory 557580 kb
Host smart-5ce12f58-11df-4997-96ea-6035bdb0e1a6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975582599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all
_with_rand_reset.1975582599
Directory /workspace/26.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2152938436
Short name T782
Test name
Test status
Simulation time 887287555 ps
CPU time 200.74 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:13:09 PM PST 24
Peak memory 558972 kb
Host smart-a099699f-c147-4ed3-85d4-4ff934f614ca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152938436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al
l_with_reset_error.2152938436
Directory /workspace/26.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.1591599273
Short name T578
Test name
Test status
Simulation time 362647328 ps
CPU time 18.74 seconds
Started Jan 03 02:09:49 PM PST 24
Finished Jan 03 02:10:12 PM PST 24
Peak memory 553980 kb
Host smart-ae4f3af1-054b-43ee-80c1-afb3946d9f77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591599273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1591599273
Directory /workspace/26.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/27.chip_tl_errors.593683320
Short name T1686
Test name
Test status
Simulation time 3507709400 ps
CPU time 191.3 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:12:55 PM PST 24
Peak memory 579004 kb
Host smart-64237b35-783e-456e-9790-3395384172bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593683320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.593683320
Directory /workspace/27.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_access_same_device.4053767587
Short name T681
Test name
Test status
Simulation time 183246285 ps
CPU time 15.62 seconds
Started Jan 03 02:09:53 PM PST 24
Finished Jan 03 02:10:11 PM PST 24
Peak memory 553116 kb
Host smart-3c116724-cc2a-4f56-a4f2-3f9130f66586
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053767587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device
.4053767587
Directory /workspace/27.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.2070803878
Short name T1546
Test name
Test status
Simulation time 37971262043 ps
CPU time 614.33 seconds
Started Jan 03 02:10:01 PM PST 24
Finished Jan 03 02:20:30 PM PST 24
Peak memory 553868 kb
Host smart-a7742829-32b8-480d-9be5-b25e102fabb5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070803878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_
device_slow_rsp.2070803878
Directory /workspace/27.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1745422273
Short name T1162
Test name
Test status
Simulation time 207831074 ps
CPU time 10.91 seconds
Started Jan 03 02:08:58 PM PST 24
Finished Jan 03 02:09:12 PM PST 24
Peak memory 553076 kb
Host smart-34a9128c-6b65-492d-9110-01e1ef67963f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745422273 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add
r.1745422273
Directory /workspace/27.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_error_random.2375804726
Short name T283
Test name
Test status
Simulation time 35153524 ps
CPU time 5.9 seconds
Started Jan 03 02:09:58 PM PST 24
Finished Jan 03 02:10:11 PM PST 24
Peak memory 551996 kb
Host smart-b0500454-8231-489c-bf56-607cd80cbb3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375804726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2375804726
Directory /workspace/27.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random.1707714628
Short name T83
Test name
Test status
Simulation time 521216715 ps
CPU time 46.27 seconds
Started Jan 03 02:09:58 PM PST 24
Finished Jan 03 02:10:51 PM PST 24
Peak memory 553916 kb
Host smart-d46da182-f3a1-420c-9cbe-b4163568513d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707714628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.1707714628
Directory /workspace/27.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.2870364892
Short name T1009
Test name
Test status
Simulation time 49462561862 ps
CPU time 561.1 seconds
Started Jan 03 02:09:55 PM PST 24
Finished Jan 03 02:19:19 PM PST 24
Peak memory 553928 kb
Host smart-e2b67637-da8f-417e-990f-f91cd5743cd6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870364892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2870364892
Directory /workspace/27.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.2386596196
Short name T661
Test name
Test status
Simulation time 40720650413 ps
CPU time 676.16 seconds
Started Jan 03 02:08:36 PM PST 24
Finished Jan 03 02:20:00 PM PST 24
Peak memory 553924 kb
Host smart-70a986d1-b44d-4f1a-a078-66521b1e9f32
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386596196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2386596196
Directory /workspace/27.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.1964959468
Short name T1455
Test name
Test status
Simulation time 525032844 ps
CPU time 42.47 seconds
Started Jan 03 02:09:57 PM PST 24
Finished Jan 03 02:10:46 PM PST 24
Peak memory 553008 kb
Host smart-5cd7e92d-22b9-4a47-9120-81e84694bcc2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964959468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del
ays.1964959468
Directory /workspace/27.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_same_source.3571404602
Short name T1720
Test name
Test status
Simulation time 1255928782 ps
CPU time 37.47 seconds
Started Jan 03 02:09:08 PM PST 24
Finished Jan 03 02:09:50 PM PST 24
Peak memory 554180 kb
Host smart-84215a17-88ae-42db-9b58-6e6461b240c2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571404602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3571404602
Directory /workspace/27.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke.432039059
Short name T1773
Test name
Test status
Simulation time 40094008 ps
CPU time 5.37 seconds
Started Jan 03 02:09:39 PM PST 24
Finished Jan 03 02:09:52 PM PST 24
Peak memory 552068 kb
Host smart-d3ddb6bd-b258-464e-be5e-8742dfbd3445
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432039059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.432039059
Directory /workspace/27.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.2379914854
Short name T1082
Test name
Test status
Simulation time 7394308635 ps
CPU time 73.68 seconds
Started Jan 03 02:09:46 PM PST 24
Finished Jan 03 02:11:05 PM PST 24
Peak memory 551876 kb
Host smart-7470c88c-1f89-45f1-8dd6-3c99f2f2f4bf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379914854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2379914854
Directory /workspace/27.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.794804213
Short name T972
Test name
Test status
Simulation time 4424705863 ps
CPU time 77.22 seconds
Started Jan 03 02:09:57 PM PST 24
Finished Jan 03 02:11:21 PM PST 24
Peak memory 551872 kb
Host smart-47777862-1e93-498b-b8c7-d500758c085a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794804213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.794804213
Directory /workspace/27.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2093252756
Short name T519
Test name
Test status
Simulation time 51268644 ps
CPU time 6.1 seconds
Started Jan 03 02:10:03 PM PST 24
Finished Jan 03 02:10:26 PM PST 24
Peak memory 552012 kb
Host smart-40155e75-298e-40e9-9136-8dd66beddc06
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093252756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay
s.2093252756
Directory /workspace/27.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all.3875654563
Short name T776
Test name
Test status
Simulation time 4546416498 ps
CPU time 184 seconds
Started Jan 03 02:08:44 PM PST 24
Finished Jan 03 02:11:54 PM PST 24
Peak memory 554316 kb
Host smart-85f1f4da-0b1f-49df-8048-c73cc88020f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875654563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3875654563
Directory /workspace/27.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.2103342576
Short name T421
Test name
Test status
Simulation time 710036483 ps
CPU time 53.73 seconds
Started Jan 03 02:08:54 PM PST 24
Finished Jan 03 02:09:51 PM PST 24
Peak memory 554204 kb
Host smart-4ba93863-5c69-42f6-9706-c279f22d8792
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103342576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2103342576
Directory /workspace/27.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.545895119
Short name T1311
Test name
Test status
Simulation time 10823416907 ps
CPU time 615.23 seconds
Started Jan 03 02:08:58 PM PST 24
Finished Jan 03 02:19:17 PM PST 24
Peak memory 559072 kb
Host smart-b3a6d4de-5775-4381-956c-ed151650fd73
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545895119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_
with_rand_reset.545895119
Directory /workspace/27.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1560137781
Short name T312
Test name
Test status
Simulation time 8204886995 ps
CPU time 354.96 seconds
Started Jan 03 02:08:52 PM PST 24
Finished Jan 03 02:14:51 PM PST 24
Peak memory 555448 kb
Host smart-39c4e741-6d72-4359-ac79-e72cdf1e6c82
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560137781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al
l_with_reset_error.1560137781
Directory /workspace/27.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.262203470
Short name T1787
Test name
Test status
Simulation time 729308122 ps
CPU time 31.33 seconds
Started Jan 03 02:08:53 PM PST 24
Finished Jan 03 02:09:28 PM PST 24
Peak memory 554144 kb
Host smart-c3522085-5985-4646-9315-cb7e6417bdcd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262203470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.262203470
Directory /workspace/27.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_access_same_device.671086874
Short name T294
Test name
Test status
Simulation time 860003018 ps
CPU time 68.32 seconds
Started Jan 03 02:09:05 PM PST 24
Finished Jan 03 02:10:18 PM PST 24
Peak memory 554920 kb
Host smart-9719cc59-447a-4456-8ce0-f2e63d117aaf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671086874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.
671086874
Directory /workspace/28.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2953544425
Short name T1473
Test name
Test status
Simulation time 3222949385 ps
CPU time 56.91 seconds
Started Jan 03 02:09:32 PM PST 24
Finished Jan 03 02:10:36 PM PST 24
Peak memory 553176 kb
Host smart-ea003672-fc7a-4a65-9fa9-99a53f9e65df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953544425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_
device_slow_rsp.2953544425
Directory /workspace/28.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1118058148
Short name T478
Test name
Test status
Simulation time 156870610 ps
CPU time 18.73 seconds
Started Jan 03 02:09:32 PM PST 24
Finished Jan 03 02:09:58 PM PST 24
Peak memory 554228 kb
Host smart-5923d2c0-3599-4219-8cde-0e1b9d87b7a7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118058148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add
r.1118058148
Directory /workspace/28.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_error_random.3519906309
Short name T410
Test name
Test status
Simulation time 271620354 ps
CPU time 22.85 seconds
Started Jan 03 02:09:31 PM PST 24
Finished Jan 03 02:10:02 PM PST 24
Peak memory 554108 kb
Host smart-c4314f68-a1e4-4c72-957d-1738c2bb6201
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519906309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3519906309
Directory /workspace/28.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random.170926317
Short name T84
Test name
Test status
Simulation time 1982356571 ps
CPU time 66.58 seconds
Started Jan 03 02:09:07 PM PST 24
Finished Jan 03 02:10:18 PM PST 24
Peak memory 554156 kb
Host smart-169b9144-30f8-45c8-b011-6ad7ff1a28de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170926317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.170926317
Directory /workspace/28.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.3403141284
Short name T1360
Test name
Test status
Simulation time 29048301632 ps
CPU time 305 seconds
Started Jan 03 02:09:05 PM PST 24
Finished Jan 03 02:14:15 PM PST 24
Peak memory 553956 kb
Host smart-0e50bcda-b005-4d03-a1a9-8ddf6fbb0982
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403141284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3403141284
Directory /workspace/28.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.1498200958
Short name T159
Test name
Test status
Simulation time 34247061174 ps
CPU time 604.66 seconds
Started Jan 03 02:09:26 PM PST 24
Finished Jan 03 02:19:40 PM PST 24
Peak memory 554252 kb
Host smart-1d8d4792-05cb-4970-bfb0-706f7d0070d5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498200958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1498200958
Directory /workspace/28.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.2978521839
Short name T1619
Test name
Test status
Simulation time 396475943 ps
CPU time 28.76 seconds
Started Jan 03 02:09:05 PM PST 24
Finished Jan 03 02:09:39 PM PST 24
Peak memory 553068 kb
Host smart-921c5403-cad0-4854-8825-6361fd91ba31
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978521839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del
ays.2978521839
Directory /workspace/28.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_same_source.1649777348
Short name T1921
Test name
Test status
Simulation time 445116027 ps
CPU time 33.15 seconds
Started Jan 03 02:09:31 PM PST 24
Finished Jan 03 02:10:12 PM PST 24
Peak memory 553940 kb
Host smart-1c0e889a-29ee-49e2-b0f8-841fd8f50994
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649777348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1649777348
Directory /workspace/28.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke.53503180
Short name T1316
Test name
Test status
Simulation time 121673995 ps
CPU time 6.99 seconds
Started Jan 03 02:08:55 PM PST 24
Finished Jan 03 02:09:05 PM PST 24
Peak memory 551788 kb
Host smart-26cde734-9909-4dff-83d4-4b481fc5ceab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53503180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.53503180
Directory /workspace/28.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.4287500892
Short name T1219
Test name
Test status
Simulation time 7511835633 ps
CPU time 73.66 seconds
Started Jan 03 02:09:31 PM PST 24
Finished Jan 03 02:10:53 PM PST 24
Peak memory 552132 kb
Host smart-7c23c856-c07f-4e48-97c3-e0afee67af5e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287500892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.4287500892
Directory /workspace/28.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3388441155
Short name T1106
Test name
Test status
Simulation time 5255626412 ps
CPU time 87.05 seconds
Started Jan 03 02:09:04 PM PST 24
Finished Jan 03 02:10:36 PM PST 24
Peak memory 551884 kb
Host smart-affb74a5-c91b-4678-8e0b-36077565bcf2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388441155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3388441155
Directory /workspace/28.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.2063668029
Short name T1093
Test name
Test status
Simulation time 54569794 ps
CPU time 6.93 seconds
Started Jan 03 02:09:04 PM PST 24
Finished Jan 03 02:09:16 PM PST 24
Peak memory 551756 kb
Host smart-afdd8033-3884-461c-870d-1f34f70bff37
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063668029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay
s.2063668029
Directory /workspace/28.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all.1829498002
Short name T874
Test name
Test status
Simulation time 2562475126 ps
CPU time 202.48 seconds
Started Jan 03 02:09:34 PM PST 24
Finished Jan 03 02:13:04 PM PST 24
Peak memory 555416 kb
Host smart-f24b5919-e58a-4e68-95f4-c73d47effdc4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829498002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1829498002
Directory /workspace/28.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.2768429232
Short name T328
Test name
Test status
Simulation time 2972143895 ps
CPU time 246.73 seconds
Started Jan 03 02:09:28 PM PST 24
Finished Jan 03 02:13:43 PM PST 24
Peak memory 555360 kb
Host smart-4a8cfbd7-d012-4b76-8478-886de8ab2a64
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768429232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2768429232
Directory /workspace/28.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1468462666
Short name T1294
Test name
Test status
Simulation time 4732012506 ps
CPU time 186.07 seconds
Started Jan 03 02:09:40 PM PST 24
Finished Jan 03 02:12:54 PM PST 24
Peak memory 555428 kb
Host smart-f1f4d6bf-36f2-476e-9836-2cfa8ad26f25
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468462666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al
l_with_reset_error.1468462666
Directory /workspace/28.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.3145039366
Short name T842
Test name
Test status
Simulation time 80772137 ps
CPU time 11.81 seconds
Started Jan 03 02:09:07 PM PST 24
Finished Jan 03 02:09:24 PM PST 24
Peak memory 553912 kb
Host smart-dcca9fa8-1f97-4ba7-935f-95da4a8c3394
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145039366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3145039366
Directory /workspace/28.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/29.chip_tl_errors.1371421340
Short name T1486
Test name
Test status
Simulation time 3592084343 ps
CPU time 293.08 seconds
Started Jan 03 02:09:38 PM PST 24
Finished Jan 03 02:14:39 PM PST 24
Peak memory 580056 kb
Host smart-22569cba-1c08-4d32-88af-1a7e439e4167
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371421340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.1371421340
Directory /workspace/29.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_access_same_device.2043146878
Short name T820
Test name
Test status
Simulation time 2441716216 ps
CPU time 108.84 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:11:34 PM PST 24
Peak memory 553168 kb
Host smart-7efd828d-bd01-4594-9135-2e17b44fe24a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043146878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device
.2043146878
Directory /workspace/29.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.324161897
Short name T801
Test name
Test status
Simulation time 52986285892 ps
CPU time 826.97 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:23:36 PM PST 24
Peak memory 555244 kb
Host smart-f80f4c9f-d242-43c7-98f9-9bb66716affd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324161897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_d
evice_slow_rsp.324161897
Directory /workspace/29.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.566706902
Short name T524
Test name
Test status
Simulation time 730523682 ps
CPU time 27.08 seconds
Started Jan 03 02:10:03 PM PST 24
Finished Jan 03 02:10:47 PM PST 24
Peak memory 553832 kb
Host smart-87e5941e-b4b8-468c-998d-b5fd81b7647c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566706902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr
.566706902
Directory /workspace/29.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_error_random.762469425
Short name T1617
Test name
Test status
Simulation time 87114340 ps
CPU time 9.92 seconds
Started Jan 03 02:09:49 PM PST 24
Finished Jan 03 02:10:03 PM PST 24
Peak memory 553848 kb
Host smart-2046b090-c9fe-457a-8bea-4e7999e60d01
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762469425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.762469425
Directory /workspace/29.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random.1340961114
Short name T257
Test name
Test status
Simulation time 98833849 ps
CPU time 10.09 seconds
Started Jan 03 02:09:41 PM PST 24
Finished Jan 03 02:09:58 PM PST 24
Peak memory 554080 kb
Host smart-1952d483-e985-441f-9bfc-e3579f7120af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340961114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.1340961114
Directory /workspace/29.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.378514232
Short name T1491
Test name
Test status
Simulation time 19267636802 ps
CPU time 202.8 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:13:07 PM PST 24
Peak memory 553088 kb
Host smart-d916f233-e86a-41dd-8930-6de22318e49f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378514232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.378514232
Directory /workspace/29.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.1718656217
Short name T1517
Test name
Test status
Simulation time 36986408638 ps
CPU time 646.22 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:20:35 PM PST 24
Peak memory 553876 kb
Host smart-b676e807-ed1a-49db-be43-eaec8d88601e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718656217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1718656217
Directory /workspace/29.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.3475689779
Short name T1193
Test name
Test status
Simulation time 79099196 ps
CPU time 10.1 seconds
Started Jan 03 02:09:53 PM PST 24
Finished Jan 03 02:10:06 PM PST 24
Peak memory 553060 kb
Host smart-6a52f07a-6a0f-478b-a127-d8ea2ee40a82
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475689779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del
ays.3475689779
Directory /workspace/29.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_same_source.2090556104
Short name T1555
Test name
Test status
Simulation time 2050763270 ps
CPU time 58.72 seconds
Started Jan 03 02:09:39 PM PST 24
Finished Jan 03 02:10:45 PM PST 24
Peak memory 554196 kb
Host smart-148fdb69-f3e8-4f1d-9748-857aed9f63ca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090556104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.2090556104
Directory /workspace/29.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke.1676629395
Short name T373
Test name
Test status
Simulation time 143778035 ps
CPU time 7.42 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:09:51 PM PST 24
Peak memory 552096 kb
Host smart-44febddb-6061-407d-9706-b7177ae1c818
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676629395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1676629395
Directory /workspace/29.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.493428947
Short name T983
Test name
Test status
Simulation time 4900972586 ps
CPU time 47.89 seconds
Started Jan 03 02:09:49 PM PST 24
Finished Jan 03 02:10:41 PM PST 24
Peak memory 552140 kb
Host smart-c9c0596c-25a8-4b62-aada-8a4c7f85c929
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493428947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.493428947
Directory /workspace/29.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1519024413
Short name T454
Test name
Test status
Simulation time 6933533431 ps
CPU time 118.07 seconds
Started Jan 03 02:09:55 PM PST 24
Finished Jan 03 02:11:56 PM PST 24
Peak memory 552140 kb
Host smart-629ab202-964e-4272-a836-7a7acd474aa1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519024413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1519024413
Directory /workspace/29.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.3959950045
Short name T1089
Test name
Test status
Simulation time 45259550 ps
CPU time 5.92 seconds
Started Jan 03 02:09:48 PM PST 24
Finished Jan 03 02:09:58 PM PST 24
Peak memory 551768 kb
Host smart-56570133-add2-42fd-8ae7-284f0d2790e6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959950045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay
s.3959950045
Directory /workspace/29.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all.3628383658
Short name T1817
Test name
Test status
Simulation time 11386227919 ps
CPU time 419.55 seconds
Started Jan 03 02:09:52 PM PST 24
Finished Jan 03 02:16:55 PM PST 24
Peak memory 555412 kb
Host smart-1345d520-1792-4b97-aa5c-53b6d6f12fd0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628383658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3628383658
Directory /workspace/29.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.2986474358
Short name T859
Test name
Test status
Simulation time 851483335 ps
CPU time 62.3 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:10:46 PM PST 24
Peak memory 554032 kb
Host smart-48e04457-0f2c-4af0-87e3-8f69ea4ec2c0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986474358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2986474358
Directory /workspace/29.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.2897945911
Short name T956
Test name
Test status
Simulation time 24388238 ps
CPU time 21.04 seconds
Started Jan 03 02:09:52 PM PST 24
Finished Jan 03 02:10:16 PM PST 24
Peak memory 553312 kb
Host smart-997ff36b-e810-4057-8285-d0ccbae606a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897945911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all
_with_rand_reset.2897945911
Directory /workspace/29.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2480833907
Short name T1703
Test name
Test status
Simulation time 11235635148 ps
CPU time 477.53 seconds
Started Jan 03 02:10:00 PM PST 24
Finished Jan 03 02:18:06 PM PST 24
Peak memory 558488 kb
Host smart-d7612c42-70cb-4592-9bbb-6cc6851653ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480833907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al
l_with_reset_error.2480833907
Directory /workspace/29.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.4059031849
Short name T1313
Test name
Test status
Simulation time 655467827 ps
CPU time 26.51 seconds
Started Jan 03 02:10:00 PM PST 24
Finished Jan 03 02:10:35 PM PST 24
Peak memory 554184 kb
Host smart-ee4a31b6-df93-449d-a1ef-fa879017e37e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059031849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.4059031849
Directory /workspace/29.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.3883275299
Short name T1513
Test name
Test status
Simulation time 35403821042 ps
CPU time 4002.55 seconds
Started Jan 03 02:07:35 PM PST 24
Finished Jan 03 03:14:27 PM PST 24
Peak memory 580000 kb
Host smart-90a7020b-15bf-451d-aaf5-74e8d033a576
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883275299 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.chip_csr_aliasing.3883275299
Directory /workspace/3.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.852320550
Short name T1436
Test name
Test status
Simulation time 9382038642 ps
CPU time 1116.65 seconds
Started Jan 03 02:07:38 PM PST 24
Finished Jan 03 02:26:27 PM PST 24
Peak memory 580004 kb
Host smart-4c1c2458-5896-4107-a92e-021c001080bc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852320550 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.852320550
Directory /workspace/3.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.3184998395
Short name T1715
Test name
Test status
Simulation time 8916795864 ps
CPU time 322.76 seconds
Started Jan 03 02:08:25 PM PST 24
Finished Jan 03 02:13:57 PM PST 24
Peak memory 630224 kb
Host smart-30847b53-22be-4d7f-9d07-05310d5b2642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184998395 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.3184998395
Directory /workspace/3.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.chip_csr_rw.3811531685
Short name T1794
Test name
Test status
Simulation time 4894418575 ps
CPU time 465.84 seconds
Started Jan 03 02:08:25 PM PST 24
Finished Jan 03 02:16:19 PM PST 24
Peak memory 580292 kb
Host smart-e6aebf57-3308-4bb4-a0e1-3f1163725dab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811531685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.3811531685
Directory /workspace/3.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.406266339
Short name T760
Test name
Test status
Simulation time 14306125442 ps
CPU time 1789.57 seconds
Started Jan 03 02:07:35 PM PST 24
Finished Jan 03 02:37:34 PM PST 24
Peak memory 580024 kb
Host smart-ea5ffad7-c4e8-4ead-b0a3-7dff37c96b33
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406266339 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.chip_same_csr_outstanding.406266339
Directory /workspace/3.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.chip_tl_errors.819018130
Short name T967
Test name
Test status
Simulation time 2066306104 ps
CPU time 82.77 seconds
Started Jan 03 02:08:07 PM PST 24
Finished Jan 03 02:09:36 PM PST 24
Peak memory 579972 kb
Host smart-9ef7a90f-0bd9-4e97-85a8-adb557d3a049
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819018130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.819018130
Directory /workspace/3.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_access_same_device.361753059
Short name T1457
Test name
Test status
Simulation time 2754565736 ps
CPU time 101.32 seconds
Started Jan 03 02:08:23 PM PST 24
Finished Jan 03 02:10:13 PM PST 24
Peak memory 554284 kb
Host smart-579fb7e3-b51b-450e-9c0e-4a516f6cf303
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361753059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.361753059
Directory /workspace/3.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2414608628
Short name T321
Test name
Test status
Simulation time 19774524838 ps
CPU time 311.39 seconds
Started Jan 03 02:08:19 PM PST 24
Finished Jan 03 02:13:38 PM PST 24
Peak memory 553140 kb
Host smart-27850749-7502-458a-8507-d07a7cffef3c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414608628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d
evice_slow_rsp.2414608628
Directory /workspace/3.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.725353626
Short name T372
Test name
Test status
Simulation time 301980809 ps
CPU time 31.71 seconds
Started Jan 03 02:08:14 PM PST 24
Finished Jan 03 02:08:49 PM PST 24
Peak memory 554076 kb
Host smart-3b863172-64b4-42d7-ab89-ef14cd67ad65
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725353626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.
725353626
Directory /workspace/3.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_error_random.2165580660
Short name T1708
Test name
Test status
Simulation time 254781084 ps
CPU time 22.62 seconds
Started Jan 03 02:07:56 PM PST 24
Finished Jan 03 02:08:29 PM PST 24
Peak memory 553864 kb
Host smart-a9864eea-f4f0-4f00-9d4d-4e53379eacfd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165580660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2165580660
Directory /workspace/3.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random.2332294207
Short name T613
Test name
Test status
Simulation time 1383557903 ps
CPU time 44.08 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:08:52 PM PST 24
Peak memory 554144 kb
Host smart-4d6dc976-1d9a-4d60-a3df-85bf4d20e255
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332294207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.2332294207
Directory /workspace/3.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.1763011921
Short name T545
Test name
Test status
Simulation time 28647546098 ps
CPU time 311.46 seconds
Started Jan 03 02:08:15 PM PST 24
Finished Jan 03 02:13:31 PM PST 24
Peak memory 554236 kb
Host smart-7ebe3194-72c9-4091-ba78-bbace9b8fd95
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763011921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1763011921
Directory /workspace/3.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.3169579699
Short name T1545
Test name
Test status
Simulation time 46512831253 ps
CPU time 745.12 seconds
Started Jan 03 02:08:12 PM PST 24
Finished Jan 03 02:20:40 PM PST 24
Peak memory 554248 kb
Host smart-a90f2b3f-c322-40ca-9b0d-de2b46821a60
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169579699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3169579699
Directory /workspace/3.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.1119433749
Short name T921
Test name
Test status
Simulation time 102318426 ps
CPU time 11.17 seconds
Started Jan 03 02:07:57 PM PST 24
Finished Jan 03 02:08:19 PM PST 24
Peak memory 554160 kb
Host smart-27d82fa9-5251-4eb1-b694-6ea68eb6cd77
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119433749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela
ys.1119433749
Directory /workspace/3.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_same_source.1188009430
Short name T1852
Test name
Test status
Simulation time 348446214 ps
CPU time 22.55 seconds
Started Jan 03 02:08:04 PM PST 24
Finished Jan 03 02:08:35 PM PST 24
Peak memory 554164 kb
Host smart-f974809d-8a77-4739-9052-30f29b4386ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188009430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1188009430
Directory /workspace/3.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke.2128675872
Short name T1629
Test name
Test status
Simulation time 218995476 ps
CPU time 9.43 seconds
Started Jan 03 02:08:13 PM PST 24
Finished Jan 03 02:08:25 PM PST 24
Peak memory 551848 kb
Host smart-2b007c9c-fe62-42a5-8ae8-23251d8609a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128675872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2128675872
Directory /workspace/3.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.643826827
Short name T725
Test name
Test status
Simulation time 9673298920 ps
CPU time 113.8 seconds
Started Jan 03 02:07:42 PM PST 24
Finished Jan 03 02:09:47 PM PST 24
Peak memory 551956 kb
Host smart-cb08063c-61df-4541-8366-a2fbe84f045f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643826827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.643826827
Directory /workspace/3.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.1460620572
Short name T769
Test name
Test status
Simulation time 5522581664 ps
CPU time 96.98 seconds
Started Jan 03 02:07:44 PM PST 24
Finished Jan 03 02:09:33 PM PST 24
Peak memory 552132 kb
Host smart-5a5b55df-b46e-4c97-a6b8-b90b567abcaf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460620572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1460620572
Directory /workspace/3.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.177618553
Short name T787
Test name
Test status
Simulation time 49956121 ps
CPU time 6.17 seconds
Started Jan 03 02:08:22 PM PST 24
Finished Jan 03 02:08:37 PM PST 24
Peak memory 552052 kb
Host smart-32e9d0c5-83f7-4850-af7c-695bb833020c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177618553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.
177618553
Directory /workspace/3.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all.729073277
Short name T902
Test name
Test status
Simulation time 2698762805 ps
CPU time 98.08 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:10:01 PM PST 24
Peak memory 555404 kb
Host smart-105bf82a-c69a-4738-ba64-788254731564
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729073277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.729073277
Directory /workspace/3.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.2155115666
Short name T1338
Test name
Test status
Simulation time 1799060778 ps
CPU time 146.47 seconds
Started Jan 03 02:08:26 PM PST 24
Finished Jan 03 02:11:01 PM PST 24
Peak memory 555340 kb
Host smart-8d66b032-c4e4-4030-9f91-b8eed7353aff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155115666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2155115666
Directory /workspace/3.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.4282596333
Short name T778
Test name
Test status
Simulation time 324781073 ps
CPU time 174.56 seconds
Started Jan 03 02:08:11 PM PST 24
Finished Jan 03 02:11:09 PM PST 24
Peak memory 556200 kb
Host smart-e8747f2e-9418-410f-9726-06b81352cb17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282596333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_
with_rand_reset.4282596333
Directory /workspace/3.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1943663470
Short name T1210
Test name
Test status
Simulation time 521541808 ps
CPU time 125.37 seconds
Started Jan 03 02:08:25 PM PST 24
Finished Jan 03 02:10:39 PM PST 24
Peak memory 555976 kb
Host smart-056b7441-58a4-4cea-9731-7d078464630e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943663470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all
_with_reset_error.1943663470
Directory /workspace/3.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.3346172966
Short name T178
Test name
Test status
Simulation time 276428795 ps
CPU time 30.59 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:08:54 PM PST 24
Peak memory 553900 kb
Host smart-13df2d9d-3a7f-4f06-8f03-ce21a44edf17
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346172966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3346172966
Directory /workspace/3.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_access_same_device.1320485884
Short name T394
Test name
Test status
Simulation time 310354021 ps
CPU time 24.98 seconds
Started Jan 03 02:08:58 PM PST 24
Finished Jan 03 02:09:25 PM PST 24
Peak memory 553128 kb
Host smart-09f56d78-403b-4565-a0f6-e14905d19428
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320485884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device
.1320485884
Directory /workspace/30.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.1618137053
Short name T1085
Test name
Test status
Simulation time 95153486532 ps
CPU time 1583.74 seconds
Started Jan 03 02:08:48 PM PST 24
Finished Jan 03 02:35:16 PM PST 24
Peak memory 555012 kb
Host smart-c0d4a11e-67f9-4198-8b26-10f923d54d80
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618137053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_
device_slow_rsp.1618137053
Directory /workspace/30.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3267947100
Short name T614
Test name
Test status
Simulation time 207870307 ps
CPU time 21.49 seconds
Started Jan 03 02:08:56 PM PST 24
Finished Jan 03 02:09:20 PM PST 24
Peak memory 552848 kb
Host smart-c45699ee-7dd5-449d-b97d-ee64c0935b77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267947100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add
r.3267947100
Directory /workspace/30.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_error_random.2147976283
Short name T1579
Test name
Test status
Simulation time 42012557 ps
CPU time 6.58 seconds
Started Jan 03 02:08:55 PM PST 24
Finished Jan 03 02:09:05 PM PST 24
Peak memory 551752 kb
Host smart-5fe725b7-4f26-4898-895f-da2135e3e34e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147976283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2147976283
Directory /workspace/30.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random.589730898
Short name T954
Test name
Test status
Simulation time 656835717 ps
CPU time 51.16 seconds
Started Jan 03 02:08:44 PM PST 24
Finished Jan 03 02:09:41 PM PST 24
Peak memory 553052 kb
Host smart-cef29795-49ac-4b28-ab49-1c57a40ac61a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589730898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.589730898
Directory /workspace/30.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.2386934888
Short name T1562
Test name
Test status
Simulation time 109932400938 ps
CPU time 1153.08 seconds
Started Jan 03 02:08:53 PM PST 24
Finished Jan 03 02:28:10 PM PST 24
Peak memory 554244 kb
Host smart-fbc6633d-f7c1-43bc-abe0-82091fe1b447
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386934888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2386934888
Directory /workspace/30.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.135791810
Short name T1412
Test name
Test status
Simulation time 3172800542 ps
CPU time 58.17 seconds
Started Jan 03 02:08:53 PM PST 24
Finished Jan 03 02:09:55 PM PST 24
Peak memory 552168 kb
Host smart-9c189f73-da34-4c47-ae95-42eb599b1537
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135791810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.135791810
Directory /workspace/30.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.1531387295
Short name T100
Test name
Test status
Simulation time 450899756 ps
CPU time 36.49 seconds
Started Jan 03 02:08:58 PM PST 24
Finished Jan 03 02:09:38 PM PST 24
Peak memory 554172 kb
Host smart-c3d33b09-050e-471f-b2a8-f622c7e6e8df
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531387295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del
ays.1531387295
Directory /workspace/30.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke.874516775
Short name T226
Test name
Test status
Simulation time 43030763 ps
CPU time 6 seconds
Started Jan 03 02:10:36 PM PST 24
Finished Jan 03 02:10:55 PM PST 24
Peak memory 551812 kb
Host smart-ea3b13f7-dcdf-4a08-96f3-72dcd136b6d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874516775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.874516775
Directory /workspace/30.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.1651210720
Short name T1088
Test name
Test status
Simulation time 5969080199 ps
CPU time 59.79 seconds
Started Jan 03 02:09:57 PM PST 24
Finished Jan 03 02:11:03 PM PST 24
Peak memory 551952 kb
Host smart-b2643ebb-0af4-456c-8231-733304825c7f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651210720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1651210720
Directory /workspace/30.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1983489058
Short name T402
Test name
Test status
Simulation time 5209057303 ps
CPU time 90.21 seconds
Started Jan 03 02:10:01 PM PST 24
Finished Jan 03 02:11:44 PM PST 24
Peak memory 551884 kb
Host smart-affacd9d-f924-4262-b57e-00993b277e22
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983489058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.1983489058
Directory /workspace/30.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2139231396
Short name T1811
Test name
Test status
Simulation time 57961326 ps
CPU time 6.74 seconds
Started Jan 03 02:09:59 PM PST 24
Finished Jan 03 02:10:12 PM PST 24
Peak memory 552008 kb
Host smart-ac737360-0666-4926-bfca-e156c06868ed
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139231396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay
s.2139231396
Directory /workspace/30.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all.2453182819
Short name T1809
Test name
Test status
Simulation time 69539148 ps
CPU time 8.44 seconds
Started Jan 03 02:09:25 PM PST 24
Finished Jan 03 02:09:43 PM PST 24
Peak memory 551908 kb
Host smart-75b22dde-be44-4038-a625-c20cbdeb9913
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453182819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2453182819
Directory /workspace/30.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.1012615419
Short name T958
Test name
Test status
Simulation time 2397370653 ps
CPU time 74.42 seconds
Started Jan 03 02:08:58 PM PST 24
Finished Jan 03 02:10:15 PM PST 24
Peak memory 555244 kb
Host smart-f36b1ed4-b5d1-4aa7-8263-6e8e83fd3fba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012615419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1012615419
Directory /workspace/30.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1930718508
Short name T361
Test name
Test status
Simulation time 1009156390 ps
CPU time 176.44 seconds
Started Jan 03 02:09:03 PM PST 24
Finished Jan 03 02:12:05 PM PST 24
Peak memory 555432 kb
Host smart-4671b41d-9352-4278-938c-25d145224779
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930718508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all
_with_rand_reset.1930718508
Directory /workspace/30.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2340813833
Short name T679
Test name
Test status
Simulation time 243692924 ps
CPU time 66.43 seconds
Started Jan 03 02:09:34 PM PST 24
Finished Jan 03 02:10:48 PM PST 24
Peak memory 555028 kb
Host smart-9d749958-efb2-4951-ad9e-855a1a36131f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340813833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al
l_with_reset_error.2340813833
Directory /workspace/30.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.4193193787
Short name T398
Test name
Test status
Simulation time 478892884 ps
CPU time 19.52 seconds
Started Jan 03 02:09:04 PM PST 24
Finished Jan 03 02:09:28 PM PST 24
Peak memory 554164 kb
Host smart-252aad2b-7933-446d-bef6-0070e4847aa4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193193787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.4193193787
Directory /workspace/30.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_access_same_device.1562033440
Short name T316
Test name
Test status
Simulation time 1000744472 ps
CPU time 39.5 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:10:24 PM PST 24
Peak memory 553892 kb
Host smart-9add2b07-54c7-46ad-bc85-a825816de16e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562033440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device
.1562033440
Directory /workspace/31.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.344302056
Short name T1475
Test name
Test status
Simulation time 16497017021 ps
CPU time 283.86 seconds
Started Jan 03 02:09:34 PM PST 24
Finished Jan 03 02:14:25 PM PST 24
Peak memory 554236 kb
Host smart-aac8aec6-3173-4fc0-888a-94d1469edce1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344302056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_d
evice_slow_rsp.344302056
Directory /workspace/31.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.1833367588
Short name T403
Test name
Test status
Simulation time 144362929 ps
CPU time 16 seconds
Started Jan 03 02:09:31 PM PST 24
Finished Jan 03 02:09:55 PM PST 24
Peak memory 554128 kb
Host smart-257e4bd7-d164-4a36-a1f9-3969aab322e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833367588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add
r.1833367588
Directory /workspace/31.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_error_random.3131632663
Short name T666
Test name
Test status
Simulation time 141403596 ps
CPU time 15.7 seconds
Started Jan 03 02:09:38 PM PST 24
Finished Jan 03 02:10:01 PM PST 24
Peak memory 554096 kb
Host smart-dab54ddd-cfa1-4d33-b7a4-58b826ad9283
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131632663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3131632663
Directory /workspace/31.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random.617731401
Short name T1342
Test name
Test status
Simulation time 746715841 ps
CPU time 31.64 seconds
Started Jan 03 02:09:05 PM PST 24
Finished Jan 03 02:09:41 PM PST 24
Peak memory 554124 kb
Host smart-4c04d4ac-e565-4def-afe5-9e76feab63dc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617731401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.617731401
Directory /workspace/31.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.1807996934
Short name T131
Test name
Test status
Simulation time 50352758003 ps
CPU time 558.13 seconds
Started Jan 03 02:09:06 PM PST 24
Finished Jan 03 02:18:29 PM PST 24
Peak memory 554192 kb
Host smart-ef1ca4a0-4346-44be-895d-8a12deddec26
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807996934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1807996934
Directory /workspace/31.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.1291687561
Short name T469
Test name
Test status
Simulation time 9732958271 ps
CPU time 163.45 seconds
Started Jan 03 02:09:35 PM PST 24
Finished Jan 03 02:12:26 PM PST 24
Peak memory 554224 kb
Host smart-d7b2c92d-e579-45a0-ae48-8c396eff5165
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291687561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1291687561
Directory /workspace/31.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.694834504
Short name T974
Test name
Test status
Simulation time 96876259 ps
CPU time 11.63 seconds
Started Jan 03 02:09:05 PM PST 24
Finished Jan 03 02:09:21 PM PST 24
Peak memory 553840 kb
Host smart-0cf349c1-3ef9-4daa-a9f7-b506d2b203d4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694834504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_dela
ys.694834504
Directory /workspace/31.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_same_source.4185372626
Short name T1655
Test name
Test status
Simulation time 2031442886 ps
CPU time 56.39 seconds
Started Jan 03 02:09:17 PM PST 24
Finished Jan 03 02:10:15 PM PST 24
Peak memory 554264 kb
Host smart-008c2da9-b567-4e5a-a01c-82a7b6086193
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185372626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.4185372626
Directory /workspace/31.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke.1382639033
Short name T1322
Test name
Test status
Simulation time 51917167 ps
CPU time 6.28 seconds
Started Jan 03 02:09:35 PM PST 24
Finished Jan 03 02:09:48 PM PST 24
Peak memory 552088 kb
Host smart-4785d4ec-1bce-4128-9d81-db255d6bfdef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382639033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1382639033
Directory /workspace/31.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.205808364
Short name T758
Test name
Test status
Simulation time 6949226625 ps
CPU time 69.38 seconds
Started Jan 03 02:09:05 PM PST 24
Finished Jan 03 02:10:19 PM PST 24
Peak memory 552112 kb
Host smart-a349e401-230b-459c-addb-c5d855e6f961
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205808364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.205808364
Directory /workspace/31.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.3853647000
Short name T1522
Test name
Test status
Simulation time 2817836374 ps
CPU time 46.35 seconds
Started Jan 03 02:09:06 PM PST 24
Finished Jan 03 02:09:57 PM PST 24
Peak memory 551828 kb
Host smart-498827b8-7489-4454-b54b-7aa3676af57a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853647000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3853647000
Directory /workspace/31.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1443558715
Short name T1387
Test name
Test status
Simulation time 40571585 ps
CPU time 5.69 seconds
Started Jan 03 02:09:05 PM PST 24
Finished Jan 03 02:09:15 PM PST 24
Peak memory 552032 kb
Host smart-1a80a82f-6de1-4dc3-9f2e-88330609faff
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443558715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay
s.1443558715
Directory /workspace/31.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all.2412097652
Short name T1838
Test name
Test status
Simulation time 4198748794 ps
CPU time 152.12 seconds
Started Jan 03 02:09:35 PM PST 24
Finished Jan 03 02:12:15 PM PST 24
Peak memory 555096 kb
Host smart-82cff9e8-2db2-44a1-bf7c-a8e31267f141
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412097652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2412097652
Directory /workspace/31.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.3040192723
Short name T420
Test name
Test status
Simulation time 4861790212 ps
CPU time 168.23 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:12:38 PM PST 24
Peak memory 554960 kb
Host smart-7858fcc7-a8a2-4657-97de-dd1fc0fc675c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040192723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3040192723
Directory /workspace/31.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2599117417
Short name T740
Test name
Test status
Simulation time 2120124300 ps
CPU time 229.52 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:13:39 PM PST 24
Peak memory 556020 kb
Host smart-85e65b17-08dd-492b-997f-29ee22d3200d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599117417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all
_with_rand_reset.2599117417
Directory /workspace/31.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2244103021
Short name T745
Test name
Test status
Simulation time 791202758 ps
CPU time 283.1 seconds
Started Jan 03 02:09:39 PM PST 24
Finished Jan 03 02:14:30 PM PST 24
Peak memory 558972 kb
Host smart-99dc879b-f6d4-48eb-9dd0-bc77105d2ff7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244103021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al
l_with_reset_error.2244103021
Directory /workspace/31.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.2958677132
Short name T1026
Test name
Test status
Simulation time 717015751 ps
CPU time 29.77 seconds
Started Jan 03 02:09:11 PM PST 24
Finished Jan 03 02:09:44 PM PST 24
Peak memory 554216 kb
Host smart-8ba96ed1-d64f-4561-929a-764fa3ae043a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958677132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.2958677132
Directory /workspace/31.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_access_same_device.910258622
Short name T306
Test name
Test status
Simulation time 895675314 ps
CPU time 58.14 seconds
Started Jan 03 02:09:31 PM PST 24
Finished Jan 03 02:10:37 PM PST 24
Peak memory 554936 kb
Host smart-43a70d39-7941-45de-aa4f-304278944e39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910258622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.
910258622
Directory /workspace/32.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.348478635
Short name T1691
Test name
Test status
Simulation time 15176685695 ps
CPU time 244.37 seconds
Started Jan 03 02:09:14 PM PST 24
Finished Jan 03 02:13:22 PM PST 24
Peak memory 553988 kb
Host smart-bf9497dd-18cd-4628-91dd-53431c09d804
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348478635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_d
evice_slow_rsp.348478635
Directory /workspace/32.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1535901369
Short name T605
Test name
Test status
Simulation time 1154279875 ps
CPU time 44.42 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:10:28 PM PST 24
Peak memory 552852 kb
Host smart-cb2d53bf-609c-4298-80ff-d5e18f2342ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535901369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add
r.1535901369
Directory /workspace/32.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_error_random.1750524099
Short name T1416
Test name
Test status
Simulation time 1867911047 ps
CPU time 60.48 seconds
Started Jan 03 02:09:35 PM PST 24
Finished Jan 03 02:10:43 PM PST 24
Peak memory 553804 kb
Host smart-9216dd88-d04c-4bc0-99fd-eaf0a5efe293
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750524099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1750524099
Directory /workspace/32.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random.489025736
Short name T1312
Test name
Test status
Simulation time 551626895 ps
CPU time 44.23 seconds
Started Jan 03 02:09:35 PM PST 24
Finished Jan 03 02:10:27 PM PST 24
Peak memory 554200 kb
Host smart-84f5a6c3-5769-47a9-b235-160ba3782804
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489025736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.489025736
Directory /workspace/32.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.2173021436
Short name T680
Test name
Test status
Simulation time 72909332822 ps
CPU time 779.38 seconds
Started Jan 03 02:09:32 PM PST 24
Finished Jan 03 02:22:39 PM PST 24
Peak memory 553064 kb
Host smart-04829f50-7967-4333-8ec1-7305d39b305e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173021436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2173021436
Directory /workspace/32.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.315508628
Short name T867
Test name
Test status
Simulation time 9679234289 ps
CPU time 168.56 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:12:38 PM PST 24
Peak memory 553940 kb
Host smart-f5b26c1f-6f50-414a-ba40-81742fc6eccc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315508628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.315508628
Directory /workspace/32.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.3288660651
Short name T1572
Test name
Test status
Simulation time 489574046 ps
CPU time 41.3 seconds
Started Jan 03 02:09:17 PM PST 24
Finished Jan 03 02:10:00 PM PST 24
Peak memory 553972 kb
Host smart-f43983d6-3217-4015-a0b6-6cd73d03ea78
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288660651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del
ays.3288660651
Directory /workspace/32.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_same_source.3276506717
Short name T1421
Test name
Test status
Simulation time 2269217059 ps
CPU time 65.68 seconds
Started Jan 03 02:09:29 PM PST 24
Finished Jan 03 02:10:43 PM PST 24
Peak memory 553968 kb
Host smart-0b01b6c9-430d-4aab-85e9-a17fcb2f9689
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276506717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3276506717
Directory /workspace/32.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke.2926777545
Short name T1504
Test name
Test status
Simulation time 219031212 ps
CPU time 8.88 seconds
Started Jan 03 02:09:47 PM PST 24
Finished Jan 03 02:10:00 PM PST 24
Peak memory 551816 kb
Host smart-751d1397-5ca5-4fcf-a50f-ff0033566ab4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926777545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2926777545
Directory /workspace/32.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.4013282657
Short name T773
Test name
Test status
Simulation time 8980652546 ps
CPU time 93.88 seconds
Started Jan 03 02:09:14 PM PST 24
Finished Jan 03 02:10:51 PM PST 24
Peak memory 551848 kb
Host smart-bcce96d3-b3e1-4890-9975-b142638a301d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013282657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.4013282657
Directory /workspace/32.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.1169995941
Short name T1759
Test name
Test status
Simulation time 4769696690 ps
CPU time 81.14 seconds
Started Jan 03 02:09:10 PM PST 24
Finished Jan 03 02:10:35 PM PST 24
Peak memory 552088 kb
Host smart-f3cc53b1-acf0-4dd3-89e1-dde160ec4d53
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169995941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1169995941
Directory /workspace/32.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.4241909143
Short name T641
Test name
Test status
Simulation time 56644993 ps
CPU time 6.53 seconds
Started Jan 03 02:09:09 PM PST 24
Finished Jan 03 02:09:20 PM PST 24
Peak memory 552032 kb
Host smart-ca42c865-af5b-4c1a-8df9-837e547d8096
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241909143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay
s.4241909143
Directory /workspace/32.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all.3849467455
Short name T742
Test name
Test status
Simulation time 2202311165 ps
CPU time 93.37 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:11:18 PM PST 24
Peak memory 555388 kb
Host smart-33269d21-cdb0-4c92-96b5-6ae598e469dc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849467455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3849467455
Directory /workspace/32.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.2510370248
Short name T453
Test name
Test status
Simulation time 1179162925 ps
CPU time 102.52 seconds
Started Jan 03 02:09:33 PM PST 24
Finished Jan 03 02:11:24 PM PST 24
Peak memory 555256 kb
Host smart-818f9980-9878-4c42-85d1-282841d1dc8f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510370248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2510370248
Directory /workspace/32.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3793911314
Short name T1713
Test name
Test status
Simulation time 2106675027 ps
CPU time 399.93 seconds
Started Jan 03 02:09:24 PM PST 24
Finished Jan 03 02:16:14 PM PST 24
Peak memory 556808 kb
Host smart-3e528c1a-6b81-4515-b0c6-893153e2285e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793911314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all
_with_rand_reset.3793911314
Directory /workspace/32.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.625859789
Short name T360
Test name
Test status
Simulation time 2975980811 ps
CPU time 390.84 seconds
Started Jan 03 02:09:15 PM PST 24
Finished Jan 03 02:15:49 PM PST 24
Peak memory 559080 kb
Host smart-d7bc1b35-c215-474c-b744-289976517cde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625859789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all
_with_reset_error.625859789
Directory /workspace/32.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.2411041337
Short name T492
Test name
Test status
Simulation time 23130018 ps
CPU time 5.51 seconds
Started Jan 03 02:09:20 PM PST 24
Finished Jan 03 02:09:33 PM PST 24
Peak memory 551780 kb
Host smart-490c226d-e900-498e-8725-3656016aa920
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411041337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2411041337
Directory /workspace/32.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_access_same_device.2803272920
Short name T892
Test name
Test status
Simulation time 589415315 ps
CPU time 49.38 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:10:38 PM PST 24
Peak memory 554144 kb
Host smart-b49a0c1f-711a-43ea-91e9-11eb78755991
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803272920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device
.2803272920
Directory /workspace/33.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3176049475
Short name T1154
Test name
Test status
Simulation time 13508540134 ps
CPU time 224.81 seconds
Started Jan 03 02:09:49 PM PST 24
Finished Jan 03 02:13:38 PM PST 24
Peak memory 554252 kb
Host smart-78054fa2-0abf-413c-8058-fab2533d4dfc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176049475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_
device_slow_rsp.3176049475
Directory /workspace/33.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3215181449
Short name T774
Test name
Test status
Simulation time 329953035 ps
CPU time 37.91 seconds
Started Jan 03 02:09:56 PM PST 24
Finished Jan 03 02:10:40 PM PST 24
Peak memory 553852 kb
Host smart-83c7b2a2-da55-4afc-88c2-48ab8bb61de4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215181449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add
r.3215181449
Directory /workspace/33.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_error_random.3109763742
Short name T534
Test name
Test status
Simulation time 1066444294 ps
CPU time 35.28 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:10:20 PM PST 24
Peak memory 552948 kb
Host smart-a87a3671-b242-4544-aabd-09142e98af0a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109763742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3109763742
Directory /workspace/33.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random.716164523
Short name T1870
Test name
Test status
Simulation time 2096207439 ps
CPU time 67.96 seconds
Started Jan 03 02:09:50 PM PST 24
Finished Jan 03 02:11:01 PM PST 24
Peak memory 554212 kb
Host smart-8e2aeb0b-389b-46b3-8c3e-1efe1af3d78b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716164523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.716164523
Directory /workspace/33.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.235669143
Short name T918
Test name
Test status
Simulation time 99617824633 ps
CPU time 956.37 seconds
Started Jan 03 02:09:41 PM PST 24
Finished Jan 03 02:25:45 PM PST 24
Peak memory 554236 kb
Host smart-62ce19c1-4e05-4063-9107-367ce7809172
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235669143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.235669143
Directory /workspace/33.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.3014445289
Short name T1892
Test name
Test status
Simulation time 35502251152 ps
CPU time 607.51 seconds
Started Jan 03 02:09:53 PM PST 24
Finished Jan 03 02:20:03 PM PST 24
Peak memory 554304 kb
Host smart-bfeaa8b4-6962-4bef-877a-e0c776703911
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014445289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3014445289
Directory /workspace/33.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.2335693398
Short name T1679
Test name
Test status
Simulation time 332731748 ps
CPU time 32.81 seconds
Started Jan 03 02:09:56 PM PST 24
Finished Jan 03 02:10:33 PM PST 24
Peak memory 553860 kb
Host smart-88aaf346-f467-4970-bbde-5e4999c051b3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335693398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del
ays.2335693398
Directory /workspace/33.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_same_source.3603447854
Short name T771
Test name
Test status
Simulation time 165029144 ps
CPU time 13.26 seconds
Started Jan 03 02:09:55 PM PST 24
Finished Jan 03 02:10:11 PM PST 24
Peak memory 554132 kb
Host smart-d0ae4f43-6966-4eb7-b0e3-2ba44be8e273
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603447854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3603447854
Directory /workspace/33.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke.2971160323
Short name T364
Test name
Test status
Simulation time 204862000 ps
CPU time 8.7 seconds
Started Jan 03 02:09:13 PM PST 24
Finished Jan 03 02:09:25 PM PST 24
Peak memory 551876 kb
Host smart-96df2861-4f50-4bd0-82b1-badc35e4f150
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971160323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2971160323
Directory /workspace/33.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.2433593387
Short name T579
Test name
Test status
Simulation time 6733956466 ps
CPU time 69.64 seconds
Started Jan 03 02:09:45 PM PST 24
Finished Jan 03 02:11:00 PM PST 24
Peak memory 551844 kb
Host smart-50589225-b459-4a4d-bc76-69a4320a3f59
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433593387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2433593387
Directory /workspace/33.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.2376124569
Short name T1388
Test name
Test status
Simulation time 5314833531 ps
CPU time 93.41 seconds
Started Jan 03 02:09:38 PM PST 24
Finished Jan 03 02:11:19 PM PST 24
Peak memory 551728 kb
Host smart-8a69853b-2dae-4e41-a509-b47d346808f3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376124569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2376124569
Directory /workspace/33.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3631545274
Short name T560
Test name
Test status
Simulation time 36986086 ps
CPU time 5.3 seconds
Started Jan 03 02:09:39 PM PST 24
Finished Jan 03 02:09:52 PM PST 24
Peak memory 552016 kb
Host smart-bbe78a7b-a602-4c4f-8e0e-89270a581c10
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631545274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay
s.3631545274
Directory /workspace/33.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all.2306353113
Short name T802
Test name
Test status
Simulation time 506997614 ps
CPU time 18.15 seconds
Started Jan 03 02:09:59 PM PST 24
Finished Jan 03 02:10:24 PM PST 24
Peak memory 554204 kb
Host smart-ad055b90-cf8c-494d-ab3b-1174acd0c560
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306353113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.2306353113
Directory /workspace/33.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.2388861570
Short name T1348
Test name
Test status
Simulation time 2414587152 ps
CPU time 195.9 seconds
Started Jan 03 02:09:54 PM PST 24
Finished Jan 03 02:13:12 PM PST 24
Peak memory 555144 kb
Host smart-5b127376-aa19-4baf-a0ae-4bce1b0f8d77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388861570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2388861570
Directory /workspace/33.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3698020807
Short name T1488
Test name
Test status
Simulation time 16024352513 ps
CPU time 749.44 seconds
Started Jan 03 02:09:57 PM PST 24
Finished Jan 03 02:22:33 PM PST 24
Peak memory 556528 kb
Host smart-3c7f5127-1f4c-48e2-b9a5-4bac7c494d05
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698020807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all
_with_rand_reset.3698020807
Directory /workspace/33.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1994420477
Short name T500
Test name
Test status
Simulation time 150332283 ps
CPU time 58.47 seconds
Started Jan 03 02:09:18 PM PST 24
Finished Jan 03 02:10:20 PM PST 24
Peak memory 555048 kb
Host smart-b424bcff-b15f-498b-8fa6-7fc3d7ea9acc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994420477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al
l_with_reset_error.1994420477
Directory /workspace/33.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.4077640557
Short name T1105
Test name
Test status
Simulation time 1126759867 ps
CPU time 45.49 seconds
Started Jan 03 02:09:49 PM PST 24
Finished Jan 03 02:10:38 PM PST 24
Peak memory 553976 kb
Host smart-74d95f99-336b-4581-8e83-1768ccbaa006
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077640557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.4077640557
Directory /workspace/33.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3220303154
Short name T1741
Test name
Test status
Simulation time 337503188 ps
CPU time 14.71 seconds
Started Jan 03 02:09:16 PM PST 24
Finished Jan 03 02:09:33 PM PST 24
Peak memory 552908 kb
Host smart-e609df6b-f351-4d7f-85ab-4f2db3377a9d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220303154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add
r.3220303154
Directory /workspace/34.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_error_random.824070379
Short name T427
Test name
Test status
Simulation time 1094052270 ps
CPU time 39.34 seconds
Started Jan 03 02:09:43 PM PST 24
Finished Jan 03 02:10:29 PM PST 24
Peak memory 554128 kb
Host smart-b28b80dd-0772-49d9-831e-1391b770d3e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824070379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.824070379
Directory /workspace/34.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random.3392903543
Short name T1786
Test name
Test status
Simulation time 1646006208 ps
CPU time 61.07 seconds
Started Jan 03 02:09:39 PM PST 24
Finished Jan 03 02:10:48 PM PST 24
Peak memory 554120 kb
Host smart-665ef37c-6b39-4b5a-95be-573599d56193
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392903543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.3392903543
Directory /workspace/34.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.2423265567
Short name T1790
Test name
Test status
Simulation time 41824565559 ps
CPU time 463.91 seconds
Started Jan 03 02:09:21 PM PST 24
Finished Jan 03 02:17:12 PM PST 24
Peak memory 554156 kb
Host smart-929effe0-73d3-4451-a388-b8ced8a77aed
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423265567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2423265567
Directory /workspace/34.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.2661352015
Short name T68
Test name
Test status
Simulation time 36794967835 ps
CPU time 551.55 seconds
Started Jan 03 02:09:25 PM PST 24
Finished Jan 03 02:18:46 PM PST 24
Peak memory 554256 kb
Host smart-2238f31a-14a2-4f09-a16f-ec520f77fbfd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661352015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2661352015
Directory /workspace/34.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.1538050192
Short name T1733
Test name
Test status
Simulation time 589506697 ps
CPU time 52.57 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:10:36 PM PST 24
Peak memory 554180 kb
Host smart-bda77e12-f6ee-4d30-a139-432aa14c9fc5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538050192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del
ays.1538050192
Directory /workspace/34.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_same_source.420633008
Short name T751
Test name
Test status
Simulation time 274032041 ps
CPU time 19.98 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:10:09 PM PST 24
Peak memory 554272 kb
Host smart-54edfd8b-069b-4761-887c-49d91f020faf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420633008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.420633008
Directory /workspace/34.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke.3981332051
Short name T1220
Test name
Test status
Simulation time 143585053 ps
CPU time 7.07 seconds
Started Jan 03 02:09:22 PM PST 24
Finished Jan 03 02:09:37 PM PST 24
Peak memory 551728 kb
Host smart-dddb2785-0388-4697-b855-97e5bcdfb3d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981332051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3981332051
Directory /workspace/34.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.2550987475
Short name T1657
Test name
Test status
Simulation time 11177194830 ps
CPU time 118.07 seconds
Started Jan 03 02:09:20 PM PST 24
Finished Jan 03 02:11:25 PM PST 24
Peak memory 551804 kb
Host smart-306c7272-e870-44bb-98d9-591791d35474
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550987475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2550987475
Directory /workspace/34.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1998056675
Short name T168
Test name
Test status
Simulation time 5088549832 ps
CPU time 90.53 seconds
Started Jan 03 02:09:21 PM PST 24
Finished Jan 03 02:10:59 PM PST 24
Peak memory 551804 kb
Host smart-a120abfb-2d27-4e9f-bf55-473b3b38b231
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998056675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1998056675
Directory /workspace/34.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1820147585
Short name T1621
Test name
Test status
Simulation time 42772108 ps
CPU time 5.87 seconds
Started Jan 03 02:09:21 PM PST 24
Finished Jan 03 02:09:34 PM PST 24
Peak memory 551696 kb
Host smart-72b78d94-f6d7-433e-bee9-7d1f6b0ef6bc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820147585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay
s.1820147585
Directory /workspace/34.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all.3054305785
Short name T1192
Test name
Test status
Simulation time 1695173298 ps
CPU time 145.68 seconds
Started Jan 03 02:09:38 PM PST 24
Finished Jan 03 02:12:11 PM PST 24
Peak memory 555040 kb
Host smart-f7cbd3b7-aab8-47f4-aace-d5c7fcbb3c19
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054305785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.3054305785
Directory /workspace/34.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3384137466
Short name T260
Test name
Test status
Simulation time 10119804696 ps
CPU time 545.88 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:18:51 PM PST 24
Peak memory 556400 kb
Host smart-67558494-7b97-40e4-9fbe-4aadb687a828
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384137466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all
_with_rand_reset.3384137466
Directory /workspace/34.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2981566879
Short name T359
Test name
Test status
Simulation time 7334755915 ps
CPU time 376.18 seconds
Started Jan 03 02:09:16 PM PST 24
Finished Jan 03 02:15:35 PM PST 24
Peak memory 559052 kb
Host smart-3829d553-27c7-4291-a5e4-b4d569036631
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981566879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al
l_with_reset_error.2981566879
Directory /workspace/34.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.1699786070
Short name T506
Test name
Test status
Simulation time 449276987 ps
CPU time 20.04 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:10:03 PM PST 24
Peak memory 554152 kb
Host smart-559e64c7-c812-4bcf-b667-e37018b2dcaa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699786070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.1699786070
Directory /workspace/34.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_access_same_device.3020937525
Short name T654
Test name
Test status
Simulation time 1933223192 ps
CPU time 73.77 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:10:57 PM PST 24
Peak memory 553900 kb
Host smart-e91d3e12-5558-46ac-82be-036e1106a6ea
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020937525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device
.3020937525
Directory /workspace/35.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.2738378743
Short name T1218
Test name
Test status
Simulation time 116334154682 ps
CPU time 1902.13 seconds
Started Jan 03 02:09:56 PM PST 24
Finished Jan 03 02:41:45 PM PST 24
Peak memory 555352 kb
Host smart-f548e268-1826-4418-8ffb-15a4c90550b6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738378743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_
device_slow_rsp.2738378743
Directory /workspace/35.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3610153859
Short name T927
Test name
Test status
Simulation time 231392168 ps
CPU time 26.44 seconds
Started Jan 03 02:09:49 PM PST 24
Finished Jan 03 02:10:19 PM PST 24
Peak memory 554164 kb
Host smart-4bc2e04b-d93b-4144-bd93-fdd58839c81f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610153859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add
r.3610153859
Directory /workspace/35.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_error_random.1748299008
Short name T684
Test name
Test status
Simulation time 219825442 ps
CPU time 10.73 seconds
Started Jan 03 02:09:55 PM PST 24
Finished Jan 03 02:10:10 PM PST 24
Peak memory 551600 kb
Host smart-920856b4-b4f7-4e7e-8cb1-88308bc16b1f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748299008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1748299008
Directory /workspace/35.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random.3040934423
Short name T1363
Test name
Test status
Simulation time 286891351 ps
CPU time 29.14 seconds
Started Jan 03 02:09:38 PM PST 24
Finished Jan 03 02:10:15 PM PST 24
Peak memory 553880 kb
Host smart-3d3d11ca-e043-40fc-8933-a15bc25bdb90
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040934423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.3040934423
Directory /workspace/35.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.937499458
Short name T744
Test name
Test status
Simulation time 80594221056 ps
CPU time 947.49 seconds
Started Jan 03 02:09:57 PM PST 24
Finished Jan 03 02:25:50 PM PST 24
Peak memory 553980 kb
Host smart-3f3ad8ae-ff77-49c5-9dbe-646e90137ec8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937499458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.937499458
Directory /workspace/35.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.16054822
Short name T1847
Test name
Test status
Simulation time 26116418239 ps
CPU time 424.66 seconds
Started Jan 03 02:09:47 PM PST 24
Finished Jan 03 02:16:56 PM PST 24
Peak memory 553936 kb
Host smart-32c7872d-9040-42d6-908a-a26197b5572a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16054822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.16054822
Directory /workspace/35.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.2113873434
Short name T1896
Test name
Test status
Simulation time 202280003 ps
CPU time 20.99 seconds
Started Jan 03 02:09:40 PM PST 24
Finished Jan 03 02:10:08 PM PST 24
Peak memory 553848 kb
Host smart-33d20c66-217e-448b-a6ff-8d73548f15a2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113873434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del
ays.2113873434
Directory /workspace/35.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_same_source.2344626935
Short name T124
Test name
Test status
Simulation time 383458400 ps
CPU time 27.1 seconds
Started Jan 03 02:10:05 PM PST 24
Finished Jan 03 02:10:50 PM PST 24
Peak memory 553896 kb
Host smart-3a502b2a-24fc-49f1-9695-debaa88972f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344626935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2344626935
Directory /workspace/35.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke.857045458
Short name T1148
Test name
Test status
Simulation time 100811830 ps
CPU time 6.17 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:09:50 PM PST 24
Peak memory 551736 kb
Host smart-2ff710ed-8c51-493c-b8b3-bfa5b8d15af8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857045458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.857045458
Directory /workspace/35.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.338773806
Short name T1618
Test name
Test status
Simulation time 7288222797 ps
CPU time 74.17 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:10:59 PM PST 24
Peak memory 552080 kb
Host smart-8351fa1c-2b5b-4bcd-a190-eff86e284842
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338773806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.338773806
Directory /workspace/35.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.3239057422
Short name T1469
Test name
Test status
Simulation time 4201505522 ps
CPU time 72.07 seconds
Started Jan 03 02:09:52 PM PST 24
Finished Jan 03 02:11:07 PM PST 24
Peak memory 552068 kb
Host smart-d0a295ef-84cd-4e47-8d6e-6d80ab271953
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239057422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3239057422
Directory /workspace/35.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1818113070
Short name T1615
Test name
Test status
Simulation time 47440334 ps
CPU time 5.81 seconds
Started Jan 03 02:09:45 PM PST 24
Finished Jan 03 02:09:56 PM PST 24
Peak memory 551652 kb
Host smart-13abede5-0f76-4a3f-aca3-29586fb64fdf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818113070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay
s.1818113070
Directory /workspace/35.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all.4069580785
Short name T1509
Test name
Test status
Simulation time 8291187569 ps
CPU time 278.05 seconds
Started Jan 03 02:10:00 PM PST 24
Finished Jan 03 02:14:46 PM PST 24
Peak memory 555328 kb
Host smart-9c05d503-3dd9-4c8d-9f71-80d21474b4d3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069580785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.4069580785
Directory /workspace/35.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.1888802838
Short name T1194
Test name
Test status
Simulation time 10990713651 ps
CPU time 354.14 seconds
Started Jan 03 02:09:54 PM PST 24
Finished Jan 03 02:15:50 PM PST 24
Peak memory 556432 kb
Host smart-bc321a55-6731-4b0b-9510-7e286b6be641
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888802838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1888802838
Directory /workspace/35.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.2844696800
Short name T548
Test name
Test status
Simulation time 306106458 ps
CPU time 132.8 seconds
Started Jan 03 02:09:47 PM PST 24
Finished Jan 03 02:12:04 PM PST 24
Peak memory 555352 kb
Host smart-0efc88a6-eae8-4c1c-865c-ae0bdd4f8fe5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844696800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all
_with_rand_reset.2844696800
Directory /workspace/35.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1538109092
Short name T1340
Test name
Test status
Simulation time 1266370122 ps
CPU time 80.06 seconds
Started Jan 03 02:10:00 PM PST 24
Finished Jan 03 02:11:28 PM PST 24
Peak memory 555028 kb
Host smart-45d2cac8-8796-4de2-a704-8271f9c7fdab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538109092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al
l_with_reset_error.1538109092
Directory /workspace/35.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.4014237481
Short name T1179
Test name
Test status
Simulation time 489912374 ps
CPU time 21.8 seconds
Started Jan 03 02:09:40 PM PST 24
Finished Jan 03 02:10:09 PM PST 24
Peak memory 553908 kb
Host smart-3f64bbfd-a7b7-4bf0-b761-71355b1f699a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014237481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.4014237481
Directory /workspace/35.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_access_same_device.4136652632
Short name T433
Test name
Test status
Simulation time 1528297324 ps
CPU time 60.18 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:11:54 PM PST 24
Peak memory 554144 kb
Host smart-45883ab3-070f-4be1-a70a-c0a26a77af97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136652632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device
.4136652632
Directory /workspace/36.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3635833212
Short name T1266
Test name
Test status
Simulation time 26144648580 ps
CPU time 430.75 seconds
Started Jan 03 02:10:40 PM PST 24
Finished Jan 03 02:18:06 PM PST 24
Peak memory 555032 kb
Host smart-250baa3e-8c4b-4884-b437-d7f59f5c8085
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635833212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_
device_slow_rsp.3635833212
Directory /workspace/36.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.523537884
Short name T363
Test name
Test status
Simulation time 355250565 ps
CPU time 16.58 seconds
Started Jan 03 02:10:38 PM PST 24
Finished Jan 03 02:11:07 PM PST 24
Peak memory 553816 kb
Host smart-7ed5619a-2911-44e4-a7fe-5e93d54539de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523537884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr
.523537884
Directory /workspace/36.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random.2697778609
Short name T1190
Test name
Test status
Simulation time 1675663525 ps
CPU time 55.07 seconds
Started Jan 03 02:10:35 PM PST 24
Finished Jan 03 02:11:43 PM PST 24
Peak memory 554164 kb
Host smart-5dc21455-0896-4e3a-abe7-5dae83979790
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697778609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.2697778609
Directory /workspace/36.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.609865999
Short name T714
Test name
Test status
Simulation time 97854791779 ps
CPU time 1057.64 seconds
Started Jan 03 02:10:35 PM PST 24
Finished Jan 03 02:28:26 PM PST 24
Peak memory 553964 kb
Host smart-65d4fb9d-967b-49d7-bf09-ab079ed3ae6b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609865999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.609865999
Directory /workspace/36.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.2529157685
Short name T639
Test name
Test status
Simulation time 24421939571 ps
CPU time 409.95 seconds
Started Jan 03 02:10:05 PM PST 24
Finished Jan 03 02:17:13 PM PST 24
Peak memory 553940 kb
Host smart-b2886a86-71dc-48fb-ab73-87448941f93f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529157685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2529157685
Directory /workspace/36.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.1439001721
Short name T1420
Test name
Test status
Simulation time 311009206 ps
CPU time 29.64 seconds
Started Jan 03 02:10:46 PM PST 24
Finished Jan 03 02:11:38 PM PST 24
Peak memory 553872 kb
Host smart-f58da9b8-de5d-4535-9f7a-a71e7e368b5b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439001721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del
ays.1439001721
Directory /workspace/36.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_same_source.3540955108
Short name T1871
Test name
Test status
Simulation time 1938612357 ps
CPU time 57 seconds
Started Jan 03 02:09:28 PM PST 24
Finished Jan 03 02:10:33 PM PST 24
Peak memory 553880 kb
Host smart-14f9ee4e-997c-4027-a220-29f2f41a9f76
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540955108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3540955108
Directory /workspace/36.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke.823799212
Short name T865
Test name
Test status
Simulation time 234922659 ps
CPU time 8.83 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:09:58 PM PST 24
Peak memory 551824 kb
Host smart-7a7fc11a-0c5d-4d07-8932-53bfc99f3f87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823799212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.823799212
Directory /workspace/36.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.1354864351
Short name T1611
Test name
Test status
Simulation time 8400196707 ps
CPU time 84.52 seconds
Started Jan 03 02:10:12 PM PST 24
Finished Jan 03 02:11:53 PM PST 24
Peak memory 551948 kb
Host smart-cb476f5b-d1c0-4efe-a666-dc1dc1e9549e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354864351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1354864351
Directory /workspace/36.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.732386554
Short name T869
Test name
Test status
Simulation time 5020461266 ps
CPU time 80.86 seconds
Started Jan 03 02:09:50 PM PST 24
Finished Jan 03 02:11:14 PM PST 24
Peak memory 552152 kb
Host smart-7b6fb1fd-3074-4eba-91c9-fb0830a2d1eb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732386554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.732386554
Directory /workspace/36.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.655065913
Short name T884
Test name
Test status
Simulation time 43577042 ps
CPU time 5.69 seconds
Started Jan 03 02:10:03 PM PST 24
Finished Jan 03 02:10:26 PM PST 24
Peak memory 551700 kb
Host smart-4033922c-3341-4462-9dad-3a748af7865b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655065913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays
.655065913
Directory /workspace/36.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all.1977856485
Short name T121
Test name
Test status
Simulation time 8510738414 ps
CPU time 275.11 seconds
Started Jan 03 02:09:21 PM PST 24
Finished Jan 03 02:14:03 PM PST 24
Peak memory 555344 kb
Host smart-6b22aa83-3f9e-4fd6-a658-8db764595a87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977856485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1977856485
Directory /workspace/36.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.2632615004
Short name T1863
Test name
Test status
Simulation time 2845151216 ps
CPU time 226 seconds
Started Jan 03 02:09:35 PM PST 24
Finished Jan 03 02:13:28 PM PST 24
Peak memory 555112 kb
Host smart-b0f9883a-ebd3-45ff-8e09-fc4220af7d0a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632615004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2632615004
Directory /workspace/36.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.366632439
Short name T1616
Test name
Test status
Simulation time 438887521 ps
CPU time 235.74 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:13:40 PM PST 24
Peak memory 556388 kb
Host smart-879fbcbb-4ff3-4e95-a227-bdd9d991e844
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366632439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_
with_rand_reset.366632439
Directory /workspace/36.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1333482135
Short name T1700
Test name
Test status
Simulation time 1347113482 ps
CPU time 278.65 seconds
Started Jan 03 02:09:25 PM PST 24
Finished Jan 03 02:14:13 PM PST 24
Peak memory 559020 kb
Host smart-a4a4e320-fdd3-42fc-8613-6235391ff279
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333482135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al
l_with_reset_error.1333482135
Directory /workspace/36.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.4033224533
Short name T1107
Test name
Test status
Simulation time 992774648 ps
CPU time 39.98 seconds
Started Jan 03 02:09:20 PM PST 24
Finished Jan 03 02:10:08 PM PST 24
Peak memory 554168 kb
Host smart-9290a463-5a55-445a-8810-0f3425f4f1e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033224533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.4033224533
Directory /workspace/36.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_access_same_device.1911550033
Short name T314
Test name
Test status
Simulation time 583598572 ps
CPU time 45.23 seconds
Started Jan 03 02:09:19 PM PST 24
Finished Jan 03 02:10:09 PM PST 24
Peak memory 553888 kb
Host smart-06e3b747-d803-4477-b720-0c741e5b469c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911550033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device
.1911550033
Directory /workspace/37.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.658040425
Short name T317
Test name
Test status
Simulation time 128730235030 ps
CPU time 2114.47 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:44:59 PM PST 24
Peak memory 554224 kb
Host smart-dacc98a0-e008-41e0-9948-110535756052
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658040425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_d
evice_slow_rsp.658040425
Directory /workspace/37.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3928115534
Short name T1151
Test name
Test status
Simulation time 807053476 ps
CPU time 33.61 seconds
Started Jan 03 02:09:47 PM PST 24
Finished Jan 03 02:10:25 PM PST 24
Peak memory 554164 kb
Host smart-3bd05ea6-e858-45fd-8d16-9c9e33992b4f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928115534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add
r.3928115534
Directory /workspace/37.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_error_random.1971676094
Short name T991
Test name
Test status
Simulation time 96353709 ps
CPU time 9.39 seconds
Started Jan 03 02:09:45 PM PST 24
Finished Jan 03 02:10:00 PM PST 24
Peak memory 554108 kb
Host smart-1de70f1f-7195-420a-ab93-154dfa2380e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971676094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.1971676094
Directory /workspace/37.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random.546413485
Short name T374
Test name
Test status
Simulation time 37099464 ps
CPU time 5.95 seconds
Started Jan 03 02:09:20 PM PST 24
Finished Jan 03 02:09:34 PM PST 24
Peak memory 551796 kb
Host smart-6fec762b-e93d-4b9f-9773-3bab1e82ccfb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546413485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.546413485
Directory /workspace/37.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.3820052332
Short name T598
Test name
Test status
Simulation time 52611846434 ps
CPU time 614.25 seconds
Started Jan 03 02:09:43 PM PST 24
Finished Jan 03 02:20:04 PM PST 24
Peak memory 554160 kb
Host smart-9ac98eed-a9dd-4ffc-b8ff-81ff45b20555
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820052332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3820052332
Directory /workspace/37.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.3446647347
Short name T1554
Test name
Test status
Simulation time 8680363278 ps
CPU time 145.22 seconds
Started Jan 03 02:09:12 PM PST 24
Finished Jan 03 02:11:40 PM PST 24
Peak memory 553900 kb
Host smart-364c1d7d-e464-43d4-887a-39bee53fc7b4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446647347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3446647347
Directory /workspace/37.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.869988463
Short name T1764
Test name
Test status
Simulation time 355245993 ps
CPU time 32.27 seconds
Started Jan 03 02:09:33 PM PST 24
Finished Jan 03 02:10:13 PM PST 24
Peak memory 554116 kb
Host smart-19d1e172-77b1-48d8-aabd-dfb900cf326c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869988463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_dela
ys.869988463
Directory /workspace/37.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_same_source.3039065106
Short name T888
Test name
Test status
Simulation time 541867890 ps
CPU time 39.08 seconds
Started Jan 03 02:09:48 PM PST 24
Finished Jan 03 02:10:31 PM PST 24
Peak memory 553892 kb
Host smart-7e25da1e-6607-4c98-b964-72c9ba088ad7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039065106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3039065106
Directory /workspace/37.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke.707559623
Short name T476
Test name
Test status
Simulation time 203315752 ps
CPU time 8.55 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:09:57 PM PST 24
Peak memory 552176 kb
Host smart-6d8efd2c-2aee-452b-95a4-1b8a952ac737
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707559623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.707559623
Directory /workspace/37.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.3213881230
Short name T1177
Test name
Test status
Simulation time 6490517003 ps
CPU time 66.87 seconds
Started Jan 03 02:09:38 PM PST 24
Finished Jan 03 02:10:53 PM PST 24
Peak memory 551736 kb
Host smart-cf42c4f2-725a-42b0-9824-e53d9789e34c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213881230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3213881230
Directory /workspace/37.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.3483307363
Short name T1481
Test name
Test status
Simulation time 5000382821 ps
CPU time 78.5 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:11:07 PM PST 24
Peak memory 551832 kb
Host smart-00ac2863-cfd4-4031-b56f-41fe1451d5a4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483307363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.3483307363
Directory /workspace/37.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.205686398
Short name T790
Test name
Test status
Simulation time 57703556 ps
CPU time 7.18 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:09:52 PM PST 24
Peak memory 552044 kb
Host smart-366f86e6-f0ba-4e93-87b8-cf9dd8417044
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205686398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays
.205686398
Directory /workspace/37.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all.4083309057
Short name T1315
Test name
Test status
Simulation time 5892884922 ps
CPU time 206.84 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:13:16 PM PST 24
Peak memory 555100 kb
Host smart-97746e7b-5c1a-42da-9971-7cda536be2e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083309057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.4083309057
Directory /workspace/37.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.78211545
Short name T1165
Test name
Test status
Simulation time 5005613549 ps
CPU time 181.96 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:12:46 PM PST 24
Peak memory 554068 kb
Host smart-a316b0b5-d611-4f26-be9c-ced53bec4e30
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78211545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.78211545
Directory /workspace/37.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.2699274247
Short name T1680
Test name
Test status
Simulation time 157816342 ps
CPU time 42.9 seconds
Started Jan 03 02:09:45 PM PST 24
Finished Jan 03 02:10:33 PM PST 24
Peak memory 555048 kb
Host smart-36d85f1d-3e6d-4631-a93d-18fce8a94deb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699274247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all
_with_rand_reset.2699274247
Directory /workspace/37.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.3697692486
Short name T1552
Test name
Test status
Simulation time 293983093 ps
CPU time 97.24 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:11:22 PM PST 24
Peak memory 556364 kb
Host smart-09947f90-693b-4165-965b-5b2c1629d47a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697692486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al
l_with_reset_error.3697692486
Directory /workspace/37.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.601418151
Short name T703
Test name
Test status
Simulation time 323883579 ps
CPU time 39.02 seconds
Started Jan 03 02:09:11 PM PST 24
Finished Jan 03 02:09:53 PM PST 24
Peak memory 554184 kb
Host smart-6ac2ee20-5022-41e6-9a06-cc415a6516a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601418151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.601418151
Directory /workspace/37.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_access_same_device.3681370757
Short name T126
Test name
Test status
Simulation time 715729715 ps
CPU time 52.15 seconds
Started Jan 03 02:09:58 PM PST 24
Finished Jan 03 02:10:56 PM PST 24
Peak memory 555216 kb
Host smart-670a5a11-c04f-4e51-a18a-784592667647
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681370757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device
.3681370757
Directory /workspace/38.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2292450561
Short name T288
Test name
Test status
Simulation time 53105323276 ps
CPU time 827.66 seconds
Started Jan 03 02:09:59 PM PST 24
Finished Jan 03 02:23:54 PM PST 24
Peak memory 554252 kb
Host smart-79549801-ef6d-4e5d-ad84-03e91059f570
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292450561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_
device_slow_rsp.2292450561
Directory /workspace/38.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1489427215
Short name T376
Test name
Test status
Simulation time 619420554 ps
CPU time 24.75 seconds
Started Jan 03 02:10:30 PM PST 24
Finished Jan 03 02:11:08 PM PST 24
Peak memory 553824 kb
Host smart-d3800d95-2af8-47a6-bb0d-31d392a74a79
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489427215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add
r.1489427215
Directory /workspace/38.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_error_random.3749690965
Short name T1592
Test name
Test status
Simulation time 92007430 ps
CPU time 9.77 seconds
Started Jan 03 02:09:58 PM PST 24
Finished Jan 03 02:10:15 PM PST 24
Peak memory 554224 kb
Host smart-a30a8b2f-1df4-4242-941f-3d8a09dc2109
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749690965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3749690965
Directory /workspace/38.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random.2391328564
Short name T243
Test name
Test status
Simulation time 457483734 ps
CPU time 37.59 seconds
Started Jan 03 02:09:48 PM PST 24
Finished Jan 03 02:10:30 PM PST 24
Peak memory 554188 kb
Host smart-3236c770-f31d-4e47-8e7b-72502eeb4920
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391328564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.2391328564
Directory /workspace/38.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.3440225970
Short name T1115
Test name
Test status
Simulation time 5412962183 ps
CPU time 58.06 seconds
Started Jan 03 02:09:38 PM PST 24
Finished Jan 03 02:10:43 PM PST 24
Peak memory 551852 kb
Host smart-86aaacd3-13dd-49ba-9e53-88affcce2af6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440225970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3440225970
Directory /workspace/38.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.1421843484
Short name T893
Test name
Test status
Simulation time 41107850367 ps
CPU time 691.85 seconds
Started Jan 03 02:10:02 PM PST 24
Finished Jan 03 02:21:50 PM PST 24
Peak memory 553120 kb
Host smart-2329839d-3a10-4101-b8de-675c77c9d159
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421843484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1421843484
Directory /workspace/38.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.4018248889
Short name T1292
Test name
Test status
Simulation time 342366627 ps
CPU time 30.58 seconds
Started Jan 03 02:09:48 PM PST 24
Finished Jan 03 02:10:23 PM PST 24
Peak memory 554148 kb
Host smart-af0d066b-5c21-476d-b441-f2f689689427
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018248889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del
ays.4018248889
Directory /workspace/38.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_same_source.3360811291
Short name T1716
Test name
Test status
Simulation time 1149435480 ps
CPU time 34.32 seconds
Started Jan 03 02:09:54 PM PST 24
Finished Jan 03 02:10:31 PM PST 24
Peak memory 553880 kb
Host smart-18dabbaf-6fa2-4c2d-95bc-8f8f9b15d7fb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360811291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3360811291
Directory /workspace/38.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke.490987970
Short name T1389
Test name
Test status
Simulation time 37259533 ps
CPU time 5.69 seconds
Started Jan 03 02:09:46 PM PST 24
Finished Jan 03 02:09:57 PM PST 24
Peak memory 551804 kb
Host smart-520d795f-a827-4a66-add3-3474f76eae48
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490987970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.490987970
Directory /workspace/38.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.943547766
Short name T1434
Test name
Test status
Simulation time 7853567529 ps
CPU time 83.41 seconds
Started Jan 03 02:09:53 PM PST 24
Finished Jan 03 02:11:19 PM PST 24
Peak memory 551804 kb
Host smart-b58f7506-6519-45d2-815e-b35e7c656af2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943547766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.943547766
Directory /workspace/38.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.1186836048
Short name T594
Test name
Test status
Simulation time 3339622256 ps
CPU time 62.32 seconds
Started Jan 03 02:09:39 PM PST 24
Finished Jan 03 02:10:49 PM PST 24
Peak memory 551644 kb
Host smart-8c27456e-0ce9-448a-9131-d8a86a19e497
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186836048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1186836048
Directory /workspace/38.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2977383776
Short name T368
Test name
Test status
Simulation time 44452616 ps
CPU time 6.13 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:09:55 PM PST 24
Peak memory 551640 kb
Host smart-3e126c84-45fd-4c36-b7c0-46a4b397dc59
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977383776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay
s.2977383776
Directory /workspace/38.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all.3317237820
Short name T1788
Test name
Test status
Simulation time 11042309385 ps
CPU time 354.47 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:16:48 PM PST 24
Peak memory 555476 kb
Host smart-f9743526-647f-43d0-b231-600e69325a53
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317237820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3317237820
Directory /workspace/38.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.460002059
Short name T1395
Test name
Test status
Simulation time 5093510601 ps
CPU time 176.07 seconds
Started Jan 03 02:10:28 PM PST 24
Finished Jan 03 02:13:38 PM PST 24
Peak memory 555488 kb
Host smart-69a2f728-9525-4e94-b6af-777a84e9b41c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460002059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.460002059
Directory /workspace/38.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.3470854222
Short name T1805
Test name
Test status
Simulation time 4970641593 ps
CPU time 455.6 seconds
Started Jan 03 02:09:56 PM PST 24
Finished Jan 03 02:17:35 PM PST 24
Peak memory 558296 kb
Host smart-d7b6328c-191f-4c68-96d8-35cdcaeb4786
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470854222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all
_with_rand_reset.3470854222
Directory /workspace/38.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3749832544
Short name T343
Test name
Test status
Simulation time 367056129 ps
CPU time 110.31 seconds
Started Jan 03 02:10:35 PM PST 24
Finished Jan 03 02:12:38 PM PST 24
Peak memory 555908 kb
Host smart-3b6db0c5-2ac4-414b-945f-093e05e5406c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749832544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al
l_with_reset_error.3749832544
Directory /workspace/38.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.4005199372
Short name T197
Test name
Test status
Simulation time 276292103 ps
CPU time 13.1 seconds
Started Jan 03 02:09:57 PM PST 24
Finished Jan 03 02:10:17 PM PST 24
Peak memory 553876 kb
Host smart-5f25ca07-1fb9-491a-9faa-9073161a8069
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005199372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.4005199372
Directory /workspace/38.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_access_same_device.1074622081
Short name T322
Test name
Test status
Simulation time 2297606075 ps
CPU time 82.62 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:12:23 PM PST 24
Peak memory 554244 kb
Host smart-2a87de30-a956-47c8-bb8c-9d5fd89d300c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074622081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device
.1074622081
Directory /workspace/39.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.1121935719
Short name T1298
Test name
Test status
Simulation time 127833356986 ps
CPU time 1918.86 seconds
Started Jan 03 02:09:21 PM PST 24
Finished Jan 03 02:41:27 PM PST 24
Peak memory 555228 kb
Host smart-c4d666c0-e8d1-4ffb-aed3-de23b762443e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121935719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_
device_slow_rsp.1121935719
Directory /workspace/39.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3518426069
Short name T610
Test name
Test status
Simulation time 864695992 ps
CPU time 31.06 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:10:14 PM PST 24
Peak memory 554116 kb
Host smart-47e0009f-4ccf-4e38-8ad9-3112dc45024b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518426069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add
r.3518426069
Directory /workspace/39.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_error_random.1931577774
Short name T750
Test name
Test status
Simulation time 216753299 ps
CPU time 18.39 seconds
Started Jan 03 02:09:20 PM PST 24
Finished Jan 03 02:09:46 PM PST 24
Peak memory 554108 kb
Host smart-eef6838c-d026-4495-957d-a57a52668619
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931577774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1931577774
Directory /workspace/39.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random.2696635542
Short name T1868
Test name
Test status
Simulation time 411891884 ps
CPU time 33.14 seconds
Started Jan 03 02:10:11 PM PST 24
Finished Jan 03 02:11:02 PM PST 24
Peak memory 554200 kb
Host smart-5f9d4176-088f-4992-b18c-480ed7addbd1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696635542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.2696635542
Directory /workspace/39.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.1018478632
Short name T834
Test name
Test status
Simulation time 84870082949 ps
CPU time 815.22 seconds
Started Jan 03 02:10:36 PM PST 24
Finished Jan 03 02:24:25 PM PST 24
Peak memory 553992 kb
Host smart-f8bfa04f-04e1-48dd-ac51-07914be39703
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018478632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1018478632
Directory /workspace/39.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.1909007630
Short name T1320
Test name
Test status
Simulation time 36528202160 ps
CPU time 531.39 seconds
Started Jan 03 02:10:36 PM PST 24
Finished Jan 03 02:19:41 PM PST 24
Peak memory 554168 kb
Host smart-4d91280a-9c0f-4d29-a373-0c8fede08d74
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909007630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1909007630
Directory /workspace/39.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.3574720217
Short name T1650
Test name
Test status
Simulation time 402552339 ps
CPU time 35.8 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:11:35 PM PST 24
Peak memory 554188 kb
Host smart-536f3bde-313b-4cee-9503-f12dc248a59e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574720217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del
ays.3574720217
Directory /workspace/39.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_same_source.1909106463
Short name T623
Test name
Test status
Simulation time 588604034 ps
CPU time 39.24 seconds
Started Jan 03 02:09:38 PM PST 24
Finished Jan 03 02:10:25 PM PST 24
Peak memory 554176 kb
Host smart-7ce92dea-b325-4aee-a3eb-abc3d57a7c90
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909106463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1909106463
Directory /workspace/39.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke.1682396512
Short name T1612
Test name
Test status
Simulation time 149959128 ps
CPU time 7.41 seconds
Started Jan 03 02:10:22 PM PST 24
Finished Jan 03 02:10:44 PM PST 24
Peak memory 551776 kb
Host smart-41d6732e-cfac-45fc-b522-5b917ebf4e19
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682396512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1682396512
Directory /workspace/39.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.3256182714
Short name T1570
Test name
Test status
Simulation time 9026173523 ps
CPU time 101.47 seconds
Started Jan 03 02:10:15 PM PST 24
Finished Jan 03 02:12:11 PM PST 24
Peak memory 552124 kb
Host smart-1fdec556-fa91-457f-9247-2ccf37370c3f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256182714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3256182714
Directory /workspace/39.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.349974583
Short name T599
Test name
Test status
Simulation time 5735792862 ps
CPU time 97.88 seconds
Started Jan 03 02:10:02 PM PST 24
Finished Jan 03 02:11:57 PM PST 24
Peak memory 552056 kb
Host smart-410d88c6-1555-47ba-9b69-1c5a5f037661
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349974583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.349974583
Directory /workspace/39.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.2023960899
Short name T584
Test name
Test status
Simulation time 43384588 ps
CPU time 5.81 seconds
Started Jan 03 02:10:33 PM PST 24
Finished Jan 03 02:10:52 PM PST 24
Peak memory 551728 kb
Host smart-c1cec9f3-c48c-43b7-a450-8536f7c3ea04
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023960899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay
s.2023960899
Directory /workspace/39.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all.1794983593
Short name T170
Test name
Test status
Simulation time 15641956388 ps
CPU time 496.5 seconds
Started Jan 03 02:09:21 PM PST 24
Finished Jan 03 02:17:45 PM PST 24
Peak memory 557744 kb
Host smart-b1ecea03-f037-43d9-96c1-7719f6a6c7d3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794983593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1794983593
Directory /workspace/39.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.1141990651
Short name T1909
Test name
Test status
Simulation time 2071132228 ps
CPU time 71.23 seconds
Started Jan 03 02:09:15 PM PST 24
Finished Jan 03 02:10:29 PM PST 24
Peak memory 555228 kb
Host smart-49763b78-8fd5-4a9e-a0fc-cb87026abbb9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141990651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1141990651
Directory /workspace/39.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.250730553
Short name T1257
Test name
Test status
Simulation time 659984439 ps
CPU time 275.83 seconds
Started Jan 03 02:09:15 PM PST 24
Finished Jan 03 02:13:54 PM PST 24
Peak memory 557444 kb
Host smart-18c8b928-6fd8-4f62-8c4c-89554b0b33cd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250730553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_
with_rand_reset.250730553
Directory /workspace/39.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2664179228
Short name T810
Test name
Test status
Simulation time 351901104 ps
CPU time 67.91 seconds
Started Jan 03 02:09:21 PM PST 24
Finished Jan 03 02:10:36 PM PST 24
Peak memory 555300 kb
Host smart-9dec799c-fa08-44df-b308-1740865088e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664179228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al
l_with_reset_error.2664179228
Directory /workspace/39.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.1324922546
Short name T1777
Test name
Test status
Simulation time 260350347 ps
CPU time 12.71 seconds
Started Jan 03 02:09:23 PM PST 24
Finished Jan 03 02:09:45 PM PST 24
Peak memory 554184 kb
Host smart-e348319a-dcc4-4758-ab34-2c65c9952fe8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324922546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1324922546
Directory /workspace/39.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.2923415130
Short name T32
Test name
Test status
Simulation time 41006086237 ps
CPU time 5878.43 seconds
Started Jan 03 02:08:43 PM PST 24
Finished Jan 03 03:46:49 PM PST 24
Peak memory 580004 kb
Host smart-5fb29fc7-40cf-4601-ac54-9dd31ea839c2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923415130 -assert nopostproc +UVM_TESTNAME=chip_
base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.chip_csr_aliasing.2923415130
Directory /workspace/4.chip_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.100652711
Short name T40
Test name
Test status
Simulation time 9918004872 ps
CPU time 751.92 seconds
Started Jan 03 02:08:26 PM PST 24
Finished Jan 03 02:21:07 PM PST 24
Peak memory 579184 kb
Host smart-43af94ed-fdf8-49fa-8335-ca682499dbdf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100652711 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.100652711
Directory /workspace/4.chip_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.3907108206
Short name T80
Test name
Test status
Simulation time 8421373646 ps
CPU time 370.26 seconds
Started Jan 03 02:07:17 PM PST 24
Finished Jan 03 02:13:33 PM PST 24
Peak memory 638460 kb
Host smart-44d9259d-4192-47e1-9a7c-acae5849e5b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907108206 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.3907108206
Directory /workspace/4.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.chip_csr_rw.2982415561
Short name T55
Test name
Test status
Simulation time 5202506759 ps
CPU time 502.8 seconds
Started Jan 03 02:07:25 PM PST 24
Finished Jan 03 02:15:59 PM PST 24
Peak memory 580068 kb
Host smart-f1fb9272-1e96-4727-867e-c3214b0a7873
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982415561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.2982415561
Directory /workspace/4.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.2478877027
Short name T56
Test name
Test status
Simulation time 27577351787 ps
CPU time 2923.79 seconds
Started Jan 03 02:07:27 PM PST 24
Finished Jan 03 02:56:21 PM PST 24
Peak memory 580008 kb
Host smart-08608c6d-6c68-4e13-9e9c-864d8a6de286
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478877027 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.2478877027
Directory /workspace/4.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_access_same_device.114955781
Short name T1101
Test name
Test status
Simulation time 724656420 ps
CPU time 28.8 seconds
Started Jan 03 02:07:09 PM PST 24
Finished Jan 03 02:07:40 PM PST 24
Peak memory 554184 kb
Host smart-f647eeb3-a4e6-445c-94cd-eec5a00f29e6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114955781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.114955781
Directory /workspace/4.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2990752268
Short name T1090
Test name
Test status
Simulation time 77201833422 ps
CPU time 1119.35 seconds
Started Jan 03 02:07:25 PM PST 24
Finished Jan 03 02:26:15 PM PST 24
Peak memory 553940 kb
Host smart-3bc1d983-4fac-42b5-a88b-6eceef3b73e5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990752268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d
evice_slow_rsp.2990752268
Directory /workspace/4.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1564488710
Short name T604
Test name
Test status
Simulation time 483756084 ps
CPU time 19.06 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:08:05 PM PST 24
Peak memory 554212 kb
Host smart-d6929924-aaaf-4408-8196-defc857d93b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564488710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr
.1564488710
Directory /workspace/4.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_error_random.1736205930
Short name T397
Test name
Test status
Simulation time 351211549 ps
CPU time 27.73 seconds
Started Jan 03 02:07:32 PM PST 24
Finished Jan 03 02:08:09 PM PST 24
Peak memory 553808 kb
Host smart-59674079-dc1e-4128-96e0-448d8691a6b4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736205930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1736205930
Directory /workspace/4.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random.1448941413
Short name T417
Test name
Test status
Simulation time 295696227 ps
CPU time 24.3 seconds
Started Jan 03 02:07:34 PM PST 24
Finished Jan 03 02:08:08 PM PST 24
Peak memory 552972 kb
Host smart-e2a8448b-7c65-4800-8b30-c3c36bf20c0a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448941413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.1448941413
Directory /workspace/4.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.3815318760
Short name T129
Test name
Test status
Simulation time 57630371804 ps
CPU time 608.29 seconds
Started Jan 03 02:07:17 PM PST 24
Finished Jan 03 02:17:30 PM PST 24
Peak memory 553964 kb
Host smart-6fb29458-f246-41dc-824c-32781c0e60c6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815318760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3815318760
Directory /workspace/4.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.1895512379
Short name T523
Test name
Test status
Simulation time 13742844736 ps
CPU time 224.32 seconds
Started Jan 03 02:07:24 PM PST 24
Finished Jan 03 02:11:20 PM PST 24
Peak memory 553896 kb
Host smart-114c5830-2418-49f0-81df-4ac395fc47b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895512379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1895512379
Directory /workspace/4.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.2335164773
Short name T60
Test name
Test status
Simulation time 393415144 ps
CPU time 29.79 seconds
Started Jan 03 02:07:47 PM PST 24
Finished Jan 03 02:08:28 PM PST 24
Peak memory 554164 kb
Host smart-1e57704a-cd83-4d9a-b242-d16bed7acf81
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335164773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela
ys.2335164773
Directory /workspace/4.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_same_source.670311154
Short name T1213
Test name
Test status
Simulation time 524979722 ps
CPU time 38 seconds
Started Jan 03 02:06:56 PM PST 24
Finished Jan 03 02:07:35 PM PST 24
Peak memory 554140 kb
Host smart-40436bd6-0812-4115-9293-49e3b1142a94
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670311154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.670311154
Directory /workspace/4.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke.293106942
Short name T596
Test name
Test status
Simulation time 153943179 ps
CPU time 7.13 seconds
Started Jan 03 02:07:17 PM PST 24
Finished Jan 03 02:07:29 PM PST 24
Peak memory 551796 kb
Host smart-ff24f637-b2ec-41e2-b476-c27f4f4181c7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293106942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.293106942
Directory /workspace/4.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.257722192
Short name T449
Test name
Test status
Simulation time 7255754348 ps
CPU time 72.07 seconds
Started Jan 03 02:07:35 PM PST 24
Finished Jan 03 02:08:57 PM PST 24
Peak memory 551820 kb
Host smart-dfef52db-78f4-4d7a-9fcb-e8bcbb7b5d03
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257722192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.257722192
Directory /workspace/4.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2390247528
Short name T879
Test name
Test status
Simulation time 4791566946 ps
CPU time 78.54 seconds
Started Jan 03 02:07:26 PM PST 24
Finished Jan 03 02:08:55 PM PST 24
Peak memory 551852 kb
Host smart-9806b463-bd38-483c-b291-90e7be6623c7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390247528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2390247528
Directory /workspace/4.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.1582082288
Short name T442
Test name
Test status
Simulation time 48449497 ps
CPU time 6.11 seconds
Started Jan 03 02:07:27 PM PST 24
Finished Jan 03 02:07:43 PM PST 24
Peak memory 552060 kb
Host smart-acc286bd-45ad-40f8-847d-c4dbbb5ebccd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582082288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays
.1582082288
Directory /workspace/4.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all.232698242
Short name T196
Test name
Test status
Simulation time 15039630880 ps
CPU time 509.15 seconds
Started Jan 03 02:07:31 PM PST 24
Finished Jan 03 02:16:09 PM PST 24
Peak memory 556664 kb
Host smart-951b79a5-0c76-4216-91d0-0b04b51135d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232698242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.232698242
Directory /workspace/4.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.1663188070
Short name T1730
Test name
Test status
Simulation time 5701859899 ps
CPU time 201.2 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:11:08 PM PST 24
Peak memory 555104 kb
Host smart-775ad865-8406-4a18-960d-9d3a20e41325
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663188070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1663188070
Directory /workspace/4.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3815481704
Short name T1508
Test name
Test status
Simulation time 113079148 ps
CPU time 64.42 seconds
Started Jan 03 02:07:55 PM PST 24
Finished Jan 03 02:09:10 PM PST 24
Peak memory 554756 kb
Host smart-d61398cd-c1fd-4f5c-9735-a7c7564d159a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815481704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_
with_rand_reset.3815481704
Directory /workspace/4.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.188301097
Short name T1782
Test name
Test status
Simulation time 1023991181 ps
CPU time 77.53 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:09:05 PM PST 24
Peak memory 555008 kb
Host smart-27c5800d-8aea-45aa-90e8-adcb4495f971
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188301097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_
with_reset_error.188301097
Directory /workspace/4.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.1460726004
Short name T572
Test name
Test status
Simulation time 214384650 ps
CPU time 24.36 seconds
Started Jan 03 02:07:27 PM PST 24
Finished Jan 03 02:08:01 PM PST 24
Peak memory 553912 kb
Host smart-ca4d9a62-4c13-441e-a6de-2407747bc434
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460726004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1460726004
Directory /workspace/4.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_access_same_device.973861594
Short name T293
Test name
Test status
Simulation time 406015886 ps
CPU time 33.47 seconds
Started Jan 03 02:09:39 PM PST 24
Finished Jan 03 02:10:20 PM PST 24
Peak memory 553860 kb
Host smart-a6cfa372-45c1-4750-b227-fab8ad97bb66
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973861594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.
973861594
Directory /workspace/40.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1823351105
Short name T313
Test name
Test status
Simulation time 94658429280 ps
CPU time 1520.98 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:35:05 PM PST 24
Peak memory 554308 kb
Host smart-0a5a7656-ec4c-45bd-a286-42343d963d08
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823351105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_
device_slow_rsp.1823351105
Directory /workspace/40.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.3599729239
Short name T1547
Test name
Test status
Simulation time 482198760 ps
CPU time 19.08 seconds
Started Jan 03 02:09:47 PM PST 24
Finished Jan 03 02:10:10 PM PST 24
Peak memory 553872 kb
Host smart-88581d6f-8de8-4c37-83bc-f5c260633f39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599729239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add
r.3599729239
Directory /workspace/40.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_error_random.3532390123
Short name T1648
Test name
Test status
Simulation time 128454481 ps
CPU time 13.37 seconds
Started Jan 03 02:09:37 PM PST 24
Finished Jan 03 02:09:58 PM PST 24
Peak memory 553788 kb
Host smart-f6c3b87b-592b-49a9-b010-2c594ee51dde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532390123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3532390123
Directory /workspace/40.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random.3722048866
Short name T1873
Test name
Test status
Simulation time 1083733379 ps
CPU time 37.52 seconds
Started Jan 03 02:09:18 PM PST 24
Finished Jan 03 02:09:57 PM PST 24
Peak memory 554160 kb
Host smart-5f3752c7-55e3-40b6-8f7e-b2846ea60503
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722048866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.3722048866
Directory /workspace/40.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.3599466719
Short name T1330
Test name
Test status
Simulation time 11362863724 ps
CPU time 124.19 seconds
Started Jan 03 02:09:20 PM PST 24
Finished Jan 03 02:11:31 PM PST 24
Peak memory 551900 kb
Host smart-82ea41a2-9a79-4bed-a1b9-8a74bca55d96
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599466719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3599466719
Directory /workspace/40.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.2047340985
Short name T671
Test name
Test status
Simulation time 12973128566 ps
CPU time 230.81 seconds
Started Jan 03 02:09:15 PM PST 24
Finished Jan 03 02:13:09 PM PST 24
Peak memory 553932 kb
Host smart-5ac211a4-ace9-4e1e-90a5-67da152f1bfe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047340985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2047340985
Directory /workspace/40.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.419906425
Short name T1902
Test name
Test status
Simulation time 395007319 ps
CPU time 33.54 seconds
Started Jan 03 02:09:20 PM PST 24
Finished Jan 03 02:10:01 PM PST 24
Peak memory 554148 kb
Host smart-96f816d0-9dc8-4d5d-ae39-ab82de8e1276
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419906425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_dela
ys.419906425
Directory /workspace/40.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_same_source.1771899387
Short name T1878
Test name
Test status
Simulation time 204129331 ps
CPU time 8.78 seconds
Started Jan 03 02:09:41 PM PST 24
Finished Jan 03 02:09:57 PM PST 24
Peak memory 551836 kb
Host smart-8ed8ba82-d954-48ac-a324-cc3a5e3e636a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771899387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1771899387
Directory /workspace/40.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke.1946722076
Short name T1599
Test name
Test status
Simulation time 141340472 ps
CPU time 7.64 seconds
Started Jan 03 02:09:43 PM PST 24
Finished Jan 03 02:09:57 PM PST 24
Peak memory 552004 kb
Host smart-f6803ff0-bae1-417c-a0d8-0589b5c0d26e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946722076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.1946722076
Directory /workspace/40.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.1328212608
Short name T436
Test name
Test status
Simulation time 5679627245 ps
CPU time 58.63 seconds
Started Jan 03 02:09:19 PM PST 24
Finished Jan 03 02:10:22 PM PST 24
Peak memory 552128 kb
Host smart-84d6b245-2f51-4814-8d8f-6d69411a841c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328212608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1328212608
Directory /workspace/40.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.841440642
Short name T514
Test name
Test status
Simulation time 5521386688 ps
CPU time 90.42 seconds
Started Jan 03 02:09:44 PM PST 24
Finished Jan 03 02:11:20 PM PST 24
Peak memory 552156 kb
Host smart-689f1076-02e3-4c46-af27-24de827fe635
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841440642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.841440642
Directory /workspace/40.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3722829532
Short name T250
Test name
Test status
Simulation time 49714339 ps
CPU time 5.99 seconds
Started Jan 03 02:09:43 PM PST 24
Finished Jan 03 02:09:55 PM PST 24
Peak memory 552092 kb
Host smart-b49ce8af-8cff-4a96-910a-1aa114691f55
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722829532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay
s.3722829532
Directory /workspace/40.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all.1930207993
Short name T1706
Test name
Test status
Simulation time 2829305879 ps
CPU time 106.52 seconds
Started Jan 03 02:09:54 PM PST 24
Finished Jan 03 02:11:43 PM PST 24
Peak memory 555076 kb
Host smart-137118e0-134c-4f16-a472-cdc666e459e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930207993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1930207993
Directory /workspace/40.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.112097652
Short name T608
Test name
Test status
Simulation time 2913620871 ps
CPU time 180.07 seconds
Started Jan 03 02:09:42 PM PST 24
Finished Jan 03 02:12:49 PM PST 24
Peak memory 555108 kb
Host smart-d4cf3ea1-68b5-44cd-ac04-464b5636f8c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112097652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.112097652
Directory /workspace/40.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3635199833
Short name T447
Test name
Test status
Simulation time 74344241 ps
CPU time 26.09 seconds
Started Jan 03 02:09:45 PM PST 24
Finished Jan 03 02:10:17 PM PST 24
Peak memory 553020 kb
Host smart-42047c9e-8e13-47b3-ba17-985e4d9f5a3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635199833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all
_with_rand_reset.3635199833
Directory /workspace/40.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3209736626
Short name T1373
Test name
Test status
Simulation time 150919565 ps
CPU time 37.95 seconds
Started Jan 03 02:09:38 PM PST 24
Finished Jan 03 02:10:24 PM PST 24
Peak memory 555064 kb
Host smart-34a3e477-00c0-4b32-a644-f2c787cf953b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209736626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al
l_with_reset_error.3209736626
Directory /workspace/40.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.2818021374
Short name T766
Test name
Test status
Simulation time 39240567 ps
CPU time 6.84 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:09:50 PM PST 24
Peak memory 551856 kb
Host smart-7a581af6-eca6-4908-8478-5cacb303c491
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818021374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2818021374
Directory /workspace/40.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_access_same_device.1447220344
Short name T885
Test name
Test status
Simulation time 2695100361 ps
CPU time 99.34 seconds
Started Jan 03 02:10:10 PM PST 24
Finished Jan 03 02:12:08 PM PST 24
Peak memory 553956 kb
Host smart-9c1a1671-23cc-47dc-9fbc-96a4c60fda75
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447220344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device
.1447220344
Directory /workspace/41.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.2725319563
Short name T669
Test name
Test status
Simulation time 287401333 ps
CPU time 33.17 seconds
Started Jan 03 02:09:52 PM PST 24
Finished Jan 03 02:10:28 PM PST 24
Peak memory 554116 kb
Host smart-ce6be62b-4e1e-44aa-88b2-35af196f879f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725319563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add
r.2725319563
Directory /workspace/41.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_error_random.634832369
Short name T1415
Test name
Test status
Simulation time 1599035722 ps
CPU time 55.51 seconds
Started Jan 03 02:09:59 PM PST 24
Finished Jan 03 02:11:02 PM PST 24
Peak memory 553812 kb
Host smart-914abdbe-3e83-413a-b224-a3a7da8f79a0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634832369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.634832369
Directory /workspace/41.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random.594833683
Short name T1806
Test name
Test status
Simulation time 164515567 ps
CPU time 15.24 seconds
Started Jan 03 02:10:01 PM PST 24
Finished Jan 03 02:10:29 PM PST 24
Peak memory 553892 kb
Host smart-d1a0f83e-d2cd-4a60-959c-0d1eb91a16a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594833683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.594833683
Directory /workspace/41.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.1765605393
Short name T208
Test name
Test status
Simulation time 90458831964 ps
CPU time 877.64 seconds
Started Jan 03 02:09:59 PM PST 24
Finished Jan 03 02:24:44 PM PST 24
Peak memory 554260 kb
Host smart-a760518d-a5cd-4b63-a2af-3d3fe943973a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765605393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1765605393
Directory /workspace/41.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.3382847439
Short name T555
Test name
Test status
Simulation time 52660456533 ps
CPU time 836.01 seconds
Started Jan 03 02:10:10 PM PST 24
Finished Jan 03 02:24:24 PM PST 24
Peak memory 553968 kb
Host smart-a268c88c-5e30-4369-8939-fc4e0cd9524c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382847439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3382847439
Directory /workspace/41.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.1825296313
Short name T1452
Test name
Test status
Simulation time 311119671 ps
CPU time 27.28 seconds
Started Jan 03 02:09:58 PM PST 24
Finished Jan 03 02:10:33 PM PST 24
Peak memory 554168 kb
Host smart-c5e8bf16-9d58-45b3-a518-6eefd69021b7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825296313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del
ays.1825296313
Directory /workspace/41.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_same_source.514149251
Short name T923
Test name
Test status
Simulation time 562078176 ps
CPU time 36.99 seconds
Started Jan 03 02:10:01 PM PST 24
Finished Jan 03 02:10:50 PM PST 24
Peak memory 554172 kb
Host smart-871b1618-0809-4249-9b96-02bc9e4eb495
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514149251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.514149251
Directory /workspace/41.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke.3916778712
Short name T1801
Test name
Test status
Simulation time 52282106 ps
CPU time 5.97 seconds
Started Jan 03 02:09:49 PM PST 24
Finished Jan 03 02:09:59 PM PST 24
Peak memory 551692 kb
Host smart-e86b19b7-651d-44f3-b0da-d0a3d82b72ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916778712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3916778712
Directory /workspace/41.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.3844195569
Short name T615
Test name
Test status
Simulation time 9371652112 ps
CPU time 101.2 seconds
Started Jan 03 02:09:38 PM PST 24
Finished Jan 03 02:11:27 PM PST 24
Peak memory 552104 kb
Host smart-1c0a767f-17dd-48dd-a59a-fbc298192f47
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844195569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3844195569
Directory /workspace/41.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.658701022
Short name T1270
Test name
Test status
Simulation time 4752890513 ps
CPU time 81.42 seconds
Started Jan 03 02:09:46 PM PST 24
Finished Jan 03 02:11:12 PM PST 24
Peak memory 551768 kb
Host smart-91bff1b6-7c60-40cf-b95e-e9da072205fe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658701022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.658701022
Directory /workspace/41.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.505118699
Short name T1860
Test name
Test status
Simulation time 38032193 ps
CPU time 5.31 seconds
Started Jan 03 02:09:36 PM PST 24
Finished Jan 03 02:09:49 PM PST 24
Peak memory 551768 kb
Host smart-54eaa756-9db0-493d-80e2-c762199d9a5e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505118699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays
.505118699
Directory /workspace/41.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all.3320543027
Short name T1813
Test name
Test status
Simulation time 12224439093 ps
CPU time 364.87 seconds
Started Jan 03 02:10:01 PM PST 24
Finished Jan 03 02:16:18 PM PST 24
Peak memory 555948 kb
Host smart-e3eee648-d43c-48c8-971f-5055378bb64f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320543027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3320543027
Directory /workspace/41.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.707863787
Short name T1353
Test name
Test status
Simulation time 2378891705 ps
CPU time 181.7 seconds
Started Jan 03 02:09:55 PM PST 24
Finished Jan 03 02:13:00 PM PST 24
Peak memory 555092 kb
Host smart-4e3b5315-7b52-4c07-ab7a-b4921c25a29b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707863787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.707863787
Directory /workspace/41.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.2934618387
Short name T1308
Test name
Test status
Simulation time 257486335 ps
CPU time 126.53 seconds
Started Jan 03 02:10:00 PM PST 24
Finished Jan 03 02:12:15 PM PST 24
Peak memory 556504 kb
Host smart-fb43c6ee-e2c6-40a6-91b5-8be385c5ddaf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934618387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all
_with_rand_reset.2934618387
Directory /workspace/41.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2173441241
Short name T785
Test name
Test status
Simulation time 1041204372 ps
CPU time 325.02 seconds
Started Jan 03 02:09:58 PM PST 24
Finished Jan 03 02:15:30 PM PST 24
Peak memory 567272 kb
Host smart-eabb56c9-621a-4691-841a-338ecfb1973c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173441241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al
l_with_reset_error.2173441241
Directory /workspace/41.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.1010279987
Short name T228
Test name
Test status
Simulation time 176918751 ps
CPU time 23.28 seconds
Started Jan 03 02:10:12 PM PST 24
Finished Jan 03 02:10:52 PM PST 24
Peak memory 554192 kb
Host smart-dc73edcd-26e3-4cbd-b37a-ed09a3ffd212
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010279987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1010279987
Directory /workspace/41.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_access_same_device.261165140
Short name T1137
Test name
Test status
Simulation time 721149012 ps
CPU time 62.65 seconds
Started Jan 03 02:10:01 PM PST 24
Finished Jan 03 02:11:17 PM PST 24
Peak memory 553848 kb
Host smart-3b5da211-3638-4b24-92e1-8efa30f95588
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261165140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.
261165140
Directory /workspace/42.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.4292269038
Short name T7
Test name
Test status
Simulation time 11068306555 ps
CPU time 189.85 seconds
Started Jan 03 02:10:01 PM PST 24
Finished Jan 03 02:13:23 PM PST 24
Peak memory 552120 kb
Host smart-a1ec2990-8a9a-49e1-82af-824f269f795e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292269038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_
device_slow_rsp.4292269038
Directory /workspace/42.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.3459056589
Short name T387
Test name
Test status
Simulation time 169597674 ps
CPU time 17.63 seconds
Started Jan 03 02:10:46 PM PST 24
Finished Jan 03 02:11:27 PM PST 24
Peak memory 554160 kb
Host smart-c129b5f0-5a20-47b9-afba-8f3e907379d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459056589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add
r.3459056589
Directory /workspace/42.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_error_random.2627941487
Short name T1534
Test name
Test status
Simulation time 32400798 ps
CPU time 6.02 seconds
Started Jan 03 02:10:00 PM PST 24
Finished Jan 03 02:10:14 PM PST 24
Peak memory 551664 kb
Host smart-02b884a4-ff60-46dc-b6d8-b02464bbc9f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627941487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2627941487
Directory /workspace/42.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random.2793147190
Short name T948
Test name
Test status
Simulation time 318046222 ps
CPU time 29.05 seconds
Started Jan 03 02:10:17 PM PST 24
Finished Jan 03 02:11:00 PM PST 24
Peak memory 553888 kb
Host smart-2809b7e4-050b-4932-ae5f-1fd63bd415f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793147190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.2793147190
Directory /workspace/42.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.331592456
Short name T184
Test name
Test status
Simulation time 61132143824 ps
CPU time 637.81 seconds
Started Jan 03 02:10:04 PM PST 24
Finished Jan 03 02:21:01 PM PST 24
Peak memory 553888 kb
Host smart-cd8a6460-60b6-44d6-ac49-4a96919e0a2e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331592456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.331592456
Directory /workspace/42.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.579347873
Short name T1247
Test name
Test status
Simulation time 51688551251 ps
CPU time 839.99 seconds
Started Jan 03 02:09:56 PM PST 24
Finished Jan 03 02:24:01 PM PST 24
Peak memory 554208 kb
Host smart-388b3afd-d2aa-4935-9c9b-67520b2574cb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579347873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.579347873
Directory /workspace/42.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.3318280110
Short name T1191
Test name
Test status
Simulation time 624140192 ps
CPU time 50.94 seconds
Started Jan 03 02:10:17 PM PST 24
Finished Jan 03 02:11:22 PM PST 24
Peak memory 553936 kb
Host smart-c0c89bf1-6d1e-4a49-9635-215ab4caa4cb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318280110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del
ays.3318280110
Directory /workspace/42.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_same_source.2137779388
Short name T571
Test name
Test status
Simulation time 145735600 ps
CPU time 12.94 seconds
Started Jan 03 02:10:29 PM PST 24
Finished Jan 03 02:10:56 PM PST 24
Peak memory 554092 kb
Host smart-dcb8e432-9c4f-458e-93e0-1b58f3464761
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137779388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2137779388
Directory /workspace/42.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke.4004288609
Short name T630
Test name
Test status
Simulation time 179260438 ps
CPU time 7.91 seconds
Started Jan 03 02:10:33 PM PST 24
Finished Jan 03 02:10:54 PM PST 24
Peak memory 552100 kb
Host smart-e77966cc-879a-4272-965b-63a54d6d01e6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004288609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.4004288609
Directory /workspace/42.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.3093027740
Short name T1464
Test name
Test status
Simulation time 8296594315 ps
CPU time 88.19 seconds
Started Jan 03 02:10:23 PM PST 24
Finished Jan 03 02:12:07 PM PST 24
Peak memory 551788 kb
Host smart-7f3f448e-b080-48b5-8a2a-9d931e742abf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093027740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3093027740
Directory /workspace/42.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.193047414
Short name T446
Test name
Test status
Simulation time 5103874641 ps
CPU time 85.4 seconds
Started Jan 03 02:10:04 PM PST 24
Finished Jan 03 02:11:47 PM PST 24
Peak memory 552084 kb
Host smart-a38a9026-2a14-4ad6-86b8-c93a441f52fe
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193047414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.193047414
Directory /workspace/42.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.3394840670
Short name T539
Test name
Test status
Simulation time 41836406 ps
CPU time 5.76 seconds
Started Jan 03 02:10:35 PM PST 24
Finished Jan 03 02:10:54 PM PST 24
Peak memory 551656 kb
Host smart-76076618-53d1-4abf-bb28-5b8490705fea
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394840670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay
s.3394840670
Directory /workspace/42.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all.2712833191
Short name T1226
Test name
Test status
Simulation time 2797838807 ps
CPU time 215.47 seconds
Started Jan 03 02:10:02 PM PST 24
Finished Jan 03 02:13:53 PM PST 24
Peak memory 555136 kb
Host smart-12d5b9ab-5fca-4920-a7d8-15b115c7f8ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712833191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2712833191
Directory /workspace/42.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.4238237071
Short name T1487
Test name
Test status
Simulation time 14985584600 ps
CPU time 494.02 seconds
Started Jan 03 02:09:56 PM PST 24
Finished Jan 03 02:18:15 PM PST 24
Peak memory 555596 kb
Host smart-a163c1c0-7c96-4249-a5d7-c448256922e4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238237071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.4238237071
Directory /workspace/42.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2927140369
Short name T152
Test name
Test status
Simulation time 12441136810 ps
CPU time 553.9 seconds
Started Jan 03 02:09:58 PM PST 24
Finished Jan 03 02:19:19 PM PST 24
Peak memory 556476 kb
Host smart-535d7021-b5e2-40b4-a13b-035f272299c2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927140369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all
_with_rand_reset.2927140369
Directory /workspace/42.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3674412654
Short name T1321
Test name
Test status
Simulation time 1157475820 ps
CPU time 174.61 seconds
Started Jan 03 02:10:14 PM PST 24
Finished Jan 03 02:13:24 PM PST 24
Peak memory 557720 kb
Host smart-7f82cff6-b1be-4209-8d86-7b8b462d4631
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674412654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al
l_with_reset_error.3674412654
Directory /workspace/42.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.3897923553
Short name T1607
Test name
Test status
Simulation time 214446937 ps
CPU time 27.33 seconds
Started Jan 03 02:10:00 PM PST 24
Finished Jan 03 02:10:35 PM PST 24
Peak memory 553084 kb
Host smart-593c4cd6-2ac0-4048-8cc9-5cffa4f93035
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897923553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3897923553
Directory /workspace/42.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_access_same_device.574604164
Short name T329
Test name
Test status
Simulation time 711878411 ps
CPU time 44.95 seconds
Started Jan 03 02:10:46 PM PST 24
Finished Jan 03 02:11:53 PM PST 24
Peak memory 554204 kb
Host smart-dfd61fa7-bf0e-4f3c-9b8f-4464ec51873d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574604164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.
574604164
Directory /workspace/43.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.2569991823
Short name T1818
Test name
Test status
Simulation time 136263556150 ps
CPU time 2153.11 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:46:47 PM PST 24
Peak memory 555208 kb
Host smart-3fdfcb87-b9c6-4b8a-b52a-555349a09c33
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569991823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_
device_slow_rsp.2569991823
Directory /workspace/43.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.539850951
Short name T1061
Test name
Test status
Simulation time 1365423534 ps
CPU time 54.01 seconds
Started Jan 03 02:10:47 PM PST 24
Finished Jan 03 02:12:03 PM PST 24
Peak memory 553828 kb
Host smart-8939c5ac-31d6-479e-9c36-62d84e472c75
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539850951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr
.539850951
Directory /workspace/43.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_error_random.1501208348
Short name T1550
Test name
Test status
Simulation time 516360862 ps
CPU time 20.43 seconds
Started Jan 03 02:10:36 PM PST 24
Finished Jan 03 02:11:09 PM PST 24
Peak memory 554108 kb
Host smart-118d84e3-32b7-41aa-b2eb-a2ea2119670e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501208348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1501208348
Directory /workspace/43.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random.3445416913
Short name T807
Test name
Test status
Simulation time 189084255 ps
CPU time 16.97 seconds
Started Jan 03 02:10:35 PM PST 24
Finished Jan 03 02:11:04 PM PST 24
Peak memory 554244 kb
Host smart-9e48a34f-7ee4-4859-b489-56ffd84145a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445416913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.3445416913
Directory /workspace/43.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.1933981991
Short name T1861
Test name
Test status
Simulation time 71560023097 ps
CPU time 694.87 seconds
Started Jan 03 02:10:44 PM PST 24
Finished Jan 03 02:22:40 PM PST 24
Peak memory 553928 kb
Host smart-02fc257e-2d4c-4773-8ee8-3aa53a5b5022
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933981991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1933981991
Directory /workspace/43.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.3601738124
Short name T1812
Test name
Test status
Simulation time 25631315062 ps
CPU time 423.6 seconds
Started Jan 03 02:09:59 PM PST 24
Finished Jan 03 02:17:09 PM PST 24
Peak memory 553924 kb
Host smart-2f05ca1c-2519-4092-b943-0fad004cda89
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601738124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3601738124
Directory /workspace/43.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.3198347205
Short name T6
Test name
Test status
Simulation time 385243567 ps
CPU time 31.22 seconds
Started Jan 03 02:10:34 PM PST 24
Finished Jan 03 02:11:17 PM PST 24
Peak memory 554116 kb
Host smart-0de5b2a9-18c5-43ce-92d2-009f73b4c6bf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198347205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del
ays.3198347205
Directory /workspace/43.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_same_source.1202487553
Short name T242
Test name
Test status
Simulation time 503091391 ps
CPU time 35.32 seconds
Started Jan 03 02:10:37 PM PST 24
Finished Jan 03 02:11:26 PM PST 24
Peak memory 554144 kb
Host smart-4b9a0626-a758-4e1a-8247-2ba53c9b63e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202487553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1202487553
Directory /workspace/43.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke.3144201466
Short name T1060
Test name
Test status
Simulation time 192384192 ps
CPU time 8.55 seconds
Started Jan 03 02:10:17 PM PST 24
Finished Jan 03 02:10:39 PM PST 24
Peak memory 552128 kb
Host smart-6e54ccdc-1bd4-49a1-b1d6-5ac21db649c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144201466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3144201466
Directory /workspace/43.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.1805542109
Short name T1246
Test name
Test status
Simulation time 8905351141 ps
CPU time 92.69 seconds
Started Jan 03 02:10:41 PM PST 24
Finished Jan 03 02:12:31 PM PST 24
Peak memory 552140 kb
Host smart-de1d183e-56bb-4f81-9345-b195ce62a8c1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805542109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1805542109
Directory /workspace/43.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3527063312
Short name T1893
Test name
Test status
Simulation time 5250270918 ps
CPU time 94.05 seconds
Started Jan 03 02:10:33 PM PST 24
Finished Jan 03 02:12:20 PM PST 24
Peak memory 552108 kb
Host smart-cde898af-bddb-42fd-a4c9-d2a470e9bedd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527063312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3527063312
Directory /workspace/43.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1943638028
Short name T591
Test name
Test status
Simulation time 44357292 ps
CPU time 5.74 seconds
Started Jan 03 02:10:22 PM PST 24
Finished Jan 03 02:10:42 PM PST 24
Peak memory 552048 kb
Host smart-25300d2f-e79d-4972-b5e2-ae913c1bd598
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943638028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay
s.1943638028
Directory /workspace/43.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all.1403852509
Short name T1077
Test name
Test status
Simulation time 14139645634 ps
CPU time 432.97 seconds
Started Jan 03 02:10:46 PM PST 24
Finished Jan 03 02:18:21 PM PST 24
Peak memory 555672 kb
Host smart-e4dcb1de-e1c3-4040-9b3d-58380b1143a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403852509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1403852509
Directory /workspace/43.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.1748795351
Short name T1484
Test name
Test status
Simulation time 2563323845 ps
CPU time 214.98 seconds
Started Jan 03 02:10:50 PM PST 24
Finished Jan 03 02:14:48 PM PST 24
Peak memory 555384 kb
Host smart-46f1c967-397e-4b81-bdbd-1a3eca8f38e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748795351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1748795351
Directory /workspace/43.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2477318234
Short name T414
Test name
Test status
Simulation time 32997465 ps
CPU time 41.83 seconds
Started Jan 03 02:10:41 PM PST 24
Finished Jan 03 02:11:40 PM PST 24
Peak memory 555348 kb
Host smart-ea4b43e8-ac5a-47aa-a293-3a50b20dd4ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477318234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all
_with_rand_reset.2477318234
Directory /workspace/43.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3278676222
Short name T525
Test name
Test status
Simulation time 252854006 ps
CPU time 57.61 seconds
Started Jan 03 02:10:48 PM PST 24
Finished Jan 03 02:12:08 PM PST 24
Peak memory 555044 kb
Host smart-35dcabc9-8b42-4f76-bd75-a4a4fb887015
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278676222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al
l_with_reset_error.3278676222
Directory /workspace/43.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.524667639
Short name T435
Test name
Test status
Simulation time 429949463 ps
CPU time 20.05 seconds
Started Jan 03 02:10:36 PM PST 24
Finished Jan 03 02:11:09 PM PST 24
Peak memory 553068 kb
Host smart-54cfea8b-b94b-44c8-8c7a-c8cbef3a96ce
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524667639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.524667639
Directory /workspace/43.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_access_same_device.2009277414
Short name T970
Test name
Test status
Simulation time 794656954 ps
CPU time 50.45 seconds
Started Jan 03 02:10:40 PM PST 24
Finished Jan 03 02:11:47 PM PST 24
Peak memory 554128 kb
Host smart-1bf344e2-193f-4f46-b9fb-0817b62eb538
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009277414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device
.2009277414
Directory /workspace/44.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1049314789
Short name T1098
Test name
Test status
Simulation time 732404866 ps
CPU time 29.12 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:11:53 PM PST 24
Peak memory 554152 kb
Host smart-3e850142-d90a-4f96-bedb-44e1d316a2bc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049314789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add
r.1049314789
Directory /workspace/44.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_error_random.4097964432
Short name T1742
Test name
Test status
Simulation time 1842699808 ps
CPU time 59.82 seconds
Started Jan 03 02:10:52 PM PST 24
Finished Jan 03 02:12:15 PM PST 24
Peak memory 553836 kb
Host smart-7b4b5d4a-a355-4f18-ad2e-64883ec18edb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097964432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.4097964432
Directory /workspace/44.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random.3375117557
Short name T70
Test name
Test status
Simulation time 467035748 ps
CPU time 44.15 seconds
Started Jan 03 02:10:51 PM PST 24
Finished Jan 03 02:11:58 PM PST 24
Peak memory 554220 kb
Host smart-32dd3913-dbb1-41b5-bb05-775f1dd3c87e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375117557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.3375117557
Directory /workspace/44.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.4013749887
Short name T219
Test name
Test status
Simulation time 46154107529 ps
CPU time 491.81 seconds
Started Jan 03 02:10:53 PM PST 24
Finished Jan 03 02:19:27 PM PST 24
Peak memory 553984 kb
Host smart-8889d7b8-1f52-4745-885a-5d576099ee7b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013749887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.4013749887
Directory /workspace/44.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.3375961107
Short name T1435
Test name
Test status
Simulation time 5871228254 ps
CPU time 100.73 seconds
Started Jan 03 02:10:52 PM PST 24
Finished Jan 03 02:12:55 PM PST 24
Peak memory 551760 kb
Host smart-e10ebb92-a9c4-419e-9aed-c2efae38f99c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375961107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3375961107
Directory /workspace/44.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.1165586059
Short name T1850
Test name
Test status
Simulation time 409936097 ps
CPU time 35.84 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:11:54 PM PST 24
Peak memory 553980 kb
Host smart-09bee3e0-b86c-4d33-926b-4ecb8f4e85eb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165586059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del
ays.1165586059
Directory /workspace/44.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_same_source.2811514766
Short name T264
Test name
Test status
Simulation time 475701221 ps
CPU time 16.01 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:11:35 PM PST 24
Peak memory 553876 kb
Host smart-c95ea6c3-528f-4c1a-9b90-12bd0e3c3d89
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811514766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2811514766
Directory /workspace/44.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke.1619705
Short name T1463
Test name
Test status
Simulation time 255367589 ps
CPU time 9.91 seconds
Started Jan 03 02:10:43 PM PST 24
Finished Jan 03 02:11:12 PM PST 24
Peak memory 551768 kb
Host smart-24e0229d-6731-4c4c-b2b1-df83339b2919
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1619705
Directory /workspace/44.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.1631949507
Short name T1571
Test name
Test status
Simulation time 8641488491 ps
CPU time 86.26 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:12:45 PM PST 24
Peak memory 552248 kb
Host smart-5101b3ee-2e21-4e12-87fc-bab9db4d4ee3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631949507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.1631949507
Directory /workspace/44.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.3692619677
Short name T1633
Test name
Test status
Simulation time 4876822110 ps
CPU time 79.45 seconds
Started Jan 03 02:10:51 PM PST 24
Finished Jan 03 02:12:33 PM PST 24
Peak memory 551872 kb
Host smart-d9ac91ea-4657-45f7-a539-49f16e78e2d4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692619677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.3692619677
Directory /workspace/44.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1230228517
Short name T1425
Test name
Test status
Simulation time 38652421 ps
CPU time 5.6 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:11:30 PM PST 24
Peak memory 552020 kb
Host smart-7a4f8952-2695-4022-948d-ba3db4e2546f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230228517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay
s.1230228517
Directory /workspace/44.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all.4178503808
Short name T173
Test name
Test status
Simulation time 2428269554 ps
CPU time 80.06 seconds
Started Jan 03 02:11:03 PM PST 24
Finished Jan 03 02:12:45 PM PST 24
Peak memory 554384 kb
Host smart-bb563302-d61d-4526-b14d-69977dfad3f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178503808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.4178503808
Directory /workspace/44.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2645856361
Short name T756
Test name
Test status
Simulation time 2693468732 ps
CPU time 156.73 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:14:00 PM PST 24
Peak memory 555372 kb
Host smart-1d837896-5307-4051-ae02-018f867c6e0d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645856361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2645856361
Directory /workspace/44.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.74637896
Short name T1238
Test name
Test status
Simulation time 7027970701 ps
CPU time 293.79 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:16:18 PM PST 24
Peak memory 555532 kb
Host smart-73e46ef9-b322-4003-9728-104bf978fa4e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74637896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_w
ith_rand_reset.74637896
Directory /workspace/44.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3749454831
Short name T1591
Test name
Test status
Simulation time 4350647206 ps
CPU time 279.83 seconds
Started Jan 03 02:10:28 PM PST 24
Finished Jan 03 02:15:23 PM PST 24
Peak memory 559080 kb
Host smart-6e2fd07b-caa3-431b-9785-25bd88d3db9d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749454831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al
l_with_reset_error.3749454831
Directory /workspace/44.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.2491858400
Short name T1140
Test name
Test status
Simulation time 198162587 ps
CPU time 23.46 seconds
Started Jan 03 02:10:59 PM PST 24
Finished Jan 03 02:11:44 PM PST 24
Peak memory 553956 kb
Host smart-3137892b-0b1c-44ff-a8a9-8b58c3cf83f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491858400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2491858400
Directory /workspace/44.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_access_same_device.305873431
Short name T1761
Test name
Test status
Simulation time 380844433 ps
CPU time 21.91 seconds
Started Jan 03 02:10:01 PM PST 24
Finished Jan 03 02:10:35 PM PST 24
Peak memory 555188 kb
Host smart-7d7c31c1-a6e6-4f40-bda4-408cd851d4a8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305873431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.
305873431
Directory /workspace/45.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.4108334598
Short name T1324
Test name
Test status
Simulation time 123925199689 ps
CPU time 2152.23 seconds
Started Jan 03 02:09:55 PM PST 24
Finished Jan 03 02:45:50 PM PST 24
Peak memory 554244 kb
Host smart-701021b7-e034-4e89-906f-1d24f4307ac4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108334598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_
device_slow_rsp.4108334598
Directory /workspace/45.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.3648727422
Short name T1374
Test name
Test status
Simulation time 322878825 ps
CPU time 31.55 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:11:25 PM PST 24
Peak memory 554168 kb
Host smart-3d63e0ea-e041-4cf6-adcb-0251e22726a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648727422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add
r.3648727422
Directory /workspace/45.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_error_random.699049143
Short name T1239
Test name
Test status
Simulation time 1664409851 ps
CPU time 53.27 seconds
Started Jan 03 02:10:05 PM PST 24
Finished Jan 03 02:11:17 PM PST 24
Peak memory 554136 kb
Host smart-677e4279-6ff1-4eb9-8602-ea81f7318c9c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699049143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.699049143
Directory /workspace/45.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random.2474156217
Short name T171
Test name
Test status
Simulation time 472753215 ps
CPU time 41.22 seconds
Started Jan 03 02:10:11 PM PST 24
Finished Jan 03 02:11:10 PM PST 24
Peak memory 553880 kb
Host smart-dc6153b2-3dfb-4e76-ba8b-18ca27199c30
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474156217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.2474156217
Directory /workspace/45.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.3778440132
Short name T1406
Test name
Test status
Simulation time 100474994993 ps
CPU time 1038.82 seconds
Started Jan 03 02:10:28 PM PST 24
Finished Jan 03 02:28:01 PM PST 24
Peak memory 554040 kb
Host smart-7978406b-1c6e-4888-aabe-ddf4f6131f45
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778440132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3778440132
Directory /workspace/45.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3202503959
Short name T155
Test name
Test status
Simulation time 21509144184 ps
CPU time 385.35 seconds
Started Jan 03 02:10:30 PM PST 24
Finished Jan 03 02:17:09 PM PST 24
Peak memory 554304 kb
Host smart-38e91766-5fd3-4884-b6f2-15c9df260f51
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202503959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3202503959
Directory /workspace/45.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.2052354807
Short name T538
Test name
Test status
Simulation time 308328636 ps
CPU time 25.38 seconds
Started Jan 03 02:10:05 PM PST 24
Finished Jan 03 02:10:49 PM PST 24
Peak memory 553868 kb
Host smart-bccb3aca-e906-4e90-8cbb-c85ab0df5ee0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052354807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del
ays.2052354807
Directory /workspace/45.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_same_source.2676731958
Short name T96
Test name
Test status
Simulation time 2581769667 ps
CPU time 78.66 seconds
Started Jan 03 02:09:55 PM PST 24
Finished Jan 03 02:11:17 PM PST 24
Peak memory 553908 kb
Host smart-a71afdca-60ff-4668-af2f-45af58146ba0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676731958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2676731958
Directory /workspace/45.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke.1454777204
Short name T1853
Test name
Test status
Simulation time 201515676 ps
CPU time 9.03 seconds
Started Jan 03 02:10:40 PM PST 24
Finished Jan 03 02:11:04 PM PST 24
Peak memory 552104 kb
Host smart-4a6c550f-cc5e-47ef-9eb2-a7c088357f93
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454777204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1454777204
Directory /workspace/45.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.1645088818
Short name T540
Test name
Test status
Simulation time 8021503674 ps
CPU time 78.42 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:12:41 PM PST 24
Peak memory 552164 kb
Host smart-e81c5e69-60c4-4f2f-a6cc-3a99d914409c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645088818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1645088818
Directory /workspace/45.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1986430314
Short name T825
Test name
Test status
Simulation time 6014166360 ps
CPU time 90.98 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:12:55 PM PST 24
Peak memory 552108 kb
Host smart-a10ad3c4-4fbf-4647-a6cc-1aeaa376b5da
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986430314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1986430314
Directory /workspace/45.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.3860835937
Short name T562
Test name
Test status
Simulation time 33906536 ps
CPU time 5.25 seconds
Started Jan 03 02:10:00 PM PST 24
Finished Jan 03 02:10:14 PM PST 24
Peak memory 551784 kb
Host smart-d31d1c9d-8631-4836-a421-05e9dfa0161e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860835937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay
s.3860835937
Directory /workspace/45.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all.1704701968
Short name T846
Test name
Test status
Simulation time 7590155986 ps
CPU time 278.73 seconds
Started Jan 03 02:10:36 PM PST 24
Finished Jan 03 02:15:28 PM PST 24
Peak memory 555408 kb
Host smart-5665ad0f-e200-49e2-8362-221ff56b7107
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704701968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1704701968
Directory /workspace/45.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.4255313042
Short name T1737
Test name
Test status
Simulation time 1185790044 ps
CPU time 98.93 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:12:32 PM PST 24
Peak memory 553980 kb
Host smart-b8833238-47dc-4c69-af70-1d6bb849e439
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255313042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.4255313042
Directory /workspace/45.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3486415684
Short name T71
Test name
Test status
Simulation time 2939530380 ps
CPU time 395.73 seconds
Started Jan 03 02:10:23 PM PST 24
Finished Jan 03 02:17:14 PM PST 24
Peak memory 558568 kb
Host smart-27a8a807-6a57-418a-8e9e-07a702e44f9d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486415684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all
_with_rand_reset.3486415684
Directory /workspace/45.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1413876351
Short name T1887
Test name
Test status
Simulation time 2109196025 ps
CPU time 134.49 seconds
Started Jan 03 02:10:50 PM PST 24
Finished Jan 03 02:13:28 PM PST 24
Peak memory 555904 kb
Host smart-f2bd89c7-8575-4718-87e6-23b2fc3a7c4c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413876351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al
l_with_reset_error.1413876351
Directory /workspace/45.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.3258208450
Short name T1701
Test name
Test status
Simulation time 923108728 ps
CPU time 37.01 seconds
Started Jan 03 02:10:33 PM PST 24
Finished Jan 03 02:11:23 PM PST 24
Peak memory 554208 kb
Host smart-91f56707-63ae-4582-a477-77e22f410196
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258208450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3258208450
Directory /workspace/45.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_access_same_device.2693229819
Short name T498
Test name
Test status
Simulation time 29856688 ps
CPU time 8.56 seconds
Started Jan 03 02:10:50 PM PST 24
Finished Jan 03 02:11:21 PM PST 24
Peak memory 552848 kb
Host smart-7d31f054-2351-42cb-a57b-3b59045d7113
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693229819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device
.2693229819
Directory /workspace/46.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.373005057
Short name T1059
Test name
Test status
Simulation time 10327662479 ps
CPU time 173.22 seconds
Started Jan 03 02:10:49 PM PST 24
Finished Jan 03 02:14:05 PM PST 24
Peak memory 551772 kb
Host smart-65bc1f55-72f0-442b-b068-4e4ed9d85a81
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373005057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_d
evice_slow_rsp.373005057
Directory /workspace/46.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.3201974513
Short name T674
Test name
Test status
Simulation time 148757945 ps
CPU time 15.67 seconds
Started Jan 03 02:10:52 PM PST 24
Finished Jan 03 02:11:30 PM PST 24
Peak memory 554176 kb
Host smart-cdf45aff-e019-4ba8-8e9a-d51b5e2d601e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201974513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add
r.3201974513
Directory /workspace/46.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_error_random.8464355
Short name T1370
Test name
Test status
Simulation time 357952296 ps
CPU time 27.95 seconds
Started Jan 03 02:10:43 PM PST 24
Finished Jan 03 02:11:31 PM PST 24
Peak memory 554100 kb
Host smart-b24cbd23-2416-4960-aed7-b1145f751510
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8464355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.8464355
Directory /workspace/46.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random.1066518279
Short name T652
Test name
Test status
Simulation time 239787362 ps
CPU time 11.01 seconds
Started Jan 03 02:10:36 PM PST 24
Finished Jan 03 02:11:00 PM PST 24
Peak memory 551876 kb
Host smart-7870a0ac-d3f5-4ae0-a85f-c09347cecc7f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066518279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.1066518279
Directory /workspace/46.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.867899609
Short name T683
Test name
Test status
Simulation time 68019436062 ps
CPU time 691.55 seconds
Started Jan 03 02:10:50 PM PST 24
Finished Jan 03 02:22:44 PM PST 24
Peak memory 553100 kb
Host smart-4e26c7e3-a114-41fd-bc8a-4baec6e1d9be
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867899609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.867899609
Directory /workspace/46.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2464862733
Short name T553
Test name
Test status
Simulation time 21554043692 ps
CPU time 380.3 seconds
Started Jan 03 02:10:41 PM PST 24
Finished Jan 03 02:17:18 PM PST 24
Peak memory 553180 kb
Host smart-c219b646-65e2-4262-967d-9bbc16f6e54f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464862733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2464862733
Directory /workspace/46.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.2048048139
Short name T861
Test name
Test status
Simulation time 81230558 ps
CPU time 9.97 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:11:26 PM PST 24
Peak memory 554128 kb
Host smart-eb2381fe-8784-4320-a24e-66dc2eefb4ea
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048048139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del
ays.2048048139
Directory /workspace/46.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_same_source.2829248264
Short name T938
Test name
Test status
Simulation time 2760673588 ps
CPU time 78.19 seconds
Started Jan 03 02:10:53 PM PST 24
Finished Jan 03 02:12:34 PM PST 24
Peak memory 554248 kb
Host smart-a1084cc3-968a-452d-8683-6f843065b544
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829248264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2829248264
Directory /workspace/46.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke.1008969663
Short name T831
Test name
Test status
Simulation time 165695774 ps
CPU time 7.89 seconds
Started Jan 03 02:10:12 PM PST 24
Finished Jan 03 02:10:36 PM PST 24
Peak memory 552072 kb
Host smart-878f8bb7-a600-4f27-8f31-7769684fb313
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008969663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1008969663
Directory /workspace/46.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.1889260715
Short name T1102
Test name
Test status
Simulation time 8775005707 ps
CPU time 99.4 seconds
Started Jan 03 02:10:36 PM PST 24
Finished Jan 03 02:12:28 PM PST 24
Peak memory 551844 kb
Host smart-56e2761f-2211-4572-b026-9735be5ead5d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889260715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1889260715
Directory /workspace/46.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.4073061798
Short name T1332
Test name
Test status
Simulation time 5213062704 ps
CPU time 94.01 seconds
Started Jan 03 02:10:22 PM PST 24
Finished Jan 03 02:12:11 PM PST 24
Peak memory 551840 kb
Host smart-237bc9ed-d694-4027-9b6a-b8f80982058f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073061798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.4073061798
Directory /workspace/46.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2628617090
Short name T990
Test name
Test status
Simulation time 44428965 ps
CPU time 5.85 seconds
Started Jan 03 02:10:48 PM PST 24
Finished Jan 03 02:11:17 PM PST 24
Peak memory 551760 kb
Host smart-c7bc4594-4f1d-4ea4-a646-15f6bc852c64
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628617090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay
s.2628617090
Directory /workspace/46.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all.1247362485
Short name T1460
Test name
Test status
Simulation time 12013164054 ps
CPU time 402.95 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:18:02 PM PST 24
Peak memory 555412 kb
Host smart-c8517f18-8053-48b5-9bde-762271f33cc6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247362485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1247362485
Directory /workspace/46.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.948050349
Short name T1083
Test name
Test status
Simulation time 7054594251 ps
CPU time 212.77 seconds
Started Jan 03 02:10:52 PM PST 24
Finished Jan 03 02:14:47 PM PST 24
Peak memory 555124 kb
Host smart-ca03768c-0361-4ea8-afca-a52a71ca160c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948050349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.948050349
Directory /workspace/46.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.2323255741
Short name T1724
Test name
Test status
Simulation time 3929429972 ps
CPU time 494.13 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:19:09 PM PST 24
Peak memory 559132 kb
Host smart-b992c35c-e35b-40d9-8fc5-db737debd9af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323255741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all
_with_rand_reset.2323255741
Directory /workspace/46.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.2133392096
Short name T1760
Test name
Test status
Simulation time 2762376723 ps
CPU time 362.37 seconds
Started Jan 03 02:10:52 PM PST 24
Finished Jan 03 02:17:17 PM PST 24
Peak memory 567260 kb
Host smart-acc24f7f-43c9-4e65-89cd-fe57aa937e2a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133392096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al
l_with_reset_error.2133392096
Directory /workspace/46.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.4265968369
Short name T1602
Test name
Test status
Simulation time 304092234 ps
CPU time 32.26 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:11:51 PM PST 24
Peak memory 554004 kb
Host smart-4d45d7cb-9348-4f49-aa5c-4112381313e5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265968369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.4265968369
Directory /workspace/46.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_access_same_device.695019565
Short name T87
Test name
Test status
Simulation time 2231159535 ps
CPU time 84.89 seconds
Started Jan 03 02:10:41 PM PST 24
Finished Jan 03 02:12:23 PM PST 24
Peak memory 555252 kb
Host smart-64da513d-aef7-4c26-9d51-dbe26a34e0f6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695019565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.
695019565
Directory /workspace/47.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.3288512850
Short name T1693
Test name
Test status
Simulation time 141818029905 ps
CPU time 2171.85 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:47:30 PM PST 24
Peak memory 554256 kb
Host smart-095024dc-0788-48fa-b780-036e4bca6999
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288512850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_
device_slow_rsp.3288512850
Directory /workspace/47.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1630181563
Short name T1019
Test name
Test status
Simulation time 1334453284 ps
CPU time 51.5 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:12:10 PM PST 24
Peak memory 554004 kb
Host smart-c3c50301-98d5-4871-abd9-9e1168a748be
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630181563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add
r.1630181563
Directory /workspace/47.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_error_random.3539222041
Short name T1278
Test name
Test status
Simulation time 1406995693 ps
CPU time 41.31 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:11:57 PM PST 24
Peak memory 553860 kb
Host smart-60362998-0344-4220-a60a-e8c1a00449c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539222041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3539222041
Directory /workspace/47.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random.1894158045
Short name T1208
Test name
Test status
Simulation time 1000137879 ps
CPU time 34.63 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:11:53 PM PST 24
Peak memory 554276 kb
Host smart-dc82d643-f546-488b-a030-566c551a9a03
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894158045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.1894158045
Directory /workspace/47.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.2806572526
Short name T509
Test name
Test status
Simulation time 13717389469 ps
CPU time 134.46 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:13:39 PM PST 24
Peak memory 553736 kb
Host smart-423f7828-6823-44f1-bafa-34cfb549944e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806572526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2806572526
Directory /workspace/47.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.1060246423
Short name T1328
Test name
Test status
Simulation time 51462887405 ps
CPU time 878.35 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:25:57 PM PST 24
Peak memory 554376 kb
Host smart-7b04ac9e-5cec-4f82-98f5-c8389f829022
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060246423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1060246423
Directory /workspace/47.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.3944330943
Short name T186
Test name
Test status
Simulation time 537341818 ps
CPU time 47.92 seconds
Started Jan 03 02:10:53 PM PST 24
Finished Jan 03 02:12:03 PM PST 24
Peak memory 553068 kb
Host smart-0c14b992-255d-4c96-ad4e-5fc1e50f42a1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944330943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del
ays.3944330943
Directory /workspace/47.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_same_source.332285383
Short name T1564
Test name
Test status
Simulation time 94461551 ps
CPU time 9.52 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:11:33 PM PST 24
Peak memory 553864 kb
Host smart-19a11245-e74c-4cd6-b49e-e5a3674400ba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332285383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.332285383
Directory /workspace/47.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke.123774452
Short name T736
Test name
Test status
Simulation time 174652542 ps
CPU time 7.57 seconds
Started Jan 03 02:10:55 PM PST 24
Finished Jan 03 02:11:24 PM PST 24
Peak memory 552108 kb
Host smart-f228da95-11ce-48da-b842-b6f779123b61
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123774452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.123774452
Directory /workspace/47.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.3451817240
Short name T1015
Test name
Test status
Simulation time 6351585563 ps
CPU time 67.17 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:12:30 PM PST 24
Peak memory 552164 kb
Host smart-25513247-8321-427d-8f2b-e6a0563dbc46
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451817240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.3451817240
Directory /workspace/47.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1963507966
Short name T1758
Test name
Test status
Simulation time 4217594857 ps
CPU time 63.56 seconds
Started Jan 03 02:11:03 PM PST 24
Finished Jan 03 02:12:28 PM PST 24
Peak memory 551844 kb
Host smart-f78645d5-cc49-42ab-8c70-c7509da6bb53
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963507966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1963507966
Directory /workspace/47.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3579001045
Short name T91
Test name
Test status
Simulation time 41946214 ps
CPU time 5.5 seconds
Started Jan 03 02:10:58 PM PST 24
Finished Jan 03 02:11:26 PM PST 24
Peak memory 551756 kb
Host smart-90bf44f2-2d11-4236-aa58-04a7af2cbb51
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579001045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay
s.3579001045
Directory /workspace/47.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all.1123711324
Short name T1157
Test name
Test status
Simulation time 13699312586 ps
CPU time 505.84 seconds
Started Jan 03 02:11:00 PM PST 24
Finished Jan 03 02:19:48 PM PST 24
Peak memory 555076 kb
Host smart-2db5f348-ee1e-41c5-ad29-08ed82755581
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123711324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1123711324
Directory /workspace/47.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.1238166461
Short name T719
Test name
Test status
Simulation time 13733884859 ps
CPU time 413.91 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:18:17 PM PST 24
Peak memory 555448 kb
Host smart-daad788d-3a89-4178-a659-a1360efcc1d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238166461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1238166461
Directory /workspace/47.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1228437945
Short name T138
Test name
Test status
Simulation time 1290294011 ps
CPU time 248.74 seconds
Started Jan 03 02:11:03 PM PST 24
Finished Jan 03 02:15:33 PM PST 24
Peak memory 556356 kb
Host smart-547ca0b1-36e3-4d17-9453-9929005a28f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228437945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all
_with_rand_reset.1228437945
Directory /workspace/47.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1666463143
Short name T1709
Test name
Test status
Simulation time 5056843310 ps
CPU time 249.94 seconds
Started Jan 03 02:09:53 PM PST 24
Finished Jan 03 02:14:05 PM PST 24
Peak memory 557000 kb
Host smart-71050e98-b6bc-4dfe-989e-5c041718a20c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666463143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al
l_with_reset_error.1666463143
Directory /workspace/47.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.1565948102
Short name T166
Test name
Test status
Simulation time 170608340 ps
CPU time 20.04 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:11:36 PM PST 24
Peak memory 553920 kb
Host smart-b1fd1111-ad30-4b6a-a40b-712c149ed33c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565948102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1565948102
Directory /workspace/47.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_access_same_device.1431536706
Short name T1876
Test name
Test status
Simulation time 1271508756 ps
CPU time 57.28 seconds
Started Jan 03 02:09:56 PM PST 24
Finished Jan 03 02:10:56 PM PST 24
Peak memory 554936 kb
Host smart-f40c4478-557f-4393-a640-d5fcf4484a3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431536706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device
.1431536706
Directory /workspace/48.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3533445725
Short name T1447
Test name
Test status
Simulation time 32052669289 ps
CPU time 519.97 seconds
Started Jan 03 02:10:28 PM PST 24
Finished Jan 03 02:19:23 PM PST 24
Peak memory 554204 kb
Host smart-c3d2f623-0858-455a-88ee-1c9cfea93b6e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533445725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_
device_slow_rsp.3533445725
Directory /workspace/48.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1474227828
Short name T379
Test name
Test status
Simulation time 38364492 ps
CPU time 6.39 seconds
Started Jan 03 02:10:43 PM PST 24
Finished Jan 03 02:11:08 PM PST 24
Peak memory 551844 kb
Host smart-fd9ca3cb-909c-45a6-b868-984a81af77b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474227828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add
r.1474227828
Directory /workspace/48.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_error_random.2801494447
Short name T814
Test name
Test status
Simulation time 1941518938 ps
CPU time 66.16 seconds
Started Jan 03 02:10:12 PM PST 24
Finished Jan 03 02:11:35 PM PST 24
Peak memory 553836 kb
Host smart-7b05edf8-5344-42ca-b929-9b1426879c18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801494447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2801494447
Directory /workspace/48.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random.2687273129
Short name T230
Test name
Test status
Simulation time 1734514292 ps
CPU time 60.72 seconds
Started Jan 03 02:10:13 PM PST 24
Finished Jan 03 02:11:30 PM PST 24
Peak memory 554184 kb
Host smart-f51fb820-e253-4a84-8fb7-5affd34816cc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687273129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2687273129
Directory /workspace/48.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.1959512987
Short name T213
Test name
Test status
Simulation time 85638752589 ps
CPU time 818.3 seconds
Started Jan 03 02:10:44 PM PST 24
Finished Jan 03 02:24:43 PM PST 24
Peak memory 554156 kb
Host smart-fe2df158-7c12-4f2f-a38e-910ea6b2be18
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959512987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1959512987
Directory /workspace/48.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.416385234
Short name T870
Test name
Test status
Simulation time 60132613354 ps
CPU time 1060.56 seconds
Started Jan 03 02:10:33 PM PST 24
Finished Jan 03 02:28:26 PM PST 24
Peak memory 554184 kb
Host smart-3e968192-0f3e-4a71-b930-9357d96f3332
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416385234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.416385234
Directory /workspace/48.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.540274855
Short name T490
Test name
Test status
Simulation time 134487419 ps
CPU time 14.95 seconds
Started Jan 03 02:10:01 PM PST 24
Finished Jan 03 02:10:29 PM PST 24
Peak memory 554076 kb
Host smart-890a99ac-f40a-4e9a-807e-34b440937608
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540274855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_dela
ys.540274855
Directory /workspace/48.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_same_source.2680506034
Short name T1265
Test name
Test status
Simulation time 566958428 ps
CPU time 38.94 seconds
Started Jan 03 02:10:00 PM PST 24
Finished Jan 03 02:10:47 PM PST 24
Peak memory 554196 kb
Host smart-001a1185-5f2b-4d08-bda1-1b003d9123f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680506034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2680506034
Directory /workspace/48.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke.3222992813
Short name T992
Test name
Test status
Simulation time 192870210 ps
CPU time 7.86 seconds
Started Jan 03 02:10:02 PM PST 24
Finished Jan 03 02:10:26 PM PST 24
Peak memory 551672 kb
Host smart-52e5056c-e8d7-42ee-b666-244d6cba96cd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222992813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3222992813
Directory /workspace/48.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.1107472161
Short name T216
Test name
Test status
Simulation time 9149091934 ps
CPU time 104.31 seconds
Started Jan 03 02:10:36 PM PST 24
Finished Jan 03 02:12:33 PM PST 24
Peak memory 552072 kb
Host smart-57ac11ed-adc9-4b1b-996c-8d3c7ea26cd3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107472161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1107472161
Directory /workspace/48.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.4106751748
Short name T730
Test name
Test status
Simulation time 5647961750 ps
CPU time 93.76 seconds
Started Jan 03 02:10:01 PM PST 24
Finished Jan 03 02:11:50 PM PST 24
Peak memory 551672 kb
Host smart-e39cfdfd-e726-437c-a1f4-a76494f42f45
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106751748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.4106751748
Directory /workspace/48.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.4079557546
Short name T1645
Test name
Test status
Simulation time 52404373 ps
CPU time 6.32 seconds
Started Jan 03 02:10:02 PM PST 24
Finished Jan 03 02:10:24 PM PST 24
Peak memory 551724 kb
Host smart-174ea924-bdb0-422b-b236-646d053fb261
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079557546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay
s.4079557546
Directory /workspace/48.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all.757197615
Short name T878
Test name
Test status
Simulation time 4374097631 ps
CPU time 163.73 seconds
Started Jan 03 02:10:41 PM PST 24
Finished Jan 03 02:13:42 PM PST 24
Peak memory 555424 kb
Host smart-e0a61b2a-8677-4944-9214-09ce843998d3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757197615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.757197615
Directory /workspace/48.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.3369119407
Short name T1622
Test name
Test status
Simulation time 750744099 ps
CPU time 45.16 seconds
Started Jan 03 02:10:48 PM PST 24
Finished Jan 03 02:11:56 PM PST 24
Peak memory 554172 kb
Host smart-618fad04-0c61-46ff-a697-8c51fc872622
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369119407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3369119407
Directory /workspace/48.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.3976816580
Short name T873
Test name
Test status
Simulation time 11788223355 ps
CPU time 603.4 seconds
Started Jan 03 02:10:18 PM PST 24
Finished Jan 03 02:20:34 PM PST 24
Peak memory 556276 kb
Host smart-249eedcd-8744-41a6-a0aa-0fdffefca425
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976816580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all
_with_rand_reset.3976816580
Directory /workspace/48.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1656224837
Short name T337
Test name
Test status
Simulation time 587578115 ps
CPU time 177.81 seconds
Started Jan 03 02:10:48 PM PST 24
Finished Jan 03 02:14:08 PM PST 24
Peak memory 558516 kb
Host smart-5749e60b-237d-4a4e-aebe-2155dfadbc21
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656224837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al
l_with_reset_error.1656224837
Directory /workspace/48.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.3780321529
Short name T1372
Test name
Test status
Simulation time 1346722397 ps
CPU time 54.86 seconds
Started Jan 03 02:10:38 PM PST 24
Finished Jan 03 02:11:47 PM PST 24
Peak memory 554228 kb
Host smart-11858b44-d551-43f5-9c7c-a440f2a61061
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780321529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3780321529
Directory /workspace/48.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_access_same_device.2637999404
Short name T711
Test name
Test status
Simulation time 72961740 ps
CPU time 7.28 seconds
Started Jan 03 02:10:53 PM PST 24
Finished Jan 03 02:11:23 PM PST 24
Peak memory 552124 kb
Host smart-dee5d634-413e-4310-b200-2d8cc146b027
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637999404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device
.2637999404
Directory /workspace/49.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.44158629
Short name T1660
Test name
Test status
Simulation time 69200119672 ps
CPU time 1198.48 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:30:52 PM PST 24
Peak memory 554268 kb
Host smart-b63e1365-a4ac-46d4-ac6e-171a2c0d22ab
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44158629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_de
vice_slow_rsp.44158629
Directory /workspace/49.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.707600977
Short name T371
Test name
Test status
Simulation time 789252192 ps
CPU time 29.89 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:11:48 PM PST 24
Peak memory 554152 kb
Host smart-4700cfe6-67a7-42d6-91f6-6aefb51c07d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707600977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr
.707600977
Directory /workspace/49.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_error_random.3917163226
Short name T412
Test name
Test status
Simulation time 366873724 ps
CPU time 28.12 seconds
Started Jan 03 02:10:44 PM PST 24
Finished Jan 03 02:11:33 PM PST 24
Peak memory 554120 kb
Host smart-dd5cf3bf-f262-4594-99c1-a626e2b04513
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917163226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3917163226
Directory /workspace/49.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random.4171906909
Short name T650
Test name
Test status
Simulation time 229100934 ps
CPU time 19.6 seconds
Started Jan 03 02:10:46 PM PST 24
Finished Jan 03 02:11:29 PM PST 24
Peak memory 553888 kb
Host smart-17aec524-8571-4dc4-8590-a5d11971718b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171906909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.4171906909
Directory /workspace/49.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.1654691941
Short name T1095
Test name
Test status
Simulation time 34898281436 ps
CPU time 386.32 seconds
Started Jan 03 02:10:55 PM PST 24
Finished Jan 03 02:17:43 PM PST 24
Peak memory 553128 kb
Host smart-01771274-9054-4480-81db-3bd0b16e81b7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654691941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1654691941
Directory /workspace/49.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.3546240533
Short name T1646
Test name
Test status
Simulation time 38860496306 ps
CPU time 620.8 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:21:39 PM PST 24
Peak memory 554236 kb
Host smart-975bd611-14ef-4949-872e-e595763e78bb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546240533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3546240533
Directory /workspace/49.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.1953983988
Short name T1869
Test name
Test status
Simulation time 105689865 ps
CPU time 10.35 seconds
Started Jan 03 02:10:41 PM PST 24
Finished Jan 03 02:11:08 PM PST 24
Peak memory 553864 kb
Host smart-ae3348cf-201c-49a6-b7cc-f74406439a05
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953983988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del
ays.1953983988
Directory /workspace/49.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_same_source.4074270724
Short name T191
Test name
Test status
Simulation time 249087018 ps
CPU time 10.43 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:11:04 PM PST 24
Peak memory 551660 kb
Host smart-1c80f825-215b-4c37-9030-d68dfedc8250
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074270724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.4074270724
Directory /workspace/49.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke.4017539075
Short name T1199
Test name
Test status
Simulation time 207683276 ps
CPU time 8.72 seconds
Started Jan 03 02:10:43 PM PST 24
Finished Jan 03 02:11:11 PM PST 24
Peak memory 551772 kb
Host smart-54dc85fa-dd2f-4532-87e3-6ea7ffdf34e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017539075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.4017539075
Directory /workspace/49.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.831764147
Short name T1815
Test name
Test status
Simulation time 7725820642 ps
CPU time 83.13 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:12:17 PM PST 24
Peak memory 552080 kb
Host smart-047fa9b4-8774-4203-9f10-1812573a5a4c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831764147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.831764147
Directory /workspace/49.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1331464416
Short name T1357
Test name
Test status
Simulation time 5288422718 ps
CPU time 90.34 seconds
Started Jan 03 02:10:49 PM PST 24
Finished Jan 03 02:12:43 PM PST 24
Peak memory 551836 kb
Host smart-ef8d4811-a383-48ff-8c26-54b2f747554b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331464416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1331464416
Directory /workspace/49.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3695689873
Short name T1390
Test name
Test status
Simulation time 44471013 ps
CPU time 6.09 seconds
Started Jan 03 02:10:47 PM PST 24
Finished Jan 03 02:11:16 PM PST 24
Peak memory 552020 kb
Host smart-b4250d79-e2e4-4ae8-87df-cb3e57d109da
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695689873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay
s.3695689873
Directory /workspace/49.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all.1085538792
Short name T177
Test name
Test status
Simulation time 13347045210 ps
CPU time 418.91 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:18:18 PM PST 24
Peak memory 555228 kb
Host smart-3ef91db6-56f5-45f8-a58a-5ab00747bbb0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085538792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1085538792
Directory /workspace/49.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.2622160902
Short name T1187
Test name
Test status
Simulation time 2641155320 ps
CPU time 193.63 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:14:30 PM PST 24
Peak memory 555260 kb
Host smart-13533c0f-bc37-49ba-bf16-af20e307c450
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622160902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2622160902
Directory /workspace/49.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.373321539
Short name T259
Test name
Test status
Simulation time 6853706214 ps
CPU time 390.35 seconds
Started Jan 03 02:10:58 PM PST 24
Finished Jan 03 02:17:50 PM PST 24
Peak memory 556500 kb
Host smart-e1478378-b748-4fe0-9bae-fb54be2e4090
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373321539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_
with_rand_reset.373321539
Directory /workspace/49.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.218537542
Short name T1644
Test name
Test status
Simulation time 2015577991 ps
CPU time 192.84 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:14:37 PM PST 24
Peak memory 555736 kb
Host smart-5e914fbb-48e5-4a1f-9daf-450dd4d3a4e7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218537542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all
_with_reset_error.218537542
Directory /workspace/49.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.848846893
Short name T690
Test name
Test status
Simulation time 719043222 ps
CPU time 32.24 seconds
Started Jan 03 02:10:53 PM PST 24
Finished Jan 03 02:11:48 PM PST 24
Peak memory 553996 kb
Host smart-e519248f-49b6-461e-bae8-bf9e579c6527
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848846893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.848846893
Directory /workspace/49.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1716591033
Short name T1865
Test name
Test status
Simulation time 8933172507 ps
CPU time 408.17 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:14:36 PM PST 24
Peak memory 620080 kb
Host smart-bac3274e-0ce9-43d0-b316-0ed6c089d65b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716591033 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.1716591033
Directory /workspace/5.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.chip_csr_rw.4217346881
Short name T1364
Test name
Test status
Simulation time 4763785160 ps
CPU time 478.61 seconds
Started Jan 03 02:07:19 PM PST 24
Finished Jan 03 02:15:27 PM PST 24
Peak memory 579992 kb
Host smart-1840896a-035b-4dcd-941f-5ff416290785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217346881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.4217346881
Directory /workspace/5.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.1414199531
Short name T9
Test name
Test status
Simulation time 16082999811 ps
CPU time 1663.68 seconds
Started Jan 03 02:07:44 PM PST 24
Finished Jan 03 02:35:40 PM PST 24
Peak memory 580052 kb
Host smart-92ab7de9-c5f4-4d82-abcf-b6179819b401
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414199531 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.1414199531
Directory /workspace/5.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.chip_tl_errors.272042009
Short name T1718
Test name
Test status
Simulation time 2953034206 ps
CPU time 182.06 seconds
Started Jan 03 02:07:35 PM PST 24
Finished Jan 03 02:10:48 PM PST 24
Peak memory 580084 kb
Host smart-bc61a1e1-03c6-44bc-8460-24bdc757b2c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272042009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.272042009
Directory /workspace/5.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_access_same_device.3310722741
Short name T1227
Test name
Test status
Simulation time 697258842 ps
CPU time 30.83 seconds
Started Jan 03 02:07:31 PM PST 24
Finished Jan 03 02:08:10 PM PST 24
Peak memory 553848 kb
Host smart-08b2b0fb-a0e4-4b73-b7b2-59c6253e512d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310722741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.
3310722741
Directory /workspace/5.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3309556103
Short name T1275
Test name
Test status
Simulation time 53760948967 ps
CPU time 946.06 seconds
Started Jan 03 02:07:37 PM PST 24
Finished Jan 03 02:23:35 PM PST 24
Peak memory 554016 kb
Host smart-b58238e6-5312-423d-9f02-0956f0bdf62a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309556103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d
evice_slow_rsp.3309556103
Directory /workspace/5.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.3401016813
Short name T1762
Test name
Test status
Simulation time 455489754 ps
CPU time 18.63 seconds
Started Jan 03 02:07:37 PM PST 24
Finished Jan 03 02:08:08 PM PST 24
Peak memory 553880 kb
Host smart-25cb8deb-eb4f-4167-95f6-af4918815a90
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401016813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr
.3401016813
Directory /workspace/5.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_error_random.3936490422
Short name T1099
Test name
Test status
Simulation time 1663780809 ps
CPU time 52.51 seconds
Started Jan 03 02:07:27 PM PST 24
Finished Jan 03 02:08:30 PM PST 24
Peak memory 554128 kb
Host smart-7d472ea2-7ea7-4ccc-83d8-b8274e9a41e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936490422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3936490422
Directory /workspace/5.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random.2437908624
Short name T82
Test name
Test status
Simulation time 2441619947 ps
CPU time 81.19 seconds
Started Jan 03 02:07:54 PM PST 24
Finished Jan 03 02:09:26 PM PST 24
Peak memory 554200 kb
Host smart-775677fe-d0b9-4db3-a8b4-231738df53f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437908624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.2437908624
Directory /workspace/5.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.1401798869
Short name T1419
Test name
Test status
Simulation time 81157870774 ps
CPU time 881.82 seconds
Started Jan 03 02:07:30 PM PST 24
Finished Jan 03 02:22:21 PM PST 24
Peak memory 553940 kb
Host smart-29801add-a899-495e-8bfc-8ca23341a673
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401798869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1401798869
Directory /workspace/5.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.2334827398
Short name T508
Test name
Test status
Simulation time 2579368656 ps
CPU time 39.37 seconds
Started Jan 03 02:07:37 PM PST 24
Finished Jan 03 02:08:27 PM PST 24
Peak memory 551820 kb
Host smart-35381b47-4441-4811-a5de-6af173624836
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334827398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2334827398
Directory /workspace/5.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2373510142
Short name T839
Test name
Test status
Simulation time 73145383 ps
CPU time 8.21 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:08:17 PM PST 24
Peak memory 551820 kb
Host smart-e51d6698-a804-4b64-beea-e09c695f395d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373510142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela
ys.2373510142
Directory /workspace/5.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_same_source.428248007
Short name T1553
Test name
Test status
Simulation time 279240408 ps
CPU time 20.19 seconds
Started Jan 03 02:07:20 PM PST 24
Finished Jan 03 02:07:53 PM PST 24
Peak memory 554172 kb
Host smart-bb5bbf88-abbc-4c3e-89d6-a0498f13f212
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428248007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.428248007
Directory /workspace/5.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke.1723252297
Short name T1274
Test name
Test status
Simulation time 200745720 ps
CPU time 7.92 seconds
Started Jan 03 02:07:27 PM PST 24
Finished Jan 03 02:07:46 PM PST 24
Peak memory 552020 kb
Host smart-70e866ff-e488-4c04-a37a-b16495340170
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723252297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1723252297
Directory /workspace/5.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.3187494866
Short name T222
Test name
Test status
Simulation time 8399542681 ps
CPU time 85.08 seconds
Started Jan 03 02:07:32 PM PST 24
Finished Jan 03 02:09:07 PM PST 24
Peak memory 551812 kb
Host smart-c7c47a74-751d-4b89-aab1-b54718c58a73
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187494866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3187494866
Directory /workspace/5.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.2390228841
Short name T1683
Test name
Test status
Simulation time 5423887632 ps
CPU time 89.41 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:09:15 PM PST 24
Peak memory 551896 kb
Host smart-32546b2c-ba36-4504-af1c-2f06f8cd097a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390228841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2390228841
Directory /workspace/5.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.2876466734
Short name T767
Test name
Test status
Simulation time 46073910 ps
CPU time 5.68 seconds
Started Jan 03 02:07:18 PM PST 24
Finished Jan 03 02:07:32 PM PST 24
Peak memory 551680 kb
Host smart-034b1910-ff76-419b-a881-ac25d79195ea
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876466734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays
.2876466734
Directory /workspace/5.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all.2700150690
Short name T95
Test name
Test status
Simulation time 3161979336 ps
CPU time 227.61 seconds
Started Jan 03 02:07:35 PM PST 24
Finished Jan 03 02:11:32 PM PST 24
Peak memory 555692 kb
Host smart-886d64eb-b238-4eaa-836e-5ab73c7ecfa9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700150690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2700150690
Directory /workspace/5.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.2631369458
Short name T1159
Test name
Test status
Simulation time 2795112784 ps
CPU time 202.24 seconds
Started Jan 03 02:07:59 PM PST 24
Finished Jan 03 02:11:31 PM PST 24
Peak memory 555352 kb
Host smart-18c70593-6df1-4818-a36b-cc494fcd8d7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631369458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2631369458
Directory /workspace/5.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.78213552
Short name T355
Test name
Test status
Simulation time 917341388 ps
CPU time 149.01 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:10:16 PM PST 24
Peak memory 555336 kb
Host smart-2b3648ba-b710-4f22-9b49-74a25fbf85da
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78213552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_wi
th_rand_reset.78213552
Directory /workspace/5.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2241276635
Short name T301
Test name
Test status
Simulation time 329233711 ps
CPU time 102.62 seconds
Started Jan 03 02:07:31 PM PST 24
Finished Jan 03 02:09:23 PM PST 24
Peak memory 555464 kb
Host smart-7a6ffc15-d973-42ca-a01a-fa8d5def755b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241276635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all
_with_reset_error.2241276635
Directory /workspace/5.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.1959627085
Short name T457
Test name
Test status
Simulation time 1417535206 ps
CPU time 59.87 seconds
Started Jan 03 02:07:26 PM PST 24
Finished Jan 03 02:08:36 PM PST 24
Peak memory 554228 kb
Host smart-68b4441b-1ab0-49a3-b9e0-a3bd2cf534d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959627085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1959627085
Directory /workspace/5.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_access_same_device.4209944308
Short name T1839
Test name
Test status
Simulation time 2392029338 ps
CPU time 92.14 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:12:56 PM PST 24
Peak memory 554220 kb
Host smart-d4c5c070-f5ef-40bf-b6f3-66b56ccc356c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209944308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device
.4209944308
Directory /workspace/50.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.3567410212
Short name T930
Test name
Test status
Simulation time 139177224510 ps
CPU time 2178.05 seconds
Started Jan 03 02:10:53 PM PST 24
Finished Jan 03 02:47:34 PM PST 24
Peak memory 555000 kb
Host smart-87e1f345-decd-45e5-b59f-f1649e86cc9f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567410212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_
device_slow_rsp.3567410212
Directory /workspace/50.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1728796824
Short name T1699
Test name
Test status
Simulation time 1023593310 ps
CPU time 39.87 seconds
Started Jan 03 02:09:55 PM PST 24
Finished Jan 03 02:10:39 PM PST 24
Peak memory 554152 kb
Host smart-dc4800c1-2bed-4c1f-bcd2-509538509cd5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728796824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add
r.1728796824
Directory /workspace/50.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_error_random.1022816387
Short name T1066
Test name
Test status
Simulation time 224896381 ps
CPU time 10.29 seconds
Started Jan 03 02:10:37 PM PST 24
Finished Jan 03 02:11:00 PM PST 24
Peak memory 552088 kb
Host smart-f7e9ad35-4e06-4ee9-9ea2-bf35ad79d6ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022816387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.1022816387
Directory /workspace/50.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random.2066498408
Short name T1113
Test name
Test status
Simulation time 1723191110 ps
CPU time 57.86 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:12:21 PM PST 24
Peak memory 553096 kb
Host smart-1937ff8c-40f2-4d84-a8e3-2ab7e234fc8a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066498408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.2066498408
Directory /workspace/50.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.2906582157
Short name T898
Test name
Test status
Simulation time 40206652202 ps
CPU time 403.98 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:18:07 PM PST 24
Peak memory 553992 kb
Host smart-9d99c19a-82ae-408e-a66f-8ebe656c9535
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906582157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.2906582157
Directory /workspace/50.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.434518422
Short name T1567
Test name
Test status
Simulation time 10861766658 ps
CPU time 182.08 seconds
Started Jan 03 02:09:55 PM PST 24
Finished Jan 03 02:12:59 PM PST 24
Peak memory 554300 kb
Host smart-4c4c3ca2-e2e1-42f9-8e3c-d2d47b9db8a5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434518422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.434518422
Directory /workspace/50.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.2567755177
Short name T1120
Test name
Test status
Simulation time 584207438 ps
CPU time 50.2 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:11:50 PM PST 24
Peak memory 553868 kb
Host smart-d2bb5017-c184-4b42-89b7-6b235798cbe1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567755177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del
ays.2567755177
Directory /workspace/50.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_same_source.3603715087
Short name T135
Test name
Test status
Simulation time 2261305289 ps
CPU time 70.27 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:12:29 PM PST 24
Peak memory 553896 kb
Host smart-fb3b7403-8644-4000-a796-77094475eda4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603715087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.3603715087
Directory /workspace/50.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke.1851137971
Short name T422
Test name
Test status
Simulation time 222268889 ps
CPU time 8.77 seconds
Started Jan 03 02:10:59 PM PST 24
Finished Jan 03 02:11:29 PM PST 24
Peak memory 552080 kb
Host smart-845f5d4e-68c1-493b-be8e-a09ef8d5f768
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851137971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.1851137971
Directory /workspace/50.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.948193209
Short name T827
Test name
Test status
Simulation time 7338694771 ps
CPU time 79.62 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:12:38 PM PST 24
Peak memory 551972 kb
Host smart-c5447cc6-2cb8-4194-b9ef-9895b931a46c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948193209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.948193209
Directory /workspace/50.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3589314492
Short name T1150
Test name
Test status
Simulation time 4958725039 ps
CPU time 79.78 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:12:39 PM PST 24
Peak memory 552260 kb
Host smart-25ac8a15-204e-451d-8f56-1190b07b7b70
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589314492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.3589314492
Directory /workspace/50.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3957930007
Short name T1237
Test name
Test status
Simulation time 53525615 ps
CPU time 6.43 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:11:23 PM PST 24
Peak memory 552104 kb
Host smart-ce63b432-d7a0-4d46-8289-301de64b9d17
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957930007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay
s.3957930007
Directory /workspace/50.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all.3918524670
Short name T635
Test name
Test status
Simulation time 3945331672 ps
CPU time 136.72 seconds
Started Jan 03 02:10:43 PM PST 24
Finished Jan 03 02:13:18 PM PST 24
Peak memory 555392 kb
Host smart-d7e312eb-31f4-4b9d-8336-a40c2ebcd3d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918524670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.3918524670
Directory /workspace/50.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2337642898
Short name T1103
Test name
Test status
Simulation time 6346585333 ps
CPU time 359.01 seconds
Started Jan 03 02:10:10 PM PST 24
Finished Jan 03 02:16:27 PM PST 24
Peak memory 557168 kb
Host smart-236a79e6-3429-416c-9bbc-118faf714684
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337642898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all
_with_rand_reset.2337642898
Directory /workspace/50.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.3316629262
Short name T1143
Test name
Test status
Simulation time 35583617 ps
CPU time 14.23 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:11:37 PM PST 24
Peak memory 552992 kb
Host smart-e3e5a380-9bdf-4195-8cbe-7760932f4f2b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316629262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al
l_with_reset_error.3316629262
Directory /workspace/50.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.3626661811
Short name T516
Test name
Test status
Simulation time 486214533 ps
CPU time 20.69 seconds
Started Jan 03 02:10:01 PM PST 24
Finished Jan 03 02:10:34 PM PST 24
Peak memory 553924 kb
Host smart-a6a54b64-4994-4c4f-8466-c5ad9349b4f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626661811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.3626661811
Directory /workspace/50.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_access_same_device.2246461832
Short name T496
Test name
Test status
Simulation time 597413728 ps
CPU time 42.21 seconds
Started Jan 03 02:10:44 PM PST 24
Finished Jan 03 02:11:47 PM PST 24
Peak memory 553836 kb
Host smart-6db70bbe-1cfa-4348-8a94-7413a52f4730
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246461832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device
.2246461832
Directory /workspace/51.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.3360836330
Short name T1124
Test name
Test status
Simulation time 22580784597 ps
CPU time 355.11 seconds
Started Jan 03 02:10:32 PM PST 24
Finished Jan 03 02:16:41 PM PST 24
Peak memory 555244 kb
Host smart-b7e6faec-9fd7-4bde-aa12-94a7891f0eb2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360836330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_
device_slow_rsp.3360836330
Directory /workspace/51.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.170152980
Short name T1138
Test name
Test status
Simulation time 1405984100 ps
CPU time 53.66 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:11:53 PM PST 24
Peak memory 553908 kb
Host smart-c3b23848-e684-42bf-9843-309f66224e1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170152980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_addr
.170152980
Directory /workspace/51.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_error_random.3254390285
Short name T595
Test name
Test status
Simulation time 480588697 ps
CPU time 47.04 seconds
Started Jan 03 02:10:38 PM PST 24
Finished Jan 03 02:11:38 PM PST 24
Peak memory 553816 kb
Host smart-bdd44163-8f21-4728-a4eb-3b07926a53fb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254390285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.3254390285
Directory /workspace/51.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random.4022876419
Short name T104
Test name
Test status
Simulation time 808866324 ps
CPU time 33.2 seconds
Started Jan 03 02:10:16 PM PST 24
Finished Jan 03 02:11:03 PM PST 24
Peak memory 554184 kb
Host smart-9cb6c347-27f5-47d3-a20c-82fde99a5317
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022876419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.4022876419
Directory /workspace/51.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.3761560067
Short name T473
Test name
Test status
Simulation time 95506626841 ps
CPU time 1081.9 seconds
Started Jan 03 02:10:31 PM PST 24
Finished Jan 03 02:28:47 PM PST 24
Peak memory 554228 kb
Host smart-b148147e-aaf9-47a7-b99b-7c7bd6e254b1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761560067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.3761560067
Directory /workspace/51.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.1461061617
Short name T1229
Test name
Test status
Simulation time 33865633035 ps
CPU time 568.32 seconds
Started Jan 03 02:09:58 PM PST 24
Finished Jan 03 02:19:33 PM PST 24
Peak memory 554220 kb
Host smart-89cd9b6b-e8ea-4d5a-b7b1-8a0b8653fbde
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461061617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.1461061617
Directory /workspace/51.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.2801053359
Short name T1307
Test name
Test status
Simulation time 524478558 ps
CPU time 50.35 seconds
Started Jan 03 02:10:43 PM PST 24
Finished Jan 03 02:11:52 PM PST 24
Peak memory 554096 kb
Host smart-2e68640d-5174-4731-a171-31037510d4ef
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801053359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del
ays.2801053359
Directory /workspace/51.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_same_source.3710107676
Short name T1134
Test name
Test status
Simulation time 2683738085 ps
CPU time 71.71 seconds
Started Jan 03 02:10:13 PM PST 24
Finished Jan 03 02:11:40 PM PST 24
Peak memory 554248 kb
Host smart-64cca04f-2927-43cb-9652-ba25c902bc5a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710107676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.3710107676
Directory /workspace/51.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke.2971176068
Short name T526
Test name
Test status
Simulation time 131334390 ps
CPU time 7.15 seconds
Started Jan 03 02:10:40 PM PST 24
Finished Jan 03 02:11:04 PM PST 24
Peak memory 551804 kb
Host smart-0711d878-a5c1-49b3-9fc4-c05c9b8b8620
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971176068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.2971176068
Directory /workspace/51.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.2321900449
Short name T1161
Test name
Test status
Simulation time 8416532802 ps
CPU time 84.58 seconds
Started Jan 03 02:09:59 PM PST 24
Finished Jan 03 02:11:31 PM PST 24
Peak memory 552112 kb
Host smart-74d3a320-489e-497e-a8cd-f02c3e5e02e4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321900449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.2321900449
Directory /workspace/51.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1911298487
Short name T1781
Test name
Test status
Simulation time 5986349099 ps
CPU time 105.75 seconds
Started Jan 03 02:10:33 PM PST 24
Finished Jan 03 02:12:31 PM PST 24
Peak memory 552132 kb
Host smart-fad14223-4692-4dda-b964-c48d39492e8a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911298487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.1911298487
Directory /workspace/51.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.2951382349
Short name T369
Test name
Test status
Simulation time 46971603 ps
CPU time 5.94 seconds
Started Jan 03 02:10:01 PM PST 24
Finished Jan 03 02:10:19 PM PST 24
Peak memory 552156 kb
Host smart-e71ec4a0-ee56-4941-aea3-ddd324fdeed6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951382349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay
s.2951382349
Directory /workspace/51.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all.79192134
Short name T122
Test name
Test status
Simulation time 4252746834 ps
CPU time 347.66 seconds
Started Jan 03 02:10:38 PM PST 24
Finished Jan 03 02:16:39 PM PST 24
Peak memory 555780 kb
Host smart-c4a77a0f-f29d-4038-800d-b233ad8e87af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79192134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.79192134
Directory /workspace/51.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.1165374240
Short name T309
Test name
Test status
Simulation time 14936208862 ps
CPU time 458.06 seconds
Started Jan 03 02:10:43 PM PST 24
Finished Jan 03 02:18:40 PM PST 24
Peak memory 555112 kb
Host smart-7193af53-c44d-4e8b-9cac-a366a795d301
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165374240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.1165374240
Directory /workspace/51.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2572988010
Short name T784
Test name
Test status
Simulation time 1218632378 ps
CPU time 157.99 seconds
Started Jan 03 02:10:45 PM PST 24
Finished Jan 03 02:13:45 PM PST 24
Peak memory 555072 kb
Host smart-e97cb76a-271b-48d2-9100-f5ae210878f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572988010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all
_with_rand_reset.2572988010
Directory /workspace/51.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.2855648114
Short name T1684
Test name
Test status
Simulation time 366577304 ps
CPU time 79.8 seconds
Started Jan 03 02:10:48 PM PST 24
Finished Jan 03 02:12:31 PM PST 24
Peak memory 555312 kb
Host smart-796465d8-4fb3-48cb-a841-762e875bad5a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855648114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al
l_with_reset_error.2855648114
Directory /workspace/51.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2151239977
Short name T386
Test name
Test status
Simulation time 298285739 ps
CPU time 16.1 seconds
Started Jan 03 02:10:47 PM PST 24
Finished Jan 03 02:11:26 PM PST 24
Peak memory 554180 kb
Host smart-1c45a99f-b495-4a63-bb59-e6a7191b0eee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151239977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.2151239977
Directory /workspace/51.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_access_same_device.2927573350
Short name T1530
Test name
Test status
Simulation time 995956807 ps
CPU time 73.61 seconds
Started Jan 03 02:10:29 PM PST 24
Finished Jan 03 02:11:57 PM PST 24
Peak memory 553920 kb
Host smart-3c8ffb61-1718-45b0-bda0-179508237011
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927573350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device
.2927573350
Directory /workspace/52.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.1231670598
Short name T304
Test name
Test status
Simulation time 62249185677 ps
CPU time 1082.71 seconds
Started Jan 03 02:10:12 PM PST 24
Finished Jan 03 02:28:31 PM PST 24
Peak memory 553992 kb
Host smart-3f8142e2-e835-4d1a-9d5d-a55a96931776
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231670598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_
device_slow_rsp.1231670598
Directory /workspace/52.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.3935304810
Short name T1628
Test name
Test status
Simulation time 172179623 ps
CPU time 9.03 seconds
Started Jan 03 02:10:22 PM PST 24
Finished Jan 03 02:10:46 PM PST 24
Peak memory 552080 kb
Host smart-7bfba92c-c0ca-4736-8400-435d0816560a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935304810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add
r.3935304810
Directory /workspace/52.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_error_random.3901684932
Short name T511
Test name
Test status
Simulation time 435106339 ps
CPU time 16.07 seconds
Started Jan 03 02:10:13 PM PST 24
Finished Jan 03 02:10:45 PM PST 24
Peak memory 554128 kb
Host smart-a0ccccf3-60fd-4877-b2c6-f7d6dab9572a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901684932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.3901684932
Directory /workspace/52.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random.830865893
Short name T406
Test name
Test status
Simulation time 774567676 ps
CPU time 30.21 seconds
Started Jan 03 02:10:04 PM PST 24
Finished Jan 03 02:10:52 PM PST 24
Peak memory 553832 kb
Host smart-943bbab8-a205-4eff-9dca-eb44aaad7140
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830865893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.830865893
Directory /workspace/52.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.957319538
Short name T99
Test name
Test status
Simulation time 95050193961 ps
CPU time 991.69 seconds
Started Jan 03 02:10:30 PM PST 24
Finished Jan 03 02:27:16 PM PST 24
Peak memory 554284 kb
Host smart-4ecef674-e5e7-47aa-8383-deda295a10aa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957319538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.957319538
Directory /workspace/52.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.3806847764
Short name T485
Test name
Test status
Simulation time 43848221110 ps
CPU time 690.91 seconds
Started Jan 03 02:10:34 PM PST 24
Finished Jan 03 02:22:17 PM PST 24
Peak memory 554272 kb
Host smart-17083305-ec13-4a08-8ea4-95b176736c98
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806847764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.3806847764
Directory /workspace/52.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.1942812068
Short name T980
Test name
Test status
Simulation time 39563529 ps
CPU time 6.3 seconds
Started Jan 03 02:10:30 PM PST 24
Finished Jan 03 02:10:50 PM PST 24
Peak memory 551712 kb
Host smart-5dc715d1-08a3-4ddb-80b3-c5da0daeb9e5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942812068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del
ays.1942812068
Directory /workspace/52.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_same_source.1756613599
Short name T1245
Test name
Test status
Simulation time 442215079 ps
CPU time 33.65 seconds
Started Jan 03 02:10:02 PM PST 24
Finished Jan 03 02:10:52 PM PST 24
Peak memory 554192 kb
Host smart-516224f8-2af2-4814-ae29-584303470129
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756613599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.1756613599
Directory /workspace/52.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke.1715414007
Short name T489
Test name
Test status
Simulation time 183602128 ps
CPU time 8.51 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:11:02 PM PST 24
Peak memory 552092 kb
Host smart-7c42bb11-ab9f-4adc-8e1e-21ef07cd5220
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715414007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.1715414007
Directory /workspace/52.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.1118681138
Short name T1920
Test name
Test status
Simulation time 5701010318 ps
CPU time 54.71 seconds
Started Jan 03 02:10:49 PM PST 24
Finished Jan 03 02:12:07 PM PST 24
Peak memory 552124 kb
Host smart-f1594d1c-9e84-4f4a-8bfb-c9c667494ef7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118681138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.1118681138
Directory /workspace/52.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3278610816
Short name T1392
Test name
Test status
Simulation time 6254533357 ps
CPU time 108.39 seconds
Started Jan 03 02:10:02 PM PST 24
Finished Jan 03 02:12:07 PM PST 24
Peak memory 551892 kb
Host smart-5b9e3d04-31cb-48e3-8595-1c1b057571a0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278610816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.3278610816
Directory /workspace/52.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1049823685
Short name T66
Test name
Test status
Simulation time 45668132 ps
CPU time 6.18 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:11:06 PM PST 24
Peak memory 552080 kb
Host smart-0cb2fdca-6e05-44d0-8961-f3e87adec737
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049823685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay
s.1049823685
Directory /workspace/52.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all.2603086486
Short name T1391
Test name
Test status
Simulation time 5333519830 ps
CPU time 205.11 seconds
Started Jan 03 02:10:11 PM PST 24
Finished Jan 03 02:13:54 PM PST 24
Peak memory 555064 kb
Host smart-43db5fb1-3596-4bee-8542-b8380910395d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603086486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.2603086486
Directory /workspace/52.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.1712388345
Short name T811
Test name
Test status
Simulation time 10723761586 ps
CPU time 359.2 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:17:16 PM PST 24
Peak memory 555212 kb
Host smart-77e6fc2d-64c7-41b9-9637-75db856c7461
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712388345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.1712388345
Directory /workspace/52.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3420156776
Short name T1034
Test name
Test status
Simulation time 13549358435 ps
CPU time 715.24 seconds
Started Jan 03 02:10:38 PM PST 24
Finished Jan 03 02:22:47 PM PST 24
Peak memory 559120 kb
Host smart-61f44800-175a-4782-80ef-9af60ba4e357
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420156776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all
_with_rand_reset.3420156776
Directory /workspace/52.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.4061697352
Short name T1006
Test name
Test status
Simulation time 294621285 ps
CPU time 74.49 seconds
Started Jan 03 02:10:29 PM PST 24
Finished Jan 03 02:11:58 PM PST 24
Peak memory 555044 kb
Host smart-49c2833c-d985-4ef9-b360-1ea51fc21784
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061697352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al
l_with_reset_error.4061697352
Directory /workspace/52.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.1847140114
Short name T1685
Test name
Test status
Simulation time 257469491 ps
CPU time 13.39 seconds
Started Jan 03 02:10:23 PM PST 24
Finished Jan 03 02:10:51 PM PST 24
Peak memory 553744 kb
Host smart-0ba1b17d-4365-4661-94d9-63c0192d8375
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847140114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.1847140114
Directory /workspace/52.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_access_same_device.2831587981
Short name T979
Test name
Test status
Simulation time 770256976 ps
CPU time 61.28 seconds
Started Jan 03 02:09:57 PM PST 24
Finished Jan 03 02:11:04 PM PST 24
Peak memory 553992 kb
Host smart-ed3474df-9dce-490d-9273-add5ee647a1e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831587981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device
.2831587981
Directory /workspace/53.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3292047669
Short name T876
Test name
Test status
Simulation time 11625387363 ps
CPU time 178.13 seconds
Started Jan 03 02:10:31 PM PST 24
Finished Jan 03 02:13:42 PM PST 24
Peak memory 553264 kb
Host smart-043d9cc2-c1d1-472d-9fe8-64fcd3972318
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292047669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_
device_slow_rsp.3292047669
Directory /workspace/53.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1716819150
Short name T1018
Test name
Test status
Simulation time 230560459 ps
CPU time 11.52 seconds
Started Jan 03 02:10:37 PM PST 24
Finished Jan 03 02:11:02 PM PST 24
Peak memory 553156 kb
Host smart-55a32e85-9cd7-4e8d-91dd-e8ee78ea1512
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716819150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add
r.1716819150
Directory /workspace/53.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_error_random.11745335
Short name T1365
Test name
Test status
Simulation time 651403154 ps
CPU time 25.7 seconds
Started Jan 03 02:10:53 PM PST 24
Finished Jan 03 02:11:41 PM PST 24
Peak memory 552840 kb
Host smart-ec2f8b82-0aa9-4210-b1fb-e8a183c7ea65
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11745335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.11745335
Directory /workspace/53.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random.977241767
Short name T727
Test name
Test status
Simulation time 435479635 ps
CPU time 17.23 seconds
Started Jan 03 02:10:37 PM PST 24
Finished Jan 03 02:11:07 PM PST 24
Peak memory 554112 kb
Host smart-4332dba7-3d3a-4c62-bc9e-c382032e2d60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977241767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.977241767
Directory /workspace/53.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.3705598604
Short name T695
Test name
Test status
Simulation time 74630356343 ps
CPU time 802.28 seconds
Started Jan 03 02:10:35 PM PST 24
Finished Jan 03 02:24:10 PM PST 24
Peak memory 554032 kb
Host smart-b137f1cf-aa35-4f35-8be1-27bfa13c6836
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705598604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.3705598604
Directory /workspace/53.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.2213384939
Short name T182
Test name
Test status
Simulation time 68588050369 ps
CPU time 1186.65 seconds
Started Jan 03 02:10:04 PM PST 24
Finished Jan 03 02:30:08 PM PST 24
Peak memory 553984 kb
Host smart-3ae52acf-2c3a-4e2d-b63a-dd90917e26e3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213384939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.2213384939
Directory /workspace/53.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.2511500951
Short name T194
Test name
Test status
Simulation time 418463701 ps
CPU time 37.12 seconds
Started Jan 03 02:10:16 PM PST 24
Finished Jan 03 02:11:08 PM PST 24
Peak memory 553896 kb
Host smart-403b798e-0877-417b-8106-557aa84bbd3c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511500951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del
ays.2511500951
Directory /workspace/53.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_same_source.3265189915
Short name T580
Test name
Test status
Simulation time 1670800764 ps
CPU time 47.41 seconds
Started Jan 03 02:10:33 PM PST 24
Finished Jan 03 02:11:34 PM PST 24
Peak memory 554152 kb
Host smart-ff741cbb-c2d4-4582-ae46-c59c8324e962
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265189915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.3265189915
Directory /workspace/53.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke.1337558248
Short name T693
Test name
Test status
Simulation time 212718971 ps
CPU time 10.15 seconds
Started Jan 03 02:10:33 PM PST 24
Finished Jan 03 02:10:56 PM PST 24
Peak memory 551640 kb
Host smart-16c657ee-7ad1-43f0-b22f-28fe1843dbb1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337558248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.1337558248
Directory /workspace/53.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.1619792682
Short name T715
Test name
Test status
Simulation time 5158340831 ps
CPU time 56.54 seconds
Started Jan 03 02:10:28 PM PST 24
Finished Jan 03 02:11:39 PM PST 24
Peak memory 552076 kb
Host smart-455bd65e-086c-4471-8f25-3620a4c22018
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619792682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.1619792682
Directory /workspace/53.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.149094463
Short name T549
Test name
Test status
Simulation time 2779900307 ps
CPU time 47.22 seconds
Started Jan 03 02:10:02 PM PST 24
Finished Jan 03 02:11:04 PM PST 24
Peak memory 552056 kb
Host smart-df096254-8753-440a-bf48-6201e3ca1dba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149094463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.149094463
Directory /workspace/53.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.262767561
Short name T1531
Test name
Test status
Simulation time 40987395 ps
CPU time 5.74 seconds
Started Jan 03 02:10:11 PM PST 24
Finished Jan 03 02:10:34 PM PST 24
Peak memory 551748 kb
Host smart-b79a3495-45ce-4b4d-81ba-d57d7207140f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262767561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays
.262767561
Directory /workspace/53.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all.3562267580
Short name T1756
Test name
Test status
Simulation time 1733681051 ps
CPU time 157.79 seconds
Started Jan 03 02:10:22 PM PST 24
Finished Jan 03 02:13:15 PM PST 24
Peak memory 555328 kb
Host smart-10ccb166-b50f-4732-9244-57f9eda98d58
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562267580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.3562267580
Directory /workspace/53.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.2878292475
Short name T1200
Test name
Test status
Simulation time 3410172164 ps
CPU time 269.75 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:15:30 PM PST 24
Peak memory 555160 kb
Host smart-f714e86b-975b-415e-a563-2a72510825c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878292475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.2878292475
Directory /workspace/53.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1875118306
Short name T1351
Test name
Test status
Simulation time 323959789 ps
CPU time 112.31 seconds
Started Jan 03 02:10:18 PM PST 24
Finished Jan 03 02:12:23 PM PST 24
Peak memory 556092 kb
Host smart-119e8210-72f6-4cca-8fdb-edbbf958bc25
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875118306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all
_with_rand_reset.1875118306
Directory /workspace/53.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1332932381
Short name T1692
Test name
Test status
Simulation time 4816889209 ps
CPU time 239.18 seconds
Started Jan 03 02:10:36 PM PST 24
Finished Jan 03 02:14:48 PM PST 24
Peak memory 556936 kb
Host smart-5de78182-1671-48b3-8358-25769d5c6395
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332932381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al
l_with_reset_error.1332932381
Directory /workspace/53.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2689929148
Short name T642
Test name
Test status
Simulation time 206896978 ps
CPU time 25.09 seconds
Started Jan 03 02:10:15 PM PST 24
Finished Jan 03 02:10:55 PM PST 24
Peak memory 554200 kb
Host smart-592141d1-3760-4c06-9461-0b0fd7e37d7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689929148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.2689929148
Directory /workspace/53.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_access_same_device.1949157848
Short name T619
Test name
Test status
Simulation time 1010739472 ps
CPU time 73.96 seconds
Started Jan 03 02:10:37 PM PST 24
Finished Jan 03 02:12:04 PM PST 24
Peak memory 553976 kb
Host smart-d6324553-be0a-40ca-a1c5-0539c1c66a8f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949157848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device
.1949157848
Directory /workspace/54.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2431911195
Short name T746
Test name
Test status
Simulation time 29783100426 ps
CPU time 509.4 seconds
Started Jan 03 02:10:46 PM PST 24
Finished Jan 03 02:19:38 PM PST 24
Peak memory 554040 kb
Host smart-020a5427-01a2-4e94-a9b1-e9a11685a439
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431911195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_
device_slow_rsp.2431911195
Directory /workspace/54.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.602682522
Short name T1139
Test name
Test status
Simulation time 138294517 ps
CPU time 8.74 seconds
Started Jan 03 02:10:31 PM PST 24
Finished Jan 03 02:10:53 PM PST 24
Peak memory 551796 kb
Host smart-7af6b21b-5084-461c-9fe0-776ef8b96282
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602682522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr
.602682522
Directory /workspace/54.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_error_random.2152187845
Short name T920
Test name
Test status
Simulation time 757829165 ps
CPU time 28.08 seconds
Started Jan 03 02:10:03 PM PST 24
Finished Jan 03 02:10:49 PM PST 24
Peak memory 553896 kb
Host smart-d5b2e774-4cf6-42e5-96b6-2141db622bbe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152187845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.2152187845
Directory /workspace/54.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random.3996141369
Short name T1078
Test name
Test status
Simulation time 217401469 ps
CPU time 10.26 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:11:04 PM PST 24
Peak memory 551828 kb
Host smart-30437d4a-0e2a-48d5-984c-1229417e7d5b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996141369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.3996141369
Directory /workspace/54.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2299034303
Short name T1666
Test name
Test status
Simulation time 32294714068 ps
CPU time 355.02 seconds
Started Jan 03 02:10:10 PM PST 24
Finished Jan 03 02:16:23 PM PST 24
Peak memory 553120 kb
Host smart-10c39a53-f0d6-44cf-a9a3-b6fdb7df6689
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299034303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2299034303
Directory /workspace/54.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.2797797306
Short name T687
Test name
Test status
Simulation time 52245313241 ps
CPU time 835.57 seconds
Started Jan 03 02:10:04 PM PST 24
Finished Jan 03 02:24:17 PM PST 24
Peak memory 553988 kb
Host smart-92e96e60-c5bd-4598-8b22-9382f8278a3d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797797306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.2797797306
Directory /workspace/54.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.3022404213
Short name T1880
Test name
Test status
Simulation time 107304163 ps
CPU time 10.81 seconds
Started Jan 03 02:10:48 PM PST 24
Finished Jan 03 02:11:21 PM PST 24
Peak memory 554172 kb
Host smart-107f167c-899c-46dc-a56c-66af5009bcbb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022404213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del
ays.3022404213
Directory /workspace/54.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_same_source.128120943
Short name T704
Test name
Test status
Simulation time 536662568 ps
CPU time 40.8 seconds
Started Jan 03 02:10:00 PM PST 24
Finished Jan 03 02:10:53 PM PST 24
Peak memory 554008 kb
Host smart-d154d592-b497-4a32-9303-8c7e8c80d54b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128120943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.128120943
Directory /workspace/54.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke.2522005603
Short name T933
Test name
Test status
Simulation time 37305756 ps
CPU time 5.23 seconds
Started Jan 03 02:10:46 PM PST 24
Finished Jan 03 02:11:14 PM PST 24
Peak memory 552128 kb
Host smart-d7552852-a32f-4fee-ae03-7e7eda96aeef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522005603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.2522005603
Directory /workspace/54.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.879432340
Short name T713
Test name
Test status
Simulation time 5510429569 ps
CPU time 57.9 seconds
Started Jan 03 02:10:48 PM PST 24
Finished Jan 03 02:12:09 PM PST 24
Peak memory 551848 kb
Host smart-17286816-8da1-4e30-84cd-cbaee0bf88a3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879432340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.879432340
Directory /workspace/54.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.2094826174
Short name T960
Test name
Test status
Simulation time 5580018423 ps
CPU time 100.92 seconds
Started Jan 03 02:10:02 PM PST 24
Finished Jan 03 02:12:00 PM PST 24
Peak memory 551656 kb
Host smart-9ce3013e-12b2-418b-a48c-cfa6353f5818
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094826174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.2094826174
Directory /workspace/54.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1422834576
Short name T385
Test name
Test status
Simulation time 56814183 ps
CPU time 6.56 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:11:06 PM PST 24
Peak memory 552012 kb
Host smart-d50259ff-4542-45d2-8930-156607598cea
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422834576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay
s.1422834576
Directory /workspace/54.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all.1876650108
Short name T116
Test name
Test status
Simulation time 999724678 ps
CPU time 90.03 seconds
Started Jan 03 02:10:02 PM PST 24
Finished Jan 03 02:11:49 PM PST 24
Peak memory 554012 kb
Host smart-738d7e20-0600-4268-a60f-c8a24431d7d4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876650108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.1876650108
Directory /workspace/54.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.840083683
Short name T1636
Test name
Test status
Simulation time 280521294 ps
CPU time 100.16 seconds
Started Jan 03 02:10:18 PM PST 24
Finished Jan 03 02:12:11 PM PST 24
Peak memory 555416 kb
Host smart-72315510-72e3-4843-a6b9-c57cd9f3279c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840083683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_
with_rand_reset.840083683
Directory /workspace/54.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.65136575
Short name T353
Test name
Test status
Simulation time 3328006354 ps
CPU time 354.03 seconds
Started Jan 03 02:10:43 PM PST 24
Finished Jan 03 02:16:55 PM PST 24
Peak memory 559096 kb
Host smart-76f445f5-04ac-4ca0-a0ab-c7de3694d8ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65136575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_
with_reset_error.65136575
Directory /workspace/54.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.1870897651
Short name T189
Test name
Test status
Simulation time 299607825 ps
CPU time 32.72 seconds
Started Jan 03 02:10:23 PM PST 24
Finished Jan 03 02:11:11 PM PST 24
Peak memory 554068 kb
Host smart-32ce6e2e-3392-4f8e-b08c-cf99086b9b50
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870897651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.1870897651
Directory /workspace/54.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_access_same_device.1081443971
Short name T1339
Test name
Test status
Simulation time 638278704 ps
CPU time 60.91 seconds
Started Jan 03 02:10:49 PM PST 24
Finished Jan 03 02:12:12 PM PST 24
Peak memory 553928 kb
Host smart-38b2a7a9-6ecc-4c31-b054-e92e491a7484
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081443971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device
.1081443971
Directory /workspace/55.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.144717651
Short name T812
Test name
Test status
Simulation time 111943455835 ps
CPU time 1688.75 seconds
Started Jan 03 02:10:46 PM PST 24
Finished Jan 03 02:39:17 PM PST 24
Peak memory 554020 kb
Host smart-a38984ce-2ba0-489a-9e98-d3f14f0307f5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144717651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_d
evice_slow_rsp.144717651
Directory /workspace/55.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.2502916731
Short name T633
Test name
Test status
Simulation time 340149093 ps
CPU time 16.12 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:11:10 PM PST 24
Peak memory 553880 kb
Host smart-d4ca2209-6797-4bed-b218-2a0a86686c82
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502916731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add
r.2502916731
Directory /workspace/55.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_error_random.1457853861
Short name T686
Test name
Test status
Simulation time 178604962 ps
CPU time 15.33 seconds
Started Jan 03 02:10:37 PM PST 24
Finished Jan 03 02:11:05 PM PST 24
Peak memory 554120 kb
Host smart-2ec718ae-1241-4339-9a99-e1a10f9b415b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457853861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.1457853861
Directory /workspace/55.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random.4208938284
Short name T1489
Test name
Test status
Simulation time 249397429 ps
CPU time 23.1 seconds
Started Jan 03 02:10:08 PM PST 24
Finished Jan 03 02:10:51 PM PST 24
Peak memory 553856 kb
Host smart-93e71a98-5771-432d-b1fe-9c6da1a9db23
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208938284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.4208938284
Directory /workspace/55.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.726438940
Short name T624
Test name
Test status
Simulation time 110715788978 ps
CPU time 1006.08 seconds
Started Jan 03 02:10:38 PM PST 24
Finished Jan 03 02:27:38 PM PST 24
Peak memory 553872 kb
Host smart-5fd76280-8f22-409f-ba40-389d8b99b0fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726438940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.726438940
Directory /workspace/55.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.1156599154
Short name T1755
Test name
Test status
Simulation time 3418075435 ps
CPU time 58.94 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:11:58 PM PST 24
Peak memory 552172 kb
Host smart-3130e1b2-cc4b-4bef-b4cb-5573037a3f64
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156599154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.1156599154
Directory /workspace/55.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.3687287665
Short name T1011
Test name
Test status
Simulation time 609254313 ps
CPU time 54.75 seconds
Started Jan 03 02:10:35 PM PST 24
Finished Jan 03 02:11:42 PM PST 24
Peak memory 554100 kb
Host smart-60429618-9b94-4261-984a-f61e767e3e32
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687287665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del
ays.3687287665
Directory /workspace/55.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_same_source.3167278786
Short name T1267
Test name
Test status
Simulation time 103072211 ps
CPU time 9.97 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:11:27 PM PST 24
Peak memory 554172 kb
Host smart-390ad982-8403-4396-b2b2-08d9bdeb79c4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167278786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.3167278786
Directory /workspace/55.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke.2811520753
Short name T822
Test name
Test status
Simulation time 186419206 ps
CPU time 8.37 seconds
Started Jan 03 02:10:12 PM PST 24
Finished Jan 03 02:10:37 PM PST 24
Peak memory 552088 kb
Host smart-2e2e65d7-0cc7-4e69-85f8-cd28186f2899
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811520753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.2811520753
Directory /workspace/55.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.1208816469
Short name T235
Test name
Test status
Simulation time 8480451940 ps
CPU time 87.33 seconds
Started Jan 03 02:10:17 PM PST 24
Finished Jan 03 02:11:58 PM PST 24
Peak memory 551860 kb
Host smart-912398e8-bb5b-4885-b6b8-0641d5f0de05
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208816469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.1208816469
Directory /workspace/55.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.2528514789
Short name T689
Test name
Test status
Simulation time 5943855126 ps
CPU time 104.17 seconds
Started Jan 03 02:10:46 PM PST 24
Finished Jan 03 02:12:52 PM PST 24
Peak memory 551836 kb
Host smart-887f273c-b6c4-4487-81df-b77cd553890f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528514789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.2528514789
Directory /workspace/55.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2191547049
Short name T1768
Test name
Test status
Simulation time 52615377 ps
CPU time 6.24 seconds
Started Jan 03 02:10:11 PM PST 24
Finished Jan 03 02:10:35 PM PST 24
Peak memory 551996 kb
Host smart-c9d38e90-a71f-4e2b-b0f9-51f56b2f3433
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191547049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay
s.2191547049
Directory /workspace/55.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all.3834337594
Short name T998
Test name
Test status
Simulation time 9559777047 ps
CPU time 364.67 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:16:59 PM PST 24
Peak memory 555300 kb
Host smart-cd84d027-308e-4fb7-b13c-cb590b488404
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834337594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3834337594
Directory /workspace/55.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.4212372227
Short name T1273
Test name
Test status
Simulation time 4014525760 ps
CPU time 143.41 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:13:23 PM PST 24
Peak memory 555120 kb
Host smart-b45f188b-0b51-40dd-8738-3af05a94fbec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212372227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.4212372227
Directory /workspace/55.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.408574279
Short name T1841
Test name
Test status
Simulation time 199650464 ps
CPU time 86.3 seconds
Started Jan 03 02:10:53 PM PST 24
Finished Jan 03 02:12:42 PM PST 24
Peak memory 555336 kb
Host smart-c0b4f5ed-5f70-42ba-9755-b7e970d66121
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408574279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_
with_rand_reset.408574279
Directory /workspace/55.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.4285778711
Short name T205
Test name
Test status
Simulation time 4726841660 ps
CPU time 211.01 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:14:31 PM PST 24
Peak memory 557520 kb
Host smart-76f37585-7807-4e0c-a1b9-2182ca992640
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285778711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al
l_with_reset_error.4285778711
Directory /workspace/55.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.3062058448
Short name T1663
Test name
Test status
Simulation time 1280841051 ps
CPU time 54.15 seconds
Started Jan 03 02:10:43 PM PST 24
Finished Jan 03 02:11:57 PM PST 24
Peak memory 553916 kb
Host smart-15493f06-5aff-41e1-9f9a-31124fe82206
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062058448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3062058448
Directory /workspace/55.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_access_same_device.3584833908
Short name T409
Test name
Test status
Simulation time 559254110 ps
CPU time 45.63 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:12:02 PM PST 24
Peak memory 553884 kb
Host smart-e778fcbf-120e-4a6f-ba39-eb074701dd60
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584833908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device
.3584833908
Directory /workspace/56.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3307593638
Short name T733
Test name
Test status
Simulation time 32344424422 ps
CPU time 527.67 seconds
Started Jan 03 02:10:40 PM PST 24
Finished Jan 03 02:19:44 PM PST 24
Peak memory 554016 kb
Host smart-15ddf3e4-df2d-4723-8085-b08450e5ba23
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307593638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_
device_slow_rsp.3307593638
Directory /workspace/56.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2581195966
Short name T1702
Test name
Test status
Simulation time 740753707 ps
CPU time 30.67 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:11:55 PM PST 24
Peak memory 553876 kb
Host smart-1c2cef00-3004-48c3-a8a2-45fea1984f77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581195966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add
r.2581195966
Directory /workspace/56.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_error_random.2941400463
Short name T1049
Test name
Test status
Simulation time 598294402 ps
CPU time 42.98 seconds
Started Jan 03 02:10:46 PM PST 24
Finished Jan 03 02:11:52 PM PST 24
Peak memory 554080 kb
Host smart-038da2e6-ed7d-498b-a296-43762f66bcab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941400463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.2941400463
Directory /workspace/56.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random.4067413337
Short name T190
Test name
Test status
Simulation time 1566030949 ps
CPU time 55.07 seconds
Started Jan 03 02:10:45 PM PST 24
Finished Jan 03 02:12:03 PM PST 24
Peak memory 554172 kb
Host smart-a9ef0c73-aa39-443a-9b0d-379b81e4bcbd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067413337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.4067413337
Directory /workspace/56.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1002776410
Short name T1879
Test name
Test status
Simulation time 7551130143 ps
CPU time 81.14 seconds
Started Jan 03 02:10:49 PM PST 24
Finished Jan 03 02:12:33 PM PST 24
Peak memory 552176 kb
Host smart-f0ec4751-e84a-4073-8cde-265d563f6d5d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002776410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1002776410
Directory /workspace/56.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.152712948
Short name T838
Test name
Test status
Simulation time 14339969600 ps
CPU time 249.74 seconds
Started Jan 03 02:10:40 PM PST 24
Finished Jan 03 02:15:05 PM PST 24
Peak memory 554292 kb
Host smart-c113f3de-2c05-473a-a039-7d7470693f13
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152712948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.152712948
Directory /workspace/56.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.2118979828
Short name T237
Test name
Test status
Simulation time 216771775 ps
CPU time 18.4 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:11:13 PM PST 24
Peak memory 554076 kb
Host smart-c3c05530-e532-4302-a2fb-406ff219a8ca
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118979828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del
ays.2118979828
Directory /workspace/56.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_same_source.12448294
Short name T1632
Test name
Test status
Simulation time 2134814396 ps
CPU time 58.67 seconds
Started Jan 03 02:10:47 PM PST 24
Finished Jan 03 02:12:09 PM PST 24
Peak memory 554188 kb
Host smart-71a829e7-ec4b-4a95-ad86-954af646c40c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12448294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.12448294
Directory /workspace/56.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke.3776732898
Short name T899
Test name
Test status
Simulation time 234491957 ps
CPU time 9.54 seconds
Started Jan 03 02:10:37 PM PST 24
Finished Jan 03 02:11:00 PM PST 24
Peak memory 552184 kb
Host smart-b885edfc-a1f5-401f-a077-69da34df2a87
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776732898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.3776732898
Directory /workspace/56.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.4184394714
Short name T1476
Test name
Test status
Simulation time 9121637402 ps
CPU time 99.49 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:12:39 PM PST 24
Peak memory 552176 kb
Host smart-336e1da5-676e-438b-8e4f-2a652e37dc77
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184394714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.4184394714
Directory /workspace/56.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2465344771
Short name T1775
Test name
Test status
Simulation time 5816378073 ps
CPU time 103.17 seconds
Started Jan 03 02:10:44 PM PST 24
Finished Jan 03 02:12:47 PM PST 24
Peak memory 552084 kb
Host smart-0e2c9406-7c13-42fa-ad99-6a307dd34f4f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465344771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.2465344771
Directory /workspace/56.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3226569841
Short name T1677
Test name
Test status
Simulation time 42380206 ps
CPU time 5.79 seconds
Started Jan 03 02:10:36 PM PST 24
Finished Jan 03 02:10:55 PM PST 24
Peak memory 551764 kb
Host smart-db2ceb92-055e-44c8-80cb-04f095f94512
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226569841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay
s.3226569841
Directory /workspace/56.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all.2295419879
Short name T1503
Test name
Test status
Simulation time 13205163940 ps
CPU time 414.45 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:18:18 PM PST 24
Peak memory 555376 kb
Host smart-8a32a33c-41b4-41f7-ab0b-cce13f0c768b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295419879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.2295419879
Directory /workspace/56.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.1597627950
Short name T673
Test name
Test status
Simulation time 2447557322 ps
CPU time 190.46 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:14:27 PM PST 24
Peak memory 555120 kb
Host smart-1e7d9f74-f665-4aed-8573-17c388cd09bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597627950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.1597627950
Directory /workspace/56.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.3810175062
Short name T1776
Test name
Test status
Simulation time 9865521393 ps
CPU time 335.18 seconds
Started Jan 03 02:10:49 PM PST 24
Finished Jan 03 02:16:47 PM PST 24
Peak memory 555996 kb
Host smart-74c4a5f7-4469-4da3-b894-9c0c71c50bb8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810175062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all
_with_rand_reset.3810175062
Directory /workspace/56.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1137010260
Short name T347
Test name
Test status
Simulation time 2531078614 ps
CPU time 207.66 seconds
Started Jan 03 02:10:58 PM PST 24
Finished Jan 03 02:14:48 PM PST 24
Peak memory 557328 kb
Host smart-f899d06b-0725-46d1-a7ef-080cc7900c08
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137010260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al
l_with_reset_error.1137010260
Directory /workspace/56.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.3741375248
Short name T401
Test name
Test status
Simulation time 55874567 ps
CPU time 8.63 seconds
Started Jan 03 02:10:47 PM PST 24
Finished Jan 03 02:11:19 PM PST 24
Peak memory 552064 kb
Host smart-ec8113f2-ad7d-4d9e-a9b6-d21a5bade915
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741375248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.3741375248
Directory /workspace/56.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_access_same_device.681106221
Short name T1587
Test name
Test status
Simulation time 769427127 ps
CPU time 31.55 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:11:56 PM PST 24
Peak memory 554200 kb
Host smart-a2d8b2e0-69e3-4f35-a7ed-0c6a57595291
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681106221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device.
681106221
Directory /workspace/57.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.1007766648
Short name T1712
Test name
Test status
Simulation time 103815585532 ps
CPU time 1563.45 seconds
Started Jan 03 02:11:03 PM PST 24
Finished Jan 03 02:37:28 PM PST 24
Peak memory 555000 kb
Host smart-796216c4-0b10-44e2-8f3c-19fc5511b9c9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007766648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_
device_slow_rsp.1007766648
Directory /workspace/57.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.99960724
Short name T1752
Test name
Test status
Simulation time 319360051 ps
CPU time 29.67 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:11:53 PM PST 24
Peak memory 553872 kb
Host smart-f0ebbb05-574b-498c-a2f7-afa13aa96b9c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99960724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_addr.99960724
Directory /workspace/57.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_error_random.2065804372
Short name T997
Test name
Test status
Simulation time 2014998799 ps
CPU time 65.96 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:12:30 PM PST 24
Peak memory 553888 kb
Host smart-de42331f-b73c-4685-8872-fcd53662908c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065804372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.2065804372
Directory /workspace/57.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random.300855440
Short name T1276
Test name
Test status
Simulation time 104051864 ps
CPU time 6.8 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:11:25 PM PST 24
Peak memory 552196 kb
Host smart-2d5aef06-3e22-45cb-b93d-42606c8d7aab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300855440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.300855440
Directory /workspace/57.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.1653424989
Short name T1153
Test name
Test status
Simulation time 7884707433 ps
CPU time 82.31 seconds
Started Jan 03 02:10:51 PM PST 24
Finished Jan 03 02:12:36 PM PST 24
Peak memory 551844 kb
Host smart-2561e116-8e42-4474-8c7f-29c3e1428647
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653424989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.1653424989
Directory /workspace/57.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.933454083
Short name T1540
Test name
Test status
Simulation time 12147347667 ps
CPU time 205.44 seconds
Started Jan 03 02:10:53 PM PST 24
Finished Jan 03 02:14:41 PM PST 24
Peak memory 553964 kb
Host smart-0e869147-1a7d-4817-983b-01d2683247df
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933454083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.933454083
Directory /workspace/57.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.2303469836
Short name T1525
Test name
Test status
Simulation time 76009059 ps
CPU time 8.98 seconds
Started Jan 03 02:10:40 PM PST 24
Finished Jan 03 02:11:05 PM PST 24
Peak memory 552896 kb
Host smart-9fd1b153-1fb9-4791-8151-b40c275aafed
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303469836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del
ays.2303469836
Directory /workspace/57.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_same_source.1459595685
Short name T223
Test name
Test status
Simulation time 1335504421 ps
CPU time 36.88 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:11:55 PM PST 24
Peak memory 554012 kb
Host smart-abcdce4b-b0a4-4ae1-b7ef-4716ac329bc7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459595685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.1459595685
Directory /workspace/57.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke.3044459518
Short name T1465
Test name
Test status
Simulation time 253121941 ps
CPU time 9.93 seconds
Started Jan 03 02:10:53 PM PST 24
Finished Jan 03 02:11:25 PM PST 24
Peak memory 552108 kb
Host smart-310dbc60-7196-4bf7-b4c4-d6b1f26bc054
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044459518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.3044459518
Directory /workspace/57.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.1630153742
Short name T1235
Test name
Test status
Simulation time 9016557007 ps
CPU time 92.56 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:12:51 PM PST 24
Peak memory 551844 kb
Host smart-9b795a10-49fb-4b46-b8ca-1c79977609b0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630153742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.1630153742
Directory /workspace/57.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2551451064
Short name T1820
Test name
Test status
Simulation time 6160873060 ps
CPU time 106 seconds
Started Jan 03 02:10:52 PM PST 24
Finished Jan 03 02:13:01 PM PST 24
Peak memory 551372 kb
Host smart-3696e14e-644a-45ff-bc79-f0580f064168
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551451064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.2551451064
Directory /workspace/57.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.1901100838
Short name T1046
Test name
Test status
Simulation time 53191801 ps
CPU time 6.23 seconds
Started Jan 03 02:10:51 PM PST 24
Finished Jan 03 02:11:20 PM PST 24
Peak memory 552120 kb
Host smart-7839fa62-2060-4582-b808-d9558a3ae2cd
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901100838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay
s.1901100838
Directory /workspace/57.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all.1238844586
Short name T246
Test name
Test status
Simulation time 6015509395 ps
CPU time 205.22 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:14:50 PM PST 24
Peak memory 554280 kb
Host smart-e51e521c-1980-4e91-82c3-daca7a0813ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238844586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.1238844586
Directory /workspace/57.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2707929836
Short name T239
Test name
Test status
Simulation time 7829907332 ps
CPU time 320 seconds
Started Jan 03 02:11:03 PM PST 24
Finished Jan 03 02:16:45 PM PST 24
Peak memory 556732 kb
Host smart-26cbaba0-3ff6-4e68-b156-2159a1969dcf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707929836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all
_with_rand_reset.2707929836
Directory /workspace/57.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.2130233190
Short name T1253
Test name
Test status
Simulation time 508417835 ps
CPU time 140.76 seconds
Started Jan 03 02:10:55 PM PST 24
Finished Jan 03 02:13:38 PM PST 24
Peak memory 557360 kb
Host smart-bcef1f2f-a575-474b-97f8-62f73279be9a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130233190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al
l_with_reset_error.2130233190
Directory /workspace/57.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.2411461686
Short name T901
Test name
Test status
Simulation time 310062907 ps
CPU time 34.72 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:11:58 PM PST 24
Peak memory 553944 kb
Host smart-8ed7c933-52bc-4687-9e17-563f48c91636
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411461686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.2411461686
Directory /workspace/57.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_access_same_device.2237375159
Short name T1672
Test name
Test status
Simulation time 823166603 ps
CPU time 30.53 seconds
Started Jan 03 02:10:59 PM PST 24
Finished Jan 03 02:11:51 PM PST 24
Peak memory 553940 kb
Host smart-f52add68-b840-4e8b-ad80-d2f7d54666b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237375159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device
.2237375159
Directory /workspace/58.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2191363048
Short name T1728
Test name
Test status
Simulation time 57324327246 ps
CPU time 994.45 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:27:53 PM PST 24
Peak memory 555272 kb
Host smart-0320f80b-92f2-421b-a94c-4409d793cc34
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191363048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_
device_slow_rsp.2191363048
Directory /workspace/58.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3473447424
Short name T448
Test name
Test status
Simulation time 131634430 ps
CPU time 14.78 seconds
Started Jan 03 02:10:58 PM PST 24
Finished Jan 03 02:11:35 PM PST 24
Peak memory 553860 kb
Host smart-a5f2bc03-bd7d-47a6-8e35-6bb1e8a26a85
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473447424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add
r.3473447424
Directory /workspace/58.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_error_random.2339306003
Short name T494
Test name
Test status
Simulation time 452042908 ps
CPU time 36.44 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:12:00 PM PST 24
Peak memory 554160 kb
Host smart-456446b6-a22c-44a3-a951-705889f0df97
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339306003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.2339306003
Directory /workspace/58.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random.4236293294
Short name T1695
Test name
Test status
Simulation time 452394875 ps
CPU time 34.19 seconds
Started Jan 03 02:10:58 PM PST 24
Finished Jan 03 02:11:54 PM PST 24
Peak memory 554156 kb
Host smart-0ef310b0-3920-4f7e-a1c3-052fb7fea07f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236293294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.4236293294
Directory /workspace/58.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.604218588
Short name T1379
Test name
Test status
Simulation time 31598333769 ps
CPU time 358.05 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:17:17 PM PST 24
Peak memory 554028 kb
Host smart-f4117339-0877-44c2-885c-b0e1781bd209
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604218588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.604218588
Directory /workspace/58.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.3720064548
Short name T904
Test name
Test status
Simulation time 16836047290 ps
CPU time 310.96 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:16:30 PM PST 24
Peak memory 554316 kb
Host smart-fc203ea2-b4db-41b0-9c3c-0bb6ee729b7e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720064548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.3720064548
Directory /workspace/58.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.3282295629
Short name T413
Test name
Test status
Simulation time 420344205 ps
CPU time 39.65 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:11:59 PM PST 24
Peak memory 554288 kb
Host smart-4bdebd3d-23ec-4299-ba2c-5229951700e6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282295629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del
ays.3282295629
Directory /workspace/58.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_same_source.4150412215
Short name T1885
Test name
Test status
Simulation time 1167548809 ps
CPU time 35.1 seconds
Started Jan 03 02:10:58 PM PST 24
Finished Jan 03 02:11:55 PM PST 24
Peak memory 553924 kb
Host smart-bc1deba9-1f26-4b85-8224-2a6f5ca93a43
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150412215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.4150412215
Directory /workspace/58.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke.3509605305
Short name T1133
Test name
Test status
Simulation time 264812291 ps
CPU time 9.9 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:11:27 PM PST 24
Peak memory 552128 kb
Host smart-c8fa5c54-18e1-46c5-8dbb-2e0d6d4fa044
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509605305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.3509605305
Directory /workspace/58.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.4284718869
Short name T1080
Test name
Test status
Simulation time 7880623679 ps
CPU time 80.4 seconds
Started Jan 03 02:11:03 PM PST 24
Finished Jan 03 02:12:45 PM PST 24
Peak memory 552092 kb
Host smart-53030e1e-c75b-47bf-96df-e7514367f482
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284718869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.4284718869
Directory /workspace/58.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2474658361
Short name T467
Test name
Test status
Simulation time 3772402534 ps
CPU time 66.26 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:12:23 PM PST 24
Peak memory 551844 kb
Host smart-c456b05e-842e-4906-92e8-e43b1e05fd73
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474658361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.2474658361
Directory /workspace/58.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.96399366
Short name T507
Test name
Test status
Simulation time 45077373 ps
CPU time 5.82 seconds
Started Jan 03 02:10:53 PM PST 24
Finished Jan 03 02:11:21 PM PST 24
Peak memory 551664 kb
Host smart-8965c262-3cf4-4d91-8861-e3a0afbc549a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96399366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delays.96399366
Directory /workspace/58.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all.4017697917
Short name T1449
Test name
Test status
Simulation time 12334972901 ps
CPU time 450.63 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:18:50 PM PST 24
Peak memory 554308 kb
Host smart-eda600b7-df70-42a3-946c-f28d483c78e2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017697917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.4017697917
Directory /workspace/58.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.2188695837
Short name T1027
Test name
Test status
Simulation time 7158618699 ps
CPU time 263.27 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:15:40 PM PST 24
Peak memory 556392 kb
Host smart-39e60067-7984-46f5-a4bd-3b8a1b32a071
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188695837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.2188695837
Directory /workspace/58.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.897665840
Short name T1439
Test name
Test status
Simulation time 520414618 ps
CPU time 213.94 seconds
Started Jan 03 02:11:19 PM PST 24
Finished Jan 03 02:15:07 PM PST 24
Peak memory 556400 kb
Host smart-ceb29f53-27e5-4c6c-8bff-be9a32eba94a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897665840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_
with_rand_reset.897665840
Directory /workspace/58.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.2267085175
Short name T1800
Test name
Test status
Simulation time 1272813209 ps
CPU time 63.67 seconds
Started Jan 03 02:11:00 PM PST 24
Finished Jan 03 02:12:26 PM PST 24
Peak memory 553984 kb
Host smart-138f764a-26af-43af-89ac-08a9fbfc8788
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267085175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2267085175
Directory /workspace/58.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_access_same_device.3145091975
Short name T1549
Test name
Test status
Simulation time 494958718 ps
CPU time 19.38 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:11:35 PM PST 24
Peak memory 553128 kb
Host smart-4ed0db9f-5030-4f78-83ba-2d5b40719fb5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145091975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device
.3145091975
Directory /workspace/59.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.870763846
Short name T1400
Test name
Test status
Simulation time 74183618358 ps
CPU time 1277.97 seconds
Started Jan 03 02:10:51 PM PST 24
Finished Jan 03 02:32:32 PM PST 24
Peak memory 553204 kb
Host smart-52cd712f-07fa-4c38-b188-22132267d27c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870763846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_d
evice_slow_rsp.870763846
Directory /workspace/59.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3937820656
Short name T1864
Test name
Test status
Simulation time 1017712432 ps
CPU time 42.96 seconds
Started Jan 03 02:10:49 PM PST 24
Finished Jan 03 02:11:55 PM PST 24
Peak memory 554160 kb
Host smart-0e8b7d5d-5c2e-4a10-9602-043e95faba81
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937820656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add
r.3937820656
Directory /workspace/59.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_error_random.576232250
Short name T1915
Test name
Test status
Simulation time 756707121 ps
CPU time 28.28 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:11:27 PM PST 24
Peak memory 554164 kb
Host smart-c81d9921-b394-4c6e-a7bc-3f53c5f6081c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576232250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.576232250
Directory /workspace/59.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random.2296652618
Short name T1816
Test name
Test status
Simulation time 319495479 ps
CPU time 26.59 seconds
Started Jan 03 02:10:41 PM PST 24
Finished Jan 03 02:11:24 PM PST 24
Peak memory 554160 kb
Host smart-b308e4df-09b6-49b4-95c5-b649c18bb376
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296652618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.2296652618
Directory /workspace/59.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.2464777621
Short name T1241
Test name
Test status
Simulation time 76866622976 ps
CPU time 860.89 seconds
Started Jan 03 02:10:46 PM PST 24
Finished Jan 03 02:25:29 PM PST 24
Peak memory 554216 kb
Host smart-1edd6c15-0b07-411b-b95f-9d5c9002c0dc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464777621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.2464777621
Directory /workspace/59.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.2140647562
Short name T1497
Test name
Test status
Simulation time 35552721482 ps
CPU time 574.36 seconds
Started Jan 03 02:10:53 PM PST 24
Finished Jan 03 02:20:50 PM PST 24
Peak memory 554136 kb
Host smart-be1aefec-d1cd-43a2-b6d3-0c38b6660dc6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140647562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.2140647562
Directory /workspace/59.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.1822502599
Short name T110
Test name
Test status
Simulation time 470637284 ps
CPU time 36.96 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:11:30 PM PST 24
Peak memory 554092 kb
Host smart-37eafee4-28c8-4f47-8175-01e7ac2d330e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822502599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del
ays.1822502599
Directory /workspace/59.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_same_source.4073418953
Short name T1403
Test name
Test status
Simulation time 540016444 ps
CPU time 34.63 seconds
Started Jan 03 02:10:50 PM PST 24
Finished Jan 03 02:11:48 PM PST 24
Peak memory 554180 kb
Host smart-5e64b871-ae6c-4d3a-9fa7-469db0b0649a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073418953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.4073418953
Directory /workspace/59.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke.3230183646
Short name T1382
Test name
Test status
Simulation time 205461722 ps
CPU time 9.68 seconds
Started Jan 03 02:10:40 PM PST 24
Finished Jan 03 02:11:05 PM PST 24
Peak memory 552044 kb
Host smart-7161024f-917c-4eb4-bcb8-51c6e47a9670
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230183646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.3230183646
Directory /workspace/59.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.2186195333
Short name T445
Test name
Test status
Simulation time 8101355388 ps
CPU time 88.86 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:12:22 PM PST 24
Peak memory 551816 kb
Host smart-539232b6-0a03-4b0f-a734-b1a08620d763
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186195333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.2186195333
Directory /workspace/59.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.2817876454
Short name T1717
Test name
Test status
Simulation time 4437879996 ps
CPU time 73.67 seconds
Started Jan 03 02:10:44 PM PST 24
Finished Jan 03 02:12:18 PM PST 24
Peak memory 551844 kb
Host smart-152d5f9b-7e49-4eb7-8545-4b4fe66c5228
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817876454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.2817876454
Directory /workspace/59.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1582489872
Short name T829
Test name
Test status
Simulation time 47446698 ps
CPU time 6.12 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:11:00 PM PST 24
Peak memory 551720 kb
Host smart-375ba25d-c097-4650-9dcb-178400bbc9a1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582489872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay
s.1582489872
Directory /workspace/59.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all.102406093
Short name T1096
Test name
Test status
Simulation time 13076559735 ps
CPU time 407.74 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:18:05 PM PST 24
Peak memory 554912 kb
Host smart-a5c25081-867a-4025-a118-5383f6cb21b5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102406093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.102406093
Directory /workspace/59.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.3654973260
Short name T284
Test name
Test status
Simulation time 6569292417 ps
CPU time 219.23 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:14:34 PM PST 24
Peak memory 555040 kb
Host smart-2c8816c5-f27e-4df0-802e-7b4448f13f14
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654973260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.3654973260
Directory /workspace/59.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.382449550
Short name T632
Test name
Test status
Simulation time 6260416973 ps
CPU time 273.05 seconds
Started Jan 03 02:10:39 PM PST 24
Finished Jan 03 02:15:27 PM PST 24
Peak memory 555156 kb
Host smart-b11c6b38-daa9-4b67-bbd6-c12f0b32af09
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382449550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_
with_rand_reset.382449550
Directory /workspace/59.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.4174795280
Short name T1381
Test name
Test status
Simulation time 480058800 ps
CPU time 111.17 seconds
Started Jan 03 02:10:52 PM PST 24
Finished Jan 03 02:13:06 PM PST 24
Peak memory 555544 kb
Host smart-11b09aff-1564-4ce6-a6cd-dea0411e53bc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174795280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al
l_with_reset_error.4174795280
Directory /workspace/59.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.1762503594
Short name T224
Test name
Test status
Simulation time 733243517 ps
CPU time 29.27 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:11:47 PM PST 24
Peak memory 553964 kb
Host smart-7babc272-199e-4ad7-a309-9e06f3b1079a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762503594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.1762503594
Directory /workspace/59.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.883697534
Short name T1638
Test name
Test status
Simulation time 9927949836 ps
CPU time 443.8 seconds
Started Jan 03 02:07:44 PM PST 24
Finished Jan 03 02:15:20 PM PST 24
Peak memory 621072 kb
Host smart-ed0b3bbe-df22-4689-9066-4fb076329ec9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883697534 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.883697534
Directory /workspace/6.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3999606043
Short name T57
Test name
Test status
Simulation time 30973364538 ps
CPU time 3312.85 seconds
Started Jan 03 02:07:20 PM PST 24
Finished Jan 03 03:02:45 PM PST 24
Peak memory 580100 kb
Host smart-1c672e4c-6d18-4a42-8323-06f89f675cf8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999606043 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.3999606043
Directory /workspace/6.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_access_same_device.3925178319
Short name T1799
Test name
Test status
Simulation time 1020560286 ps
CPU time 73.95 seconds
Started Jan 03 02:07:33 PM PST 24
Finished Jan 03 02:08:57 PM PST 24
Peak memory 553868 kb
Host smart-09e43fc8-25a7-4ba5-863d-7bdb2ba1300c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925178319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.
3925178319
Directory /workspace/6.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.37551443
Short name T1581
Test name
Test status
Simulation time 119448094798 ps
CPU time 1859.1 seconds
Started Jan 03 02:08:08 PM PST 24
Finished Jan 03 02:39:13 PM PST 24
Peak memory 555304 kb
Host smart-e5355d6f-8922-4236-ada6-27676d7863d3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37551443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_dev
ice_slow_rsp.37551443
Directory /workspace/6.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2532473590
Short name T455
Test name
Test status
Simulation time 751883449 ps
CPU time 29.17 seconds
Started Jan 03 02:07:21 PM PST 24
Finished Jan 03 02:08:02 PM PST 24
Peak memory 553968 kb
Host smart-524664de-eef2-4291-9aa1-0d45873ba5fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532473590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr
.2532473590
Directory /workspace/6.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_error_random.3387822414
Short name T546
Test name
Test status
Simulation time 1090811831 ps
CPU time 38.56 seconds
Started Jan 03 02:07:30 PM PST 24
Finished Jan 03 02:08:17 PM PST 24
Peak memory 553848 kb
Host smart-66766b92-e504-48af-b4e8-08bc58f6f32f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387822414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3387822414
Directory /workspace/6.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random.1296385413
Short name T46
Test name
Test status
Simulation time 1839352921 ps
CPU time 62.76 seconds
Started Jan 03 02:07:32 PM PST 24
Finished Jan 03 02:08:44 PM PST 24
Peak memory 554132 kb
Host smart-936341dd-8745-4a88-b776-fdcea8a2f190
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296385413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.1296385413
Directory /workspace/6.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.2609318068
Short name T1329
Test name
Test status
Simulation time 9430675213 ps
CPU time 104.97 seconds
Started Jan 03 02:08:07 PM PST 24
Finished Jan 03 02:09:58 PM PST 24
Peak memory 551888 kb
Host smart-88e563fe-2195-4faf-bab0-0fc288d627c8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609318068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2609318068
Directory /workspace/6.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.1225819373
Short name T1594
Test name
Test status
Simulation time 52557708473 ps
CPU time 890.65 seconds
Started Jan 03 02:07:21 PM PST 24
Finished Jan 03 02:22:24 PM PST 24
Peak memory 554296 kb
Host smart-a5a350b3-87b9-4d3d-9b7a-33780bf9a38c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225819373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1225819373
Directory /workspace/6.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.4168762870
Short name T1012
Test name
Test status
Simulation time 30995457 ps
CPU time 5.46 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:07:53 PM PST 24
Peak memory 551736 kb
Host smart-0fa000b9-f3f3-4ea5-9cbd-5d7564827377
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168762870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela
ys.4168762870
Directory /workspace/6.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_same_source.499003614
Short name T1013
Test name
Test status
Simulation time 1105387767 ps
CPU time 34.29 seconds
Started Jan 03 02:10:17 PM PST 24
Finished Jan 03 02:11:05 PM PST 24
Peak memory 554200 kb
Host smart-2e0a01c0-79db-459a-891f-2c8edaf23a2a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499003614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.499003614
Directory /workspace/6.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke.1692647913
Short name T533
Test name
Test status
Simulation time 43596197 ps
CPU time 5.56 seconds
Started Jan 03 02:07:16 PM PST 24
Finished Jan 03 02:07:27 PM PST 24
Peak memory 551620 kb
Host smart-c1a2db3a-02fd-40ef-9ab6-37af7e2d5a73
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692647913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1692647913
Directory /workspace/6.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.4072264751
Short name T521
Test name
Test status
Simulation time 9848841177 ps
CPU time 122.32 seconds
Started Jan 03 02:07:24 PM PST 24
Finished Jan 03 02:09:38 PM PST 24
Peak memory 552216 kb
Host smart-8e950bb1-2704-4cbe-85fa-4693eba8c5fa
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072264751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.4072264751
Directory /workspace/6.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.3386652985
Short name T330
Test name
Test status
Simulation time 4314728338 ps
CPU time 74.92 seconds
Started Jan 03 02:07:30 PM PST 24
Finished Jan 03 02:08:54 PM PST 24
Peak memory 551820 kb
Host smart-39406a74-a228-42d6-8c73-e0d392febef3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386652985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3386652985
Directory /workspace/6.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3448065686
Short name T267
Test name
Test status
Simulation time 51055228 ps
CPU time 5.64 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:07:52 PM PST 24
Peak memory 552132 kb
Host smart-b056f6fe-af3a-4806-9b3d-8c4820139541
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448065686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays
.3448065686
Directory /workspace/6.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all.1517646460
Short name T258
Test name
Test status
Simulation time 3205760267 ps
CPU time 117.35 seconds
Started Jan 03 02:07:41 PM PST 24
Finished Jan 03 02:09:50 PM PST 24
Peak memory 555392 kb
Host smart-0fce9646-a526-4cd4-a2fe-d81a76eda74c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517646460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1517646460
Directory /workspace/6.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3102707304
Short name T392
Test name
Test status
Simulation time 9380467387 ps
CPU time 359.64 seconds
Started Jan 03 02:07:16 PM PST 24
Finished Jan 03 02:13:21 PM PST 24
Peak memory 555100 kb
Host smart-70864454-cd34-4bbc-b84e-546863fbad1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102707304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3102707304
Directory /workspace/6.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.4244934887
Short name T926
Test name
Test status
Simulation time 1906820649 ps
CPU time 298.11 seconds
Started Jan 03 02:07:25 PM PST 24
Finished Jan 03 02:12:34 PM PST 24
Peak memory 556140 kb
Host smart-9d9e6315-c514-42d8-8644-6cc13a8c6fdf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244934887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_
with_rand_reset.4244934887
Directory /workspace/6.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3128000172
Short name T1422
Test name
Test status
Simulation time 690048844 ps
CPU time 148.26 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:10:15 PM PST 24
Peak memory 558504 kb
Host smart-fbff45b3-8945-486d-a320-b6ba3651aba1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128000172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all
_with_reset_error.3128000172
Directory /workspace/6.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.2327577697
Short name T1467
Test name
Test status
Simulation time 339326008 ps
CPU time 35.67 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:08:23 PM PST 24
Peak memory 554188 kb
Host smart-555f008f-19c8-4df6-81c9-4a572e287065
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327577697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2327577697
Directory /workspace/6.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_access_same_device.1303637937
Short name T323
Test name
Test status
Simulation time 515443465 ps
CPU time 47.29 seconds
Started Jan 03 02:11:03 PM PST 24
Finished Jan 03 02:12:12 PM PST 24
Peak memory 553908 kb
Host smart-f4c93aae-d428-4d05-99c4-42583236f54f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303637937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device
.1303637937
Directory /workspace/60.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.222794606
Short name T310
Test name
Test status
Simulation time 120710065135 ps
CPU time 1831.4 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:41:50 PM PST 24
Peak memory 555152 kb
Host smart-cfdb5f6b-3639-4708-bae6-2e62f154aade
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222794606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_d
evice_slow_rsp.222794606
Directory /workspace/60.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.306223380
Short name T568
Test name
Test status
Simulation time 713799259 ps
CPU time 28.76 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:11:53 PM PST 24
Peak memory 553860 kb
Host smart-564dd53f-c805-413d-8923-c7aafe095b83
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306223380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr
.306223380
Directory /workspace/60.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_error_random.1084550207
Short name T574
Test name
Test status
Simulation time 806416194 ps
CPU time 25.92 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:11:49 PM PST 24
Peak memory 553868 kb
Host smart-b0cd10f4-ccdc-4ba0-a665-3d8e8d9d8403
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084550207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.1084550207
Directory /workspace/60.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random.2107091576
Short name T192
Test name
Test status
Simulation time 494403300 ps
CPU time 37.94 seconds
Started Jan 03 02:10:59 PM PST 24
Finished Jan 03 02:11:58 PM PST 24
Peak memory 553876 kb
Host smart-6e5f8ef6-3b5f-4105-ab2a-fc50ddffa0d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107091576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.2107091576
Directory /workspace/60.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.2179581972
Short name T1114
Test name
Test status
Simulation time 77395097692 ps
CPU time 804.43 seconds
Started Jan 03 02:10:58 PM PST 24
Finished Jan 03 02:24:44 PM PST 24
Peak memory 554216 kb
Host smart-37f76986-d2e5-4cb2-b45f-9e8ad3f4b57d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179581972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.2179581972
Directory /workspace/60.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.2064160119
Short name T1605
Test name
Test status
Simulation time 5722296051 ps
CPU time 101.77 seconds
Started Jan 03 02:10:55 PM PST 24
Finished Jan 03 02:12:59 PM PST 24
Peak memory 551920 kb
Host smart-8cc46a6b-5daa-4cb4-83d0-d977778ad405
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064160119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.2064160119
Directory /workspace/60.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.4219865125
Short name T1906
Test name
Test status
Simulation time 295847544 ps
CPU time 25.79 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:11:42 PM PST 24
Peak memory 553908 kb
Host smart-7ba73280-fddb-4678-8110-25b08384bd72
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219865125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del
ays.4219865125
Directory /workspace/60.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_same_source.3741559915
Short name T1204
Test name
Test status
Simulation time 334528575 ps
CPU time 24.93 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:11:48 PM PST 24
Peak memory 554200 kb
Host smart-ed6d874c-6e4c-42b8-84f4-4a3387877ab5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741559915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.3741559915
Directory /workspace/60.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke.88732561
Short name T818
Test name
Test status
Simulation time 207646466 ps
CPU time 8.53 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:11:33 PM PST 24
Peak memory 552064 kb
Host smart-6b451042-718a-4a79-8a7f-d4598f4cc1f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88732561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.88732561
Directory /workspace/60.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.617747637
Short name T830
Test name
Test status
Simulation time 8176916666 ps
CPU time 89.46 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:12:53 PM PST 24
Peak memory 552108 kb
Host smart-f932b18c-910e-48b9-a23e-f0dd209a1ac1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617747637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.617747637
Directory /workspace/60.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.3916900495
Short name T1394
Test name
Test status
Simulation time 3975748113 ps
CPU time 68.48 seconds
Started Jan 03 02:10:52 PM PST 24
Finished Jan 03 02:12:23 PM PST 24
Peak memory 551744 kb
Host smart-dbdbe58d-c3b2-4556-af76-b5dfa3cf261a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916900495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.3916900495
Directory /workspace/60.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2240988965
Short name T677
Test name
Test status
Simulation time 46681780 ps
CPU time 5.9 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:11:30 PM PST 24
Peak memory 551632 kb
Host smart-190a1904-a2a4-4f32-8a82-6b33fc45a902
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240988965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay
s.2240988965
Directory /workspace/60.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all.1269849285
Short name T1263
Test name
Test status
Simulation time 2433158294 ps
CPU time 169.15 seconds
Started Jan 03 02:11:03 PM PST 24
Finished Jan 03 02:14:14 PM PST 24
Peak memory 555104 kb
Host smart-0acd9bcc-4340-4eb3-9cff-92ab342b3bb0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269849285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.1269849285
Directory /workspace/60.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.3692389907
Short name T844
Test name
Test status
Simulation time 2985322979 ps
CPU time 195.4 seconds
Started Jan 03 02:11:03 PM PST 24
Finished Jan 03 02:14:40 PM PST 24
Peak memory 555084 kb
Host smart-9d682546-fa74-4e2a-a5af-ae99067dc96b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692389907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.3692389907
Directory /workspace/60.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.390556245
Short name T1209
Test name
Test status
Simulation time 3072916093 ps
CPU time 491.55 seconds
Started Jan 03 02:11:00 PM PST 24
Finished Jan 03 02:19:34 PM PST 24
Peak memory 558052 kb
Host smart-17eb42e2-2464-4f98-8e81-d934be25d651
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390556245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_
with_rand_reset.390556245
Directory /workspace/60.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2180982308
Short name T1710
Test name
Test status
Simulation time 374696889 ps
CPU time 98.87 seconds
Started Jan 03 02:10:41 PM PST 24
Finished Jan 03 02:12:37 PM PST 24
Peak memory 555324 kb
Host smart-7d72d785-e5cf-4003-8785-8b2dca2693b0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180982308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al
l_with_reset_error.2180982308
Directory /workspace/60.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.2157709546
Short name T1474
Test name
Test status
Simulation time 214603941 ps
CPU time 26.45 seconds
Started Jan 03 02:11:01 PM PST 24
Finished Jan 03 02:11:49 PM PST 24
Peak memory 553968 kb
Host smart-5542fe1c-6443-40aa-9107-fee89acfa6bb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157709546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.2157709546
Directory /workspace/60.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_access_same_device.1194160
Short name T286
Test name
Test status
Simulation time 2260771207 ps
CPU time 87.59 seconds
Started Jan 03 02:10:59 PM PST 24
Finished Jan 03 02:12:49 PM PST 24
Peak memory 555072 kb
Host smart-c131cba8-bfa8-4979-ac12-bea3602619f2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device.1194160
Directory /workspace/61.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2149625292
Short name T999
Test name
Test status
Simulation time 3054225138 ps
CPU time 56.35 seconds
Started Jan 03 02:11:00 PM PST 24
Finished Jan 03 02:12:19 PM PST 24
Peak memory 552064 kb
Host smart-47c62eaf-2b49-4ef8-bb59-03daa534a668
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149625292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_
device_slow_rsp.2149625292
Directory /workspace/61.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.1322880939
Short name T1514
Test name
Test status
Simulation time 78405725 ps
CPU time 11.13 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:11:12 PM PST 24
Peak memory 554168 kb
Host smart-a827111d-4094-46dd-8008-cc476b87f550
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322880939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add
r.1322880939
Directory /workspace/61.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_error_random.1952322921
Short name T1721
Test name
Test status
Simulation time 541335170 ps
CPU time 43.88 seconds
Started Jan 03 02:10:45 PM PST 24
Finished Jan 03 02:11:51 PM PST 24
Peak memory 554108 kb
Host smart-c3788c5b-f377-4fe4-a2b0-51d4a99ad276
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952322921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.1952322921
Directory /workspace/61.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random.755499841
Short name T1537
Test name
Test status
Simulation time 221546802 ps
CPU time 18.96 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:11:38 PM PST 24
Peak memory 553900 kb
Host smart-129c6a35-def8-4764-8d32-8d67614cc7b3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755499841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.755499841
Directory /workspace/61.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.1531516131
Short name T644
Test name
Test status
Simulation time 42452853340 ps
CPU time 402.75 seconds
Started Jan 03 02:11:00 PM PST 24
Finished Jan 03 02:18:05 PM PST 24
Peak memory 554224 kb
Host smart-a2d37044-426b-4d3e-b8fe-e740a85a82c6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531516131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.1531516131
Directory /workspace/61.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.800534467
Short name T1170
Test name
Test status
Simulation time 63213506700 ps
CPU time 1166.48 seconds
Started Jan 03 02:11:00 PM PST 24
Finished Jan 03 02:30:49 PM PST 24
Peak memory 553864 kb
Host smart-b13e8847-5dd5-4a4e-86cf-12657e34fbce
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800534467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.800534467
Directory /workspace/61.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.3990689811
Short name T775
Test name
Test status
Simulation time 217091027 ps
CPU time 20.72 seconds
Started Jan 03 02:10:59 PM PST 24
Finished Jan 03 02:11:41 PM PST 24
Peak memory 553840 kb
Host smart-3df9a8e9-1e26-42b1-9eb1-296936b0d519
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990689811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del
ays.3990689811
Directory /workspace/61.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_same_source.828671914
Short name T139
Test name
Test status
Simulation time 970738527 ps
CPU time 29.7 seconds
Started Jan 03 02:10:58 PM PST 24
Finished Jan 03 02:11:49 PM PST 24
Peak memory 554188 kb
Host smart-7b684a36-c910-4cb1-b482-b64e68d9f6a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828671914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.828671914
Directory /workspace/61.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke.2427317684
Short name T1008
Test name
Test status
Simulation time 254242172 ps
CPU time 9.8 seconds
Started Jan 03 02:11:00 PM PST 24
Finished Jan 03 02:11:32 PM PST 24
Peak memory 552160 kb
Host smart-16ff6f7b-51fc-46af-8ed5-d220218f8cfd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427317684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.2427317684
Directory /workspace/61.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.1632866895
Short name T384
Test name
Test status
Simulation time 5345164022 ps
CPU time 55.87 seconds
Started Jan 03 02:10:57 PM PST 24
Finished Jan 03 02:12:14 PM PST 24
Peak memory 552048 kb
Host smart-e8d4cc24-74d2-423d-9964-2fb0a26b6f21
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632866895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.1632866895
Directory /workspace/61.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3215616789
Short name T505
Test name
Test status
Simulation time 4376112876 ps
CPU time 70.66 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:12:27 PM PST 24
Peak memory 552160 kb
Host smart-6dfaf0be-729e-4a18-93b4-dd26dd55cb09
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215616789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.3215616789
Directory /workspace/61.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3108977262
Short name T1280
Test name
Test status
Simulation time 50509311 ps
CPU time 6.03 seconds
Started Jan 03 02:11:03 PM PST 24
Finished Jan 03 02:11:31 PM PST 24
Peak memory 551648 kb
Host smart-937f74ca-edf7-4eb1-9298-4a349e7229ad
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108977262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay
s.3108977262
Directory /workspace/61.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all.1180062172
Short name T1132
Test name
Test status
Simulation time 10763824914 ps
CPU time 367.84 seconds
Started Jan 03 02:10:54 PM PST 24
Finished Jan 03 02:17:25 PM PST 24
Peak memory 556648 kb
Host smart-d424914f-a682-4191-bfe3-04ec5b8ade4f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180062172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.1180062172
Directory /workspace/61.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.2696755865
Short name T1371
Test name
Test status
Simulation time 1316382820 ps
CPU time 115.28 seconds
Started Jan 03 02:10:46 PM PST 24
Finished Jan 03 02:13:04 PM PST 24
Peak memory 555036 kb
Host smart-7ab8f172-be54-4b24-8940-846fd38e0056
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696755865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.2696755865
Directory /workspace/61.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.493605697
Short name T1613
Test name
Test status
Simulation time 986869588 ps
CPU time 245.78 seconds
Started Jan 03 02:10:43 PM PST 24
Finished Jan 03 02:15:08 PM PST 24
Peak memory 555860 kb
Host smart-7d59c68d-de26-420c-8360-b58229bbff2f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493605697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_
with_rand_reset.493605697
Directory /workspace/61.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3588607504
Short name T900
Test name
Test status
Simulation time 10393175321 ps
CPU time 468.92 seconds
Started Jan 03 02:10:49 PM PST 24
Finished Jan 03 02:19:01 PM PST 24
Peak memory 558236 kb
Host smart-371e8fbc-4e75-427a-aeda-7edf147a4b6c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588607504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al
l_with_reset_error.3588607504
Directory /workspace/61.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.19632994
Short name T862
Test name
Test status
Simulation time 232710483 ps
CPU time 13.19 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:11:31 PM PST 24
Peak memory 554180 kb
Host smart-19cb876f-25dd-4406-8344-57ad644a2b01
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19632994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.19632994
Directory /workspace/61.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_access_same_device.4056385947
Short name T1118
Test name
Test status
Simulation time 830492587 ps
CPU time 33.08 seconds
Started Jan 03 02:11:02 PM PST 24
Finished Jan 03 02:11:57 PM PST 24
Peak memory 553060 kb
Host smart-d19a0fc6-f235-4367-b7e2-9e11c2becd08
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056385947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device
.4056385947
Directory /workspace/62.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.839124663
Short name T1369
Test name
Test status
Simulation time 72845677735 ps
CPU time 1090.71 seconds
Started Jan 03 02:11:18 PM PST 24
Finished Jan 03 02:29:44 PM PST 24
Peak memory 555000 kb
Host smart-4382ca2f-7495-43a4-85a7-83123fcaaa85
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839124663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_d
evice_slow_rsp.839124663
Directory /workspace/62.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.2535051384
Short name T700
Test name
Test status
Simulation time 749888294 ps
CPU time 27.86 seconds
Started Jan 03 02:11:19 PM PST 24
Finished Jan 03 02:12:01 PM PST 24
Peak memory 554128 kb
Host smart-d74402e2-aad3-43be-917a-3aa61997a7d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535051384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add
r.2535051384
Directory /workspace/62.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_error_random.198099364
Short name T1255
Test name
Test status
Simulation time 654103859 ps
CPU time 21.05 seconds
Started Jan 03 02:11:18 PM PST 24
Finished Jan 03 02:11:54 PM PST 24
Peak memory 553844 kb
Host smart-1ba71aaa-3094-4082-b7b5-0172b7cb375a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198099364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.198099364
Directory /workspace/62.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random.2500270735
Short name T1916
Test name
Test status
Simulation time 1227744740 ps
CPU time 43.16 seconds
Started Jan 03 02:10:56 PM PST 24
Finished Jan 03 02:12:01 PM PST 24
Peak memory 554180 kb
Host smart-c8af3918-6e3d-4ea6-9cba-f306a0befcb0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500270735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.2500270735
Directory /workspace/62.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.494728954
Short name T1627
Test name
Test status
Simulation time 119361133066 ps
CPU time 1218.4 seconds
Started Jan 03 02:10:50 PM PST 24
Finished Jan 03 02:31:32 PM PST 24
Peak memory 553948 kb
Host smart-920795eb-e1bf-4f87-9e01-b32bcb42f104
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494728954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.494728954
Directory /workspace/62.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.140462469
Short name T564
Test name
Test status
Simulation time 39019946161 ps
CPU time 638.08 seconds
Started Jan 03 02:10:50 PM PST 24
Finished Jan 03 02:21:51 PM PST 24
Peak memory 553888 kb
Host smart-ed94c909-315f-4321-b993-4ef275a975b4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140462469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.140462469
Directory /workspace/62.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.3027206716
Short name T439
Test name
Test status
Simulation time 560799272 ps
CPU time 46.96 seconds
Started Jan 03 02:10:53 PM PST 24
Finished Jan 03 02:12:03 PM PST 24
Peak memory 553816 kb
Host smart-a606c574-124c-49ec-b825-f55118990ea0
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027206716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del
ays.3027206716
Directory /workspace/62.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_same_source.1461205157
Short name T472
Test name
Test status
Simulation time 422071889 ps
CPU time 14.6 seconds
Started Jan 03 02:11:16 PM PST 24
Finished Jan 03 02:11:46 PM PST 24
Peak memory 554268 kb
Host smart-c50f042d-3ad8-4c40-800d-9813f8d02f3c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461205157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.1461205157
Directory /workspace/62.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke.2409183492
Short name T1205
Test name
Test status
Simulation time 205082286 ps
CPU time 8.82 seconds
Started Jan 03 02:10:46 PM PST 24
Finished Jan 03 02:11:18 PM PST 24
Peak memory 552088 kb
Host smart-a98c1612-85d0-4a8b-861b-d25e4ee77683
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409183492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.2409183492
Directory /workspace/62.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.750830373
Short name T537
Test name
Test status
Simulation time 8034314801 ps
CPU time 86.92 seconds
Started Jan 03 02:10:42 PM PST 24
Finished Jan 03 02:12:27 PM PST 24
Peak memory 551896 kb
Host smart-ffe2abe6-f1e3-41d8-9a26-ba684a5932ae
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750830373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.750830373
Directory /workspace/62.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3067935142
Short name T845
Test name
Test status
Simulation time 3954264376 ps
CPU time 69.86 seconds
Started Jan 03 02:10:45 PM PST 24
Finished Jan 03 02:12:18 PM PST 24
Peak memory 551808 kb
Host smart-e16341c9-c8fa-484f-8200-683ef9abc0e1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067935142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.3067935142
Directory /workspace/62.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1535335863
Short name T1285
Test name
Test status
Simulation time 42951195 ps
CPU time 5.89 seconds
Started Jan 03 02:10:45 PM PST 24
Finished Jan 03 02:11:13 PM PST 24
Peak memory 552012 kb
Host smart-6c307e39-88f5-44d9-b291-37861e713a9a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535335863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay
s.1535335863
Directory /workspace/62.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all.1652516919
Short name T780
Test name
Test status
Simulation time 2601334785 ps
CPU time 201.79 seconds
Started Jan 03 02:11:17 PM PST 24
Finished Jan 03 02:14:54 PM PST 24
Peak memory 555216 kb
Host smart-5931b3a3-9e84-49ca-8d59-c284c873b81a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652516919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.1652516919
Directory /workspace/62.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.2102951560
Short name T320
Test name
Test status
Simulation time 15712373911 ps
CPU time 538.52 seconds
Started Jan 03 02:11:16 PM PST 24
Finished Jan 03 02:20:30 PM PST 24
Peak memory 555484 kb
Host smart-51d97e8c-5327-4a46-b099-a8ca181e56d8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102951560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.2102951560
Directory /workspace/62.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.2087820628
Short name T1180
Test name
Test status
Simulation time 5318297115 ps
CPU time 534.8 seconds
Started Jan 03 02:11:20 PM PST 24
Finished Jan 03 02:20:29 PM PST 24
Peak memory 559120 kb
Host smart-e1334607-2562-4155-9875-10221a210e66
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087820628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all
_with_rand_reset.2087820628
Directory /workspace/62.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2785939073
Short name T1888
Test name
Test status
Simulation time 180924194 ps
CPU time 40.4 seconds
Started Jan 03 02:11:15 PM PST 24
Finished Jan 03 02:12:11 PM PST 24
Peak memory 555412 kb
Host smart-02500c5c-6210-4fc3-841a-81f77f7c1308
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785939073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al
l_with_reset_error.2785939073
Directory /workspace/62.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1897964634
Short name T805
Test name
Test status
Simulation time 799594928 ps
CPU time 34.98 seconds
Started Jan 03 02:11:16 PM PST 24
Finished Jan 03 02:12:07 PM PST 24
Peak memory 553904 kb
Host smart-9f5ec011-10d8-4fb8-ba6d-7fc330376ae8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897964634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.1897964634
Directory /workspace/62.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_access_same_device.3154922066
Short name T292
Test name
Test status
Simulation time 1550630551 ps
CPU time 56.92 seconds
Started Jan 03 02:11:16 PM PST 24
Finished Jan 03 02:12:29 PM PST 24
Peak memory 554172 kb
Host smart-7044cedd-3e72-4b09-968d-dd00d16c6aa9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154922066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device
.3154922066
Directory /workspace/63.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.3718329946
Short name T297
Test name
Test status
Simulation time 82107024581 ps
CPU time 1534.33 seconds
Started Jan 03 02:11:15 PM PST 24
Finished Jan 03 02:37:05 PM PST 24
Peak memory 554028 kb
Host smart-df97d3f2-319f-4219-9d74-848e9d90dccf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718329946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_
device_slow_rsp.3718329946
Directory /workspace/63.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.991642141
Short name T1533
Test name
Test status
Simulation time 185661068 ps
CPU time 21.83 seconds
Started Jan 03 02:11:15 PM PST 24
Finished Jan 03 02:11:53 PM PST 24
Peak memory 553896 kb
Host smart-c2564c90-a86c-4839-9350-984892658966
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991642141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr
.991642141
Directory /workspace/63.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_error_random.1976108069
Short name T1310
Test name
Test status
Simulation time 2254729288 ps
CPU time 86.56 seconds
Started Jan 03 02:11:16 PM PST 24
Finished Jan 03 02:12:58 PM PST 24
Peak memory 552892 kb
Host smart-bc45341b-dedd-4519-8e0e-bd4f2270cfcf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976108069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.1976108069
Directory /workspace/63.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random.474960935
Short name T547
Test name
Test status
Simulation time 1318717273 ps
CPU time 46.19 seconds
Started Jan 03 02:11:15 PM PST 24
Finished Jan 03 02:12:17 PM PST 24
Peak memory 554220 kb
Host smart-53c2e126-d4e6-4775-8c5e-8e32d2240509
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474960935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.474960935
Directory /workspace/63.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.2605254883
Short name T132
Test name
Test status
Simulation time 33751254263 ps
CPU time 393.07 seconds
Started Jan 03 02:11:15 PM PST 24
Finished Jan 03 02:18:04 PM PST 24
Peak memory 553968 kb
Host smart-cba47c0a-b6b8-4214-9721-2aa55cc69aa8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605254883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.2605254883
Directory /workspace/63.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.1310889089
Short name T1428
Test name
Test status
Simulation time 48782663574 ps
CPU time 779.93 seconds
Started Jan 03 02:11:24 PM PST 24
Finished Jan 03 02:24:36 PM PST 24
Peak memory 553096 kb
Host smart-b17cf091-08d5-4af6-9e1b-6146555c7c70
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310889089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.1310889089
Directory /workspace/63.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.3578425892
Short name T1183
Test name
Test status
Simulation time 421513450 ps
CPU time 40.83 seconds
Started Jan 03 02:11:13 PM PST 24
Finished Jan 03 02:12:10 PM PST 24
Peak memory 552976 kb
Host smart-e6eeedf8-d06f-4d56-84c0-69ba036c6c14
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578425892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del
ays.3578425892
Directory /workspace/63.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_same_source.2053994736
Short name T1912
Test name
Test status
Simulation time 1819378283 ps
CPU time 57.53 seconds
Started Jan 03 02:11:24 PM PST 24
Finished Jan 03 02:12:33 PM PST 24
Peak memory 553128 kb
Host smart-9d46e9f3-65f0-41a4-9c40-20ea11104062
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053994736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.2053994736
Directory /workspace/63.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke.112806223
Short name T735
Test name
Test status
Simulation time 57798981 ps
CPU time 6.7 seconds
Started Jan 03 02:11:15 PM PST 24
Finished Jan 03 02:11:37 PM PST 24
Peak memory 552076 kb
Host smart-d5016138-f8bb-4e6f-a981-2b2ea25d6eff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112806223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.112806223
Directory /workspace/63.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.3273641417
Short name T1440
Test name
Test status
Simulation time 7175864200 ps
CPU time 81.33 seconds
Started Jan 03 02:11:30 PM PST 24
Finished Jan 03 02:13:01 PM PST 24
Peak memory 551808 kb
Host smart-082d5dd4-52f3-4865-b22f-47da21b1d62d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273641417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.3273641417
Directory /workspace/63.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3869522198
Short name T1081
Test name
Test status
Simulation time 3689048926 ps
CPU time 62.92 seconds
Started Jan 03 02:11:23 PM PST 24
Finished Jan 03 02:12:38 PM PST 24
Peak memory 552092 kb
Host smart-d946f10a-28af-4cc6-9989-3137847e3ca2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869522198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.3869522198
Directory /workspace/63.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2227745497
Short name T651
Test name
Test status
Simulation time 51043542 ps
CPU time 6.06 seconds
Started Jan 03 02:11:18 PM PST 24
Finished Jan 03 02:11:39 PM PST 24
Peak memory 552020 kb
Host smart-0fc0137a-085e-4e4c-bb33-9f8941fcbcb4
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227745497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay
s.2227745497
Directory /workspace/63.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.1716905110
Short name T544
Test name
Test status
Simulation time 1049758284 ps
CPU time 90.02 seconds
Started Jan 03 02:11:16 PM PST 24
Finished Jan 03 02:13:02 PM PST 24
Peak memory 555004 kb
Host smart-fae4725e-00ef-412f-96e0-8d88db6003d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716905110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.1716905110
Directory /workspace/63.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3814888608
Short name T1824
Test name
Test status
Simulation time 590826500 ps
CPU time 192.97 seconds
Started Jan 03 02:11:17 PM PST 24
Finished Jan 03 02:14:45 PM PST 24
Peak memory 556344 kb
Host smart-94047d31-11a8-4f0c-a49a-bad2bfc8036b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814888608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all
_with_rand_reset.3814888608
Directory /workspace/63.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3588608134
Short name T1130
Test name
Test status
Simulation time 1809778207 ps
CPU time 342.98 seconds
Started Jan 03 02:11:16 PM PST 24
Finished Jan 03 02:17:14 PM PST 24
Peak memory 559008 kb
Host smart-99e107e2-ac25-460c-8a5c-dd9123a9ae39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588608134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al
l_with_reset_error.3588608134
Directory /workspace/63.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.3275769391
Short name T1647
Test name
Test status
Simulation time 81895677 ps
CPU time 11.31 seconds
Started Jan 03 02:11:14 PM PST 24
Finished Jan 03 02:11:41 PM PST 24
Peak memory 553956 kb
Host smart-2c87ed67-8971-4e19-b193-a8c8f6b9d0c8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275769391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.3275769391
Directory /workspace/63.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_access_same_device.3771129707
Short name T809
Test name
Test status
Simulation time 2212047132 ps
CPU time 104.88 seconds
Started Jan 03 02:11:24 PM PST 24
Finished Jan 03 02:13:21 PM PST 24
Peak memory 554248 kb
Host smart-654cc6c9-8b76-4382-9e25-41cc477cd069
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771129707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device
.3771129707
Directory /workspace/64.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.1244648781
Short name T1917
Test name
Test status
Simulation time 56310634 ps
CPU time 8.49 seconds
Started Jan 03 02:11:22 PM PST 24
Finished Jan 03 02:11:44 PM PST 24
Peak memory 553784 kb
Host smart-4d3ed972-aa93-42e2-b362-eeb128f6417f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244648781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add
r.1244648781
Directory /workspace/64.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_error_random.725530576
Short name T532
Test name
Test status
Simulation time 1169947515 ps
CPU time 42.12 seconds
Started Jan 03 02:11:33 PM PST 24
Finished Jan 03 02:12:24 PM PST 24
Peak memory 554080 kb
Host smart-6540bbf3-a811-4079-a99b-010627149b8d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725530576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.725530576
Directory /workspace/64.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random.3220693717
Short name T1171
Test name
Test status
Simulation time 1457081442 ps
CPU time 51.42 seconds
Started Jan 03 02:11:16 PM PST 24
Finished Jan 03 02:12:23 PM PST 24
Peak memory 554076 kb
Host smart-7c36f4db-280c-4dca-a5a2-751229f34227
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220693717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.3220693717
Directory /workspace/64.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.2156650978
Short name T779
Test name
Test status
Simulation time 112783553318 ps
CPU time 1172.46 seconds
Started Jan 03 02:11:31 PM PST 24
Finished Jan 03 02:31:13 PM PST 24
Peak memory 554228 kb
Host smart-e169a9eb-082c-4523-957d-6000311a75f6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156650978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.2156650978
Directory /workspace/64.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.4165777913
Short name T1482
Test name
Test status
Simulation time 19039702874 ps
CPU time 319.2 seconds
Started Jan 03 02:11:20 PM PST 24
Finished Jan 03 02:16:53 PM PST 24
Peak memory 554204 kb
Host smart-4864a770-fee4-4f45-9f7d-dc4794daaeac
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165777913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.4165777913
Directory /workspace/64.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.2066267227
Short name T795
Test name
Test status
Simulation time 35217215 ps
CPU time 6.2 seconds
Started Jan 03 02:11:19 PM PST 24
Finished Jan 03 02:11:39 PM PST 24
Peak memory 551856 kb
Host smart-b1e6fe32-33ba-446f-81a0-c439b40850f1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066267227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del
ays.2066267227
Directory /workspace/64.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_same_source.2244884683
Short name T1597
Test name
Test status
Simulation time 2242189804 ps
CPU time 66.03 seconds
Started Jan 03 02:11:21 PM PST 24
Finished Jan 03 02:12:41 PM PST 24
Peak memory 554260 kb
Host smart-c2786555-7c54-4adc-849b-786727ad060f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244884683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.2244884683
Directory /workspace/64.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke.1824833159
Short name T1397
Test name
Test status
Simulation time 53876396 ps
CPU time 6.8 seconds
Started Jan 03 02:11:20 PM PST 24
Finished Jan 03 02:11:41 PM PST 24
Peak memory 551772 kb
Host smart-7fdd7db0-8a01-42b4-95dd-b3ecd21f013c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824833159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.1824833159
Directory /workspace/64.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.1621120745
Short name T837
Test name
Test status
Simulation time 6772381740 ps
CPU time 75.81 seconds
Started Jan 03 02:11:14 PM PST 24
Finished Jan 03 02:12:45 PM PST 24
Peak memory 551732 kb
Host smart-c4f42fac-ad86-4f9c-9b84-c7d722c52ae3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621120745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.1621120745
Directory /workspace/64.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.712292013
Short name T1409
Test name
Test status
Simulation time 4797764219 ps
CPU time 88.7 seconds
Started Jan 03 02:11:22 PM PST 24
Finished Jan 03 02:13:04 PM PST 24
Peak memory 552152 kb
Host smart-cb8b7300-cee3-486f-ae8b-469ce2c87787
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712292013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.712292013
Directory /workspace/64.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.2245902456
Short name T1399
Test name
Test status
Simulation time 43899002 ps
CPU time 6.3 seconds
Started Jan 03 02:11:31 PM PST 24
Finished Jan 03 02:11:46 PM PST 24
Peak memory 551592 kb
Host smart-578ad3d4-cfc4-4982-84c9-4a17bdf36156
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245902456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay
s.2245902456
Directory /workspace/64.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all.1169702657
Short name T638
Test name
Test status
Simulation time 3933976401 ps
CPU time 157.58 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:14:28 PM PST 24
Peak memory 555120 kb
Host smart-40b5ae1b-4c20-48c6-af53-9c939245c2de
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169702657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.1169702657
Directory /workspace/64.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.109408080
Short name T1483
Test name
Test status
Simulation time 14645769394 ps
CPU time 457.63 seconds
Started Jan 03 02:11:34 PM PST 24
Finished Jan 03 02:19:21 PM PST 24
Peak memory 555120 kb
Host smart-b44fb348-20c3-4595-8811-a300276301aa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109408080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.109408080
Directory /workspace/64.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1630929436
Short name T211
Test name
Test status
Simulation time 9185170723 ps
CPU time 391.01 seconds
Started Jan 03 02:11:19 PM PST 24
Finished Jan 03 02:18:04 PM PST 24
Peak memory 555088 kb
Host smart-33d04171-fdf4-45b3-9114-7f6428c9791e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630929436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all
_with_rand_reset.1630929436
Directory /workspace/64.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.2116045576
Short name T325
Test name
Test status
Simulation time 5437038331 ps
CPU time 494.31 seconds
Started Jan 03 02:11:34 PM PST 24
Finished Jan 03 02:19:58 PM PST 24
Peak memory 567324 kb
Host smart-8aa402bd-27dc-4872-aa45-7fa1ffd0381e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116045576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al
l_with_reset_error.2116045576
Directory /workspace/64.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.1615259614
Short name T1149
Test name
Test status
Simulation time 106302384 ps
CPU time 13.17 seconds
Started Jan 03 02:11:19 PM PST 24
Finished Jan 03 02:11:46 PM PST 24
Peak memory 553772 kb
Host smart-a9ff3347-953a-4dcc-b623-8e15523e6710
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615259614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.1615259614
Directory /workspace/64.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_access_same_device.348315195
Short name T302
Test name
Test status
Simulation time 166810380 ps
CPU time 12.14 seconds
Started Jan 03 02:11:38 PM PST 24
Finished Jan 03 02:12:04 PM PST 24
Peak memory 554156 kb
Host smart-3d58cf9a-5050-4770-8b5f-181225684c09
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348315195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device.
348315195
Directory /workspace/65.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1165585101
Short name T266
Test name
Test status
Simulation time 12568922248 ps
CPU time 209.17 seconds
Started Jan 03 02:11:35 PM PST 24
Finished Jan 03 02:15:14 PM PST 24
Peak memory 553916 kb
Host smart-42e1b47f-5e17-4446-bc96-210e1cf662cb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165585101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_
device_slow_rsp.1165585101
Directory /workspace/65.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1748364473
Short name T1810
Test name
Test status
Simulation time 82753957 ps
CPU time 6.34 seconds
Started Jan 03 02:11:33 PM PST 24
Finished Jan 03 02:11:49 PM PST 24
Peak memory 552008 kb
Host smart-b74201eb-6ce5-4918-ba83-3733c7de4c55
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748364473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add
r.1748364473
Directory /workspace/65.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_error_random.3824629339
Short name T1198
Test name
Test status
Simulation time 1409041187 ps
CPU time 45.98 seconds
Started Jan 03 02:15:56 PM PST 24
Finished Jan 03 02:16:44 PM PST 24
Peak memory 554116 kb
Host smart-07f34f3b-30c8-4b85-a81f-f52ccf0d062e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824629339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.3824629339
Directory /workspace/65.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random.3887804079
Short name T263
Test name
Test status
Simulation time 968393489 ps
CPU time 40.36 seconds
Started Jan 03 02:11:34 PM PST 24
Finished Jan 03 02:12:24 PM PST 24
Peak memory 554128 kb
Host smart-444cca34-c5ef-4c0d-9492-20ca9d20dab9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887804079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.3887804079
Directory /workspace/65.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.3341604847
Short name T1301
Test name
Test status
Simulation time 26317164365 ps
CPU time 275.22 seconds
Started Jan 03 02:11:36 PM PST 24
Finished Jan 03 02:16:21 PM PST 24
Peak memory 553956 kb
Host smart-a66b2c0f-cf1e-4877-85bc-215ee0c73c03
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341604847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.3341604847
Directory /workspace/65.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2468564474
Short name T1886
Test name
Test status
Simulation time 68959955215 ps
CPU time 1130.14 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:30:42 PM PST 24
Peak memory 554328 kb
Host smart-45441bed-7691-4913-81e7-386161674ecd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468564474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.2468564474
Directory /workspace/65.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.4172283737
Short name T1163
Test name
Test status
Simulation time 93663538 ps
CPU time 10.98 seconds
Started Jan 03 02:11:38 PM PST 24
Finished Jan 03 02:12:04 PM PST 24
Peak memory 553816 kb
Host smart-0ab29263-a35d-4c76-975b-305e91543d2f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172283737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del
ays.4172283737
Directory /workspace/65.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_same_source.3096789730
Short name T752
Test name
Test status
Simulation time 2635858458 ps
CPU time 70.58 seconds
Started Jan 03 02:11:41 PM PST 24
Finished Jan 03 02:13:08 PM PST 24
Peak memory 554168 kb
Host smart-45d59af5-17fa-4f36-b128-a325b8495d2b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096789730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.3096789730
Directory /workspace/65.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke.1564473219
Short name T617
Test name
Test status
Simulation time 42889405 ps
CPU time 5.65 seconds
Started Jan 03 02:11:34 PM PST 24
Finished Jan 03 02:11:49 PM PST 24
Peak memory 552108 kb
Host smart-bf1bde80-b67d-47f7-94eb-198cd54fedd5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564473219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.1564473219
Directory /workspace/65.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.2784648457
Short name T1444
Test name
Test status
Simulation time 10022824542 ps
CPU time 101.64 seconds
Started Jan 03 02:11:39 PM PST 24
Finished Jan 03 02:13:36 PM PST 24
Peak memory 551804 kb
Host smart-03dee21f-d7d1-45bb-a7e2-7b3928def945
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784648457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.2784648457
Directory /workspace/65.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.1540437765
Short name T1327
Test name
Test status
Simulation time 5147318098 ps
CPU time 94.25 seconds
Started Jan 03 02:11:41 PM PST 24
Finished Jan 03 02:13:31 PM PST 24
Peak memory 552108 kb
Host smart-06ff7ad4-841c-4e2c-ba07-f43d6d86fe44
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540437765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.1540437765
Directory /workspace/65.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.2051805644
Short name T1145
Test name
Test status
Simulation time 55249400 ps
CPU time 6.93 seconds
Started Jan 03 02:11:19 PM PST 24
Finished Jan 03 02:11:40 PM PST 24
Peak memory 551756 kb
Host smart-72e7c922-318c-4ad7-aa1b-40742261bf81
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051805644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay
s.2051805644
Directory /workspace/65.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all.3936217908
Short name T1874
Test name
Test status
Simulation time 3709426673 ps
CPU time 148.89 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:14:20 PM PST 24
Peak memory 554280 kb
Host smart-1023f23b-8023-4001-80a9-4ae360e79e52
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936217908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.3936217908
Directory /workspace/65.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.1956585055
Short name T1725
Test name
Test status
Simulation time 5524552552 ps
CPU time 239.56 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:15:51 PM PST 24
Peak memory 554160 kb
Host smart-0ad2adc3-88be-4eab-97eb-ff05dfcdcdd1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956585055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.1956585055
Directory /workspace/65.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1447413680
Short name T1437
Test name
Test status
Simulation time 2805407083 ps
CPU time 323.39 seconds
Started Jan 03 02:11:42 PM PST 24
Finished Jan 03 02:17:22 PM PST 24
Peak memory 556684 kb
Host smart-282ff43e-1e6f-4d83-a20e-38ea5cbac9d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447413680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all
_with_rand_reset.1447413680
Directory /workspace/65.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2211168559
Short name T348
Test name
Test status
Simulation time 505478845 ps
CPU time 126.42 seconds
Started Jan 03 02:15:31 PM PST 24
Finished Jan 03 02:17:45 PM PST 24
Peak memory 557240 kb
Host smart-1440fd40-626b-49b2-b06d-625011e1bbc1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211168559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al
l_with_reset_error.2211168559
Directory /workspace/65.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.3031646166
Short name T858
Test name
Test status
Simulation time 270609246 ps
CPU time 13.95 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:12:05 PM PST 24
Peak memory 552944 kb
Host smart-f1188d29-79da-4de2-b121-4002275683c6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031646166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.3031646166
Directory /workspace/65.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_access_same_device.1696924693
Short name T326
Test name
Test status
Simulation time 1215489780 ps
CPU time 90.89 seconds
Started Jan 03 02:11:17 PM PST 24
Finished Jan 03 02:13:03 PM PST 24
Peak memory 553936 kb
Host smart-d6f52481-9ad1-46f1-8a5c-7f73efcf1678
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696924693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device
.1696924693
Directory /workspace/66.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2597087839
Short name T1825
Test name
Test status
Simulation time 44121488964 ps
CPU time 803.24 seconds
Started Jan 03 02:11:16 PM PST 24
Finished Jan 03 02:24:55 PM PST 24
Peak memory 554176 kb
Host smart-aa3e5f70-b836-443c-8aa8-5681d4826dd1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597087839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_
device_slow_rsp.2597087839
Directory /workspace/66.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.366832199
Short name T718
Test name
Test status
Simulation time 85053634 ps
CPU time 6.96 seconds
Started Jan 03 02:11:19 PM PST 24
Finished Jan 03 02:11:41 PM PST 24
Peak memory 551880 kb
Host smart-abf10dfd-cf9d-4336-b3aa-d6b56b571576
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366832199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr
.366832199
Directory /workspace/66.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_error_random.3157192499
Short name T366
Test name
Test status
Simulation time 195146148 ps
CPU time 15.63 seconds
Started Jan 03 02:11:15 PM PST 24
Finished Jan 03 02:11:46 PM PST 24
Peak memory 554096 kb
Host smart-9f1d0523-10dd-4157-8a6b-6a0445f83014
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157192499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.3157192499
Directory /workspace/66.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random.1088384262
Short name T493
Test name
Test status
Simulation time 118022799 ps
CPU time 8.73 seconds
Started Jan 03 02:11:48 PM PST 24
Finished Jan 03 02:12:11 PM PST 24
Peak memory 552120 kb
Host smart-cca6f6e7-506d-4b6e-b0b0-aed894485b12
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088384262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.1088384262
Directory /workspace/66.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.4148251674
Short name T542
Test name
Test status
Simulation time 105707779233 ps
CPU time 1129.35 seconds
Started Jan 03 02:11:54 PM PST 24
Finished Jan 03 02:30:54 PM PST 24
Peak memory 554280 kb
Host smart-7d3cb73a-1a9a-49a6-ba3f-cf2a3124cafc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148251674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.4148251674
Directory /workspace/66.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.1270304842
Short name T510
Test name
Test status
Simulation time 9741846198 ps
CPU time 162.12 seconds
Started Jan 03 02:11:20 PM PST 24
Finished Jan 03 02:14:16 PM PST 24
Peak memory 553928 kb
Host smart-7ef0b2d9-a9bf-48fe-b0f9-46018a388ea6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270304842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.1270304842
Directory /workspace/66.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.943645957
Short name T592
Test name
Test status
Simulation time 429549863 ps
CPU time 35.57 seconds
Started Jan 03 02:11:47 PM PST 24
Finished Jan 03 02:12:37 PM PST 24
Peak memory 553900 kb
Host smart-c35913ca-d876-49f9-8248-888ea73fc391
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943645957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_dela
ys.943645957
Directory /workspace/66.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_same_source.431124380
Short name T668
Test name
Test status
Simulation time 2170600551 ps
CPU time 65.05 seconds
Started Jan 03 02:11:16 PM PST 24
Finished Jan 03 02:12:36 PM PST 24
Peak memory 554168 kb
Host smart-0c5a93fe-7e08-4b2d-bea6-2f12e94cecab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431124380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.431124380
Directory /workspace/66.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke.3436389099
Short name T662
Test name
Test status
Simulation time 192192915 ps
CPU time 8.25 seconds
Started Jan 03 02:11:21 PM PST 24
Finished Jan 03 02:11:43 PM PST 24
Peak memory 552068 kb
Host smart-0eaf84b3-128f-46e9-ba86-522c1a460dd1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436389099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.3436389099
Directory /workspace/66.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.3143389470
Short name T1333
Test name
Test status
Simulation time 9542186812 ps
CPU time 98.33 seconds
Started Jan 03 02:11:52 PM PST 24
Finished Jan 03 02:13:42 PM PST 24
Peak memory 552180 kb
Host smart-9a23de6e-78a4-4a9a-a9ff-fbb1866fc9ee
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143389470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.3143389470
Directory /workspace/66.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.2546389037
Short name T404
Test name
Test status
Simulation time 3211198136 ps
CPU time 49.81 seconds
Started Jan 03 02:11:40 PM PST 24
Finished Jan 03 02:12:46 PM PST 24
Peak memory 552128 kb
Host smart-f97f1ac8-89a9-4ae5-b129-f1098ea8c4b0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546389037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.2546389037
Directory /workspace/66.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.49748412
Short name T609
Test name
Test status
Simulation time 51413274 ps
CPU time 6.1 seconds
Started Jan 03 02:11:44 PM PST 24
Finished Jan 03 02:12:06 PM PST 24
Peak memory 551796 kb
Host smart-053c6c57-7970-49d1-b106-83f0637786dc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49748412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays.49748412
Directory /workspace/66.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all.1637979808
Short name T649
Test name
Test status
Simulation time 14745231632 ps
CPU time 553.86 seconds
Started Jan 03 02:11:14 PM PST 24
Finished Jan 03 02:20:44 PM PST 24
Peak memory 555432 kb
Host smart-06e17aa2-b9e4-42db-b92b-9cdf2bb04674
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637979808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.1637979808
Directory /workspace/66.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.234950858
Short name T1536
Test name
Test status
Simulation time 11295196999 ps
CPU time 391.55 seconds
Started Jan 03 02:11:18 PM PST 24
Finished Jan 03 02:18:05 PM PST 24
Peak memory 555072 kb
Host smart-0f10e8cc-298e-4073-8834-fa9081300e1b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234950858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.234950858
Directory /workspace/66.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1246802705
Short name T1731
Test name
Test status
Simulation time 99610248 ps
CPU time 35.77 seconds
Started Jan 03 02:11:31 PM PST 24
Finished Jan 03 02:12:16 PM PST 24
Peak memory 554420 kb
Host smart-2f611103-bd09-4d7d-84f4-cb8dd9c84bc3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246802705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all
_with_rand_reset.1246802705
Directory /workspace/66.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.4073122495
Short name T1898
Test name
Test status
Simulation time 1516208817 ps
CPU time 155.17 seconds
Started Jan 03 02:11:17 PM PST 24
Finished Jan 03 02:14:07 PM PST 24
Peak memory 556340 kb
Host smart-910d28ed-80a6-4999-ba2b-6a692e264368
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073122495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al
l_with_reset_error.4073122495
Directory /workspace/66.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.3346657025
Short name T950
Test name
Test status
Simulation time 107380655 ps
CPU time 14.79 seconds
Started Jan 03 02:11:15 PM PST 24
Finished Jan 03 02:11:46 PM PST 24
Peak memory 553836 kb
Host smart-00ada7f9-11a0-4620-a50d-ce3897982d5e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346657025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.3346657025
Directory /workspace/66.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_access_same_device.3906069078
Short name T1202
Test name
Test status
Simulation time 324075147 ps
CPU time 15.95 seconds
Started Jan 03 02:11:15 PM PST 24
Finished Jan 03 02:11:47 PM PST 24
Peak memory 553144 kb
Host smart-690e9645-d9c1-4b11-89c0-a624a95de1a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906069078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device
.3906069078
Directory /workspace/67.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2923752992
Short name T1380
Test name
Test status
Simulation time 49595584600 ps
CPU time 822.42 seconds
Started Jan 03 02:11:36 PM PST 24
Finished Jan 03 02:25:29 PM PST 24
Peak memory 553912 kb
Host smart-1527d052-31b3-4c80-bbb9-fc722ad42ae0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923752992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_
device_slow_rsp.2923752992
Directory /workspace/67.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.926890951
Short name T1038
Test name
Test status
Simulation time 142476583 ps
CPU time 7.82 seconds
Started Jan 03 02:11:31 PM PST 24
Finished Jan 03 02:11:48 PM PST 24
Peak memory 551664 kb
Host smart-21e9d8d2-f07c-4bb6-b4aa-85deafc4e0d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926890951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_addr
.926890951
Directory /workspace/67.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_error_random.3340620703
Short name T853
Test name
Test status
Simulation time 418540068 ps
CPU time 34.52 seconds
Started Jan 03 02:11:20 PM PST 24
Finished Jan 03 02:12:08 PM PST 24
Peak memory 554088 kb
Host smart-3fe663c0-b017-4a72-b6d7-9d27791c2fab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340620703 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.3340620703
Directory /workspace/67.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random.2107962994
Short name T843
Test name
Test status
Simulation time 2268168448 ps
CPU time 89.16 seconds
Started Jan 03 02:11:18 PM PST 24
Finished Jan 03 02:13:02 PM PST 24
Peak memory 553144 kb
Host smart-eb7fd65b-a956-4288-a908-baec95273bd5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107962994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.2107962994
Directory /workspace/67.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.1408586333
Short name T1386
Test name
Test status
Simulation time 77538219754 ps
CPU time 862.4 seconds
Started Jan 03 02:11:15 PM PST 24
Finished Jan 03 02:25:53 PM PST 24
Peak memory 553976 kb
Host smart-8bcfc764-97ef-429c-8958-d07ca6499a23
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408586333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.1408586333
Directory /workspace/67.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.1275159317
Short name T1041
Test name
Test status
Simulation time 47424636418 ps
CPU time 808.39 seconds
Started Jan 03 02:11:17 PM PST 24
Finished Jan 03 02:25:01 PM PST 24
Peak memory 553096 kb
Host smart-c71d9c8a-af4b-4479-a172-ba071a3c6491
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275159317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.1275159317
Directory /workspace/67.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.2377868530
Short name T1186
Test name
Test status
Simulation time 222153060 ps
CPU time 18.96 seconds
Started Jan 03 02:11:20 PM PST 24
Finished Jan 03 02:11:53 PM PST 24
Peak memory 553860 kb
Host smart-00d12896-213d-47b0-be91-648c5eea75c1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377868530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del
ays.2377868530
Directory /workspace/67.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_same_source.1869559257
Short name T1913
Test name
Test status
Simulation time 303500568 ps
CPU time 12.54 seconds
Started Jan 03 02:11:17 PM PST 24
Finished Jan 03 02:11:45 PM PST 24
Peak memory 554144 kb
Host smart-5d115b60-2a40-42f0-aab5-eca9d21ee568
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869559257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.1869559257
Directory /workspace/67.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke.1520211587
Short name T629
Test name
Test status
Simulation time 180343175 ps
CPU time 8.35 seconds
Started Jan 03 02:11:14 PM PST 24
Finished Jan 03 02:11:38 PM PST 24
Peak memory 551600 kb
Host smart-17bc4748-88bb-479d-96fa-3df82fe04737
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520211587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.1520211587
Directory /workspace/67.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.357049517
Short name T557
Test name
Test status
Simulation time 9310821747 ps
CPU time 94.11 seconds
Started Jan 03 02:11:24 PM PST 24
Finished Jan 03 02:13:10 PM PST 24
Peak memory 551936 kb
Host smart-f11b9366-06fd-428a-8ad9-9ad44fa7342d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357049517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.357049517
Directory /workspace/67.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.816074105
Short name T1024
Test name
Test status
Simulation time 6152960278 ps
CPU time 103.37 seconds
Started Jan 03 02:11:20 PM PST 24
Finished Jan 03 02:13:17 PM PST 24
Peak memory 551832 kb
Host smart-c5793108-a6b9-47bc-ba3e-15d06fb2e245
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816074105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.816074105
Directory /workspace/67.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1544467801
Short name T616
Test name
Test status
Simulation time 49575772 ps
CPU time 6.32 seconds
Started Jan 03 02:11:14 PM PST 24
Finished Jan 03 02:11:37 PM PST 24
Peak memory 551816 kb
Host smart-43e94485-78bf-4328-93a5-4da8d5cca228
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544467801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay
s.1544467801
Directory /workspace/67.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all.3337566249
Short name T199
Test name
Test status
Simulation time 1366763922 ps
CPU time 105.22 seconds
Started Jan 03 02:11:36 PM PST 24
Finished Jan 03 02:13:31 PM PST 24
Peak memory 554024 kb
Host smart-66203fca-d140-403a-9ce6-8e94706b56df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337566249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.3337566249
Directory /workspace/67.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.3314086713
Short name T42
Test name
Test status
Simulation time 804768037 ps
CPU time 71.5 seconds
Started Jan 03 02:11:24 PM PST 24
Finished Jan 03 02:12:47 PM PST 24
Peak memory 555028 kb
Host smart-04c93aea-cdab-40ed-9c3e-7e3a10930667
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314086713 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.3314086713
Directory /workspace/67.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3697246881
Short name T423
Test name
Test status
Simulation time 80676876 ps
CPU time 46.37 seconds
Started Jan 03 02:11:33 PM PST 24
Finished Jan 03 02:12:29 PM PST 24
Peak memory 553832 kb
Host smart-51974feb-7236-4985-91ae-e1edc2d82fa2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697246881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all
_with_rand_reset.3697246881
Directory /workspace/67.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1357849370
Short name T961
Test name
Test status
Simulation time 10608340232 ps
CPU time 574.05 seconds
Started Jan 03 02:11:22 PM PST 24
Finished Jan 03 02:21:09 PM PST 24
Peak memory 567284 kb
Host smart-1277d2f0-f267-4d45-bb49-beaa64d36c98
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357849370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al
l_with_reset_error.1357849370
Directory /workspace/67.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.2874162869
Short name T1136
Test name
Test status
Simulation time 19321915 ps
CPU time 5.43 seconds
Started Jan 03 02:11:31 PM PST 24
Finished Jan 03 02:11:45 PM PST 24
Peak memory 552112 kb
Host smart-8bd6642f-f2c3-4105-8f32-caac8914ea2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874162869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.2874162869
Directory /workspace/67.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_access_same_device.181646391
Short name T1804
Test name
Test status
Simulation time 3155615958 ps
CPU time 132.1 seconds
Started Jan 03 02:11:36 PM PST 24
Finished Jan 03 02:13:58 PM PST 24
Peak memory 555224 kb
Host smart-316c9f63-18e0-45d8-85d2-1353cc2ff2a5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181646391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device.
181646391
Directory /workspace/68.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1376767442
Short name T296
Test name
Test status
Simulation time 127491343270 ps
CPU time 2070.88 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:46:20 PM PST 24
Peak memory 555088 kb
Host smart-992864e0-ba8b-4897-8a9e-99120afd3621
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376767442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_
device_slow_rsp.1376767442
Directory /workspace/68.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2094504145
Short name T1744
Test name
Test status
Simulation time 774170293 ps
CPU time 28.33 seconds
Started Jan 03 02:11:38 PM PST 24
Finished Jan 03 02:12:21 PM PST 24
Peak memory 554132 kb
Host smart-b0acb272-0183-4be3-80e6-f695c4f379d7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094504145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add
r.2094504145
Directory /workspace/68.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_error_random.510936897
Short name T754
Test name
Test status
Simulation time 350339756 ps
CPU time 14.88 seconds
Started Jan 03 02:11:20 PM PST 24
Finished Jan 03 02:11:49 PM PST 24
Peak memory 554144 kb
Host smart-25339552-de81-4bb0-b234-0d8df56164e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510936897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.510936897
Directory /workspace/68.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random.2131871709
Short name T1641
Test name
Test status
Simulation time 2165081145 ps
CPU time 76.43 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:13:05 PM PST 24
Peak memory 554200 kb
Host smart-1409e021-e5eb-4279-8367-a0db21e6c860
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131871709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.2131871709
Directory /workspace/68.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.3470085813
Short name T1798
Test name
Test status
Simulation time 70121850817 ps
CPU time 749.21 seconds
Started Jan 03 02:11:23 PM PST 24
Finished Jan 03 02:24:05 PM PST 24
Peak memory 554192 kb
Host smart-6622e859-5cad-437c-9e85-c5b564500ca2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470085813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.3470085813
Directory /workspace/68.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.3433596739
Short name T732
Test name
Test status
Simulation time 10880263290 ps
CPU time 195.85 seconds
Started Jan 03 02:11:41 PM PST 24
Finished Jan 03 02:15:13 PM PST 24
Peak memory 553924 kb
Host smart-e2c5dce5-333b-437b-a635-0c346c4ef7b9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433596739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.3433596739
Directory /workspace/68.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.3965044840
Short name T1783
Test name
Test status
Simulation time 289524709 ps
CPU time 24.24 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:12:13 PM PST 24
Peak memory 553876 kb
Host smart-7a7274c8-de14-48b4-95d8-3a1b3dd36407
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965044840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del
ays.3965044840
Directory /workspace/68.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_same_source.2857967536
Short name T1087
Test name
Test status
Simulation time 885535636 ps
CPU time 27.29 seconds
Started Jan 03 02:11:36 PM PST 24
Finished Jan 03 02:12:13 PM PST 24
Peak memory 553936 kb
Host smart-e265c981-7072-4f05-9e28-aad0a6ef2647
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857967536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.2857967536
Directory /workspace/68.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke.4264883597
Short name T1296
Test name
Test status
Simulation time 203315317 ps
CPU time 8.31 seconds
Started Jan 03 02:11:23 PM PST 24
Finished Jan 03 02:11:44 PM PST 24
Peak memory 551776 kb
Host smart-e27d0bb7-0ef8-4d4b-9005-644bef241cd7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264883597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.4264883597
Directory /workspace/68.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.973272713
Short name T590
Test name
Test status
Simulation time 8142154200 ps
CPU time 83.88 seconds
Started Jan 03 02:11:33 PM PST 24
Finished Jan 03 02:13:06 PM PST 24
Peak memory 552156 kb
Host smart-de79dc41-beca-494c-b6a1-5681da02a821
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973272713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.973272713
Directory /workspace/68.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2815765812
Short name T1568
Test name
Test status
Simulation time 5679049314 ps
CPU time 96.74 seconds
Started Jan 03 02:11:38 PM PST 24
Finished Jan 03 02:13:28 PM PST 24
Peak memory 552076 kb
Host smart-422f0f0b-b848-45a1-ba74-e9c9c71b742e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815765812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.2815765812
Directory /workspace/68.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.3530933358
Short name T1057
Test name
Test status
Simulation time 48533050 ps
CPU time 6.18 seconds
Started Jan 03 02:11:23 PM PST 24
Finished Jan 03 02:11:42 PM PST 24
Peak memory 551720 kb
Host smart-ce0c2112-4d57-4e69-abfe-b8ea8430bd5c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530933358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay
s.3530933358
Directory /workspace/68.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all.2267961271
Short name T118
Test name
Test status
Simulation time 2495438747 ps
CPU time 197.52 seconds
Started Jan 03 02:11:34 PM PST 24
Finished Jan 03 02:15:01 PM PST 24
Peak memory 555116 kb
Host smart-5be703c5-4fd0-4f68-83d5-174544b903cb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267961271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.2267961271
Directory /workspace/68.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.4043841872
Short name T1769
Test name
Test status
Simulation time 1924232601 ps
CPU time 64.56 seconds
Started Jan 03 02:11:44 PM PST 24
Finished Jan 03 02:13:04 PM PST 24
Peak memory 554148 kb
Host smart-584405cc-6992-4cf9-954e-b038a8b9be77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043841872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.4043841872
Directory /workspace/68.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2790930009
Short name T346
Test name
Test status
Simulation time 6385447861 ps
CPU time 360.14 seconds
Started Jan 03 02:11:35 PM PST 24
Finished Jan 03 02:17:44 PM PST 24
Peak memory 555152 kb
Host smart-8b636f4b-8a52-4934-bff8-fba41f4a0a18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790930009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all
_with_rand_reset.2790930009
Directory /workspace/68.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2009889453
Short name T875
Test name
Test status
Simulation time 515015854 ps
CPU time 110.6 seconds
Started Jan 03 02:11:42 PM PST 24
Finished Jan 03 02:13:48 PM PST 24
Peak memory 554688 kb
Host smart-661c481a-dc90-4898-acbc-3b70e7228ba7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009889453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al
l_with_reset_error.2009889453
Directory /workspace/68.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.163716729
Short name T1493
Test name
Test status
Simulation time 1228023131 ps
CPU time 49.97 seconds
Started Jan 03 02:11:24 PM PST 24
Finished Jan 03 02:12:26 PM PST 24
Peak memory 553980 kb
Host smart-1229aa77-368e-4855-8cc2-38785a4b72e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163716729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.163716729
Directory /workspace/68.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_access_same_device.549402048
Short name T1408
Test name
Test status
Simulation time 2413424811 ps
CPU time 90.04 seconds
Started Jan 03 02:11:44 PM PST 24
Finished Jan 03 02:13:30 PM PST 24
Peak memory 553192 kb
Host smart-8bafdf3b-51b5-4922-9cc8-512f4f7e15e6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549402048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device.
549402048
Directory /workspace/69.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2733983374
Short name T1052
Test name
Test status
Simulation time 127726027589 ps
CPU time 2054.81 seconds
Started Jan 03 02:11:46 PM PST 24
Finished Jan 03 02:46:17 PM PST 24
Peak memory 555100 kb
Host smart-0d7a9182-638e-4d10-a39f-efdc1478cb08
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733983374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_
device_slow_rsp.2733983374
Directory /workspace/69.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1537735378
Short name T390
Test name
Test status
Simulation time 1340601134 ps
CPU time 52.31 seconds
Started Jan 03 02:11:44 PM PST 24
Finished Jan 03 02:12:52 PM PST 24
Peak memory 553976 kb
Host smart-48034992-a1eb-4108-b131-feec238ba0fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537735378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add
r.1537735378
Directory /workspace/69.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_error_random.2463634941
Short name T430
Test name
Test status
Simulation time 519118394 ps
CPU time 18.21 seconds
Started Jan 03 02:11:36 PM PST 24
Finished Jan 03 02:12:05 PM PST 24
Peak memory 554084 kb
Host smart-e0ecfdd7-c5de-4acf-b163-97145e4686c7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463634941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.2463634941
Directory /workspace/69.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random.133733213
Short name T1739
Test name
Test status
Simulation time 1217731454 ps
CPU time 44.05 seconds
Started Jan 03 02:11:42 PM PST 24
Finished Jan 03 02:12:42 PM PST 24
Peak memory 553868 kb
Host smart-5043993c-ccaf-4685-8ad2-5ce855660777
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133733213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.133733213
Directory /workspace/69.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.147363068
Short name T1814
Test name
Test status
Simulation time 53982013400 ps
CPU time 547.57 seconds
Started Jan 03 02:11:43 PM PST 24
Finished Jan 03 02:21:07 PM PST 24
Peak memory 554216 kb
Host smart-fb52e940-3851-4820-a8ef-f49158ca7ea4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147363068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.147363068
Directory /workspace/69.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.516961244
Short name T783
Test name
Test status
Simulation time 32296046280 ps
CPU time 523.92 seconds
Started Jan 03 02:11:48 PM PST 24
Finished Jan 03 02:20:46 PM PST 24
Peak memory 554284 kb
Host smart-af559d46-4f10-46fb-97ed-f8a85d064bb3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516961244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.516961244
Directory /workspace/69.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.274358209
Short name T1070
Test name
Test status
Simulation time 62421968 ps
CPU time 7.87 seconds
Started Jan 03 02:11:50 PM PST 24
Finished Jan 03 02:12:11 PM PST 24
Peak memory 552132 kb
Host smart-6e7f1f28-44a3-4008-bd05-f2bc119f0afc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274358209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_dela
ys.274358209
Directory /workspace/69.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_same_source.1063684167
Short name T233
Test name
Test status
Simulation time 2530295970 ps
CPU time 74.04 seconds
Started Jan 03 02:11:47 PM PST 24
Finished Jan 03 02:13:16 PM PST 24
Peak memory 553152 kb
Host smart-90edecdc-9266-4726-9f1f-35bd76b84ec3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063684167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.1063684167
Directory /workspace/69.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke.876562606
Short name T567
Test name
Test status
Simulation time 228123827 ps
CPU time 8.87 seconds
Started Jan 03 02:11:43 PM PST 24
Finished Jan 03 02:12:08 PM PST 24
Peak memory 551676 kb
Host smart-7847217d-2769-43f4-9d58-b75a7444cccf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876562606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.876562606
Directory /workspace/69.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.1659259244
Short name T431
Test name
Test status
Simulation time 8419946763 ps
CPU time 92.66 seconds
Started Jan 03 02:11:38 PM PST 24
Finished Jan 03 02:13:26 PM PST 24
Peak memory 551800 kb
Host smart-ab0e2c7d-6ce7-4489-b00e-e09eb81520dd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659259244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.1659259244
Directory /workspace/69.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1848831861
Short name T1494
Test name
Test status
Simulation time 5581112063 ps
CPU time 96.06 seconds
Started Jan 03 02:11:40 PM PST 24
Finished Jan 03 02:13:33 PM PST 24
Peak memory 551800 kb
Host smart-0d4f2943-afc7-42f2-959c-0f49628fe6f9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848831861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.1848831861
Directory /workspace/69.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.942747406
Short name T475
Test name
Test status
Simulation time 55179192 ps
CPU time 7.2 seconds
Started Jan 03 02:11:40 PM PST 24
Finished Jan 03 02:12:04 PM PST 24
Peak memory 552012 kb
Host smart-dbddd246-4a80-41e1-a8a6-aea34b7da18a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942747406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays
.942747406
Directory /workspace/69.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all.3175795872
Short name T265
Test name
Test status
Simulation time 1442008553 ps
CPU time 120.93 seconds
Started Jan 03 02:11:20 PM PST 24
Finished Jan 03 02:13:35 PM PST 24
Peak memory 555012 kb
Host smart-f33bfb84-3dcb-4281-8d87-1e0d5d8922d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175795872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.3175795872
Directory /workspace/69.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.3422613675
Short name T1518
Test name
Test status
Simulation time 15446369951 ps
CPU time 518.79 seconds
Started Jan 03 02:11:19 PM PST 24
Finished Jan 03 02:20:12 PM PST 24
Peak memory 556928 kb
Host smart-e6851201-7e31-4cc5-ac77-2f8e8219e7df
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422613675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.3422613675
Directory /workspace/69.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1111687478
Short name T1393
Test name
Test status
Simulation time 4658023833 ps
CPU time 303.17 seconds
Started Jan 03 02:11:48 PM PST 24
Finished Jan 03 02:17:05 PM PST 24
Peak memory 557544 kb
Host smart-edd73054-694f-4d37-a34f-c8cf0a905c77
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111687478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all
_with_rand_reset.1111687478
Directory /workspace/69.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2133549692
Short name T270
Test name
Test status
Simulation time 494727816 ps
CPU time 139.51 seconds
Started Jan 03 02:11:20 PM PST 24
Finished Jan 03 02:13:54 PM PST 24
Peak memory 557748 kb
Host smart-d2bc524b-d4f6-4f28-bb9d-2b159441c727
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133549692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al
l_with_reset_error.2133549692
Directory /workspace/69.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.3796395834
Short name T464
Test name
Test status
Simulation time 300755089 ps
CPU time 15.52 seconds
Started Jan 03 02:11:33 PM PST 24
Finished Jan 03 02:11:58 PM PST 24
Peak memory 553928 kb
Host smart-4e8978ad-29c7-42e0-af67-fad45b0a6172
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796395834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.3796395834
Directory /workspace/69.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.431101974
Short name T835
Test name
Test status
Simulation time 7012011606 ps
CPU time 362.35 seconds
Started Jan 03 02:07:37 PM PST 24
Finished Jan 03 02:13:52 PM PST 24
Peak memory 629156 kb
Host smart-a99155dd-0054-4729-8c82-b0274a8d8226
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431101974 -assert nopostproc +U
VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.431101974
Directory /workspace/7.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.chip_csr_rw.808405260
Short name T8
Test name
Test status
Simulation time 3601043688 ps
CPU time 287.33 seconds
Started Jan 03 02:07:30 PM PST 24
Finished Jan 03 02:12:26 PM PST 24
Peak memory 579948 kb
Host smart-85d0b3d0-65c1-4db8-9711-5cafd79aa2ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808405260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.808405260
Directory /workspace/7.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.1999178324
Short name T23
Test name
Test status
Simulation time 15125867264 ps
CPU time 1568.72 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:33:57 PM PST 24
Peak memory 579988 kb
Host smart-512224f4-30df-47b0-a65f-5643743b0aed
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999178324 -assert nopostproc +UVM_TE
STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.1999178324
Directory /workspace/7.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.chip_tl_errors.3155775091
Short name T1903
Test name
Test status
Simulation time 3851598585 ps
CPU time 241.13 seconds
Started Jan 03 02:07:31 PM PST 24
Finished Jan 03 02:11:41 PM PST 24
Peak memory 580016 kb
Host smart-210f7481-cb21-453e-a56c-a227cbf17d14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155775091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.3155775091
Directory /workspace/7.chip_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_access_same_device.3884687809
Short name T1252
Test name
Test status
Simulation time 432429842 ps
CPU time 31.4 seconds
Started Jan 03 02:07:54 PM PST 24
Finished Jan 03 02:08:36 PM PST 24
Peak memory 554012 kb
Host smart-c9a45d40-50df-404e-9e21-354f233f9818
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884687809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.
3884687809
Directory /workspace/7.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2450146983
Short name T1287
Test name
Test status
Simulation time 56214259766 ps
CPU time 879.94 seconds
Started Jan 03 02:07:30 PM PST 24
Finished Jan 03 02:22:19 PM PST 24
Peak memory 553980 kb
Host smart-a4334157-12b7-44a8-abcf-96601c729fc0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450146983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d
evice_slow_rsp.2450146983
Directory /workspace/7.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.4141014094
Short name T424
Test name
Test status
Simulation time 1262228173 ps
CPU time 46.25 seconds
Started Jan 03 02:07:43 PM PST 24
Finished Jan 03 02:08:41 PM PST 24
Peak memory 553864 kb
Host smart-743e6f90-1b37-4ea1-8fb6-7ce717ce6e11
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141014094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr
.4141014094
Directory /workspace/7.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_error_random.3019344008
Short name T1043
Test name
Test status
Simulation time 2547694594 ps
CPU time 84.32 seconds
Started Jan 03 02:08:05 PM PST 24
Finished Jan 03 02:09:37 PM PST 24
Peak memory 554184 kb
Host smart-ccd38d3c-1fda-4289-af76-c244bd08fc4d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019344008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3019344008
Directory /workspace/7.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random.1139885313
Short name T1168
Test name
Test status
Simulation time 1866748512 ps
CPU time 65.54 seconds
Started Jan 03 02:07:26 PM PST 24
Finished Jan 03 02:08:42 PM PST 24
Peak memory 554188 kb
Host smart-3d7c4508-7f70-441e-8abe-f1a7eda361d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139885313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.1139885313
Directory /workspace/7.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.2234060734
Short name T249
Test name
Test status
Simulation time 6624846934 ps
CPU time 68.82 seconds
Started Jan 03 02:07:32 PM PST 24
Finished Jan 03 02:08:51 PM PST 24
Peak memory 551716 kb
Host smart-9265e883-15fb-43ff-8a7a-be85fb3f95c8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234060734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2234060734
Directory /workspace/7.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.2313099441
Short name T659
Test name
Test status
Simulation time 55637026499 ps
CPU time 859.07 seconds
Started Jan 03 02:07:24 PM PST 24
Finished Jan 03 02:21:55 PM PST 24
Peak memory 554060 kb
Host smart-f8db2a2d-49d3-4161-8af7-a3d0b2e3675a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313099441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2313099441
Directory /workspace/7.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.3324425639
Short name T1358
Test name
Test status
Simulation time 341035049 ps
CPU time 28.95 seconds
Started Jan 03 02:07:24 PM PST 24
Finished Jan 03 02:08:05 PM PST 24
Peak memory 554100 kb
Host smart-5862616f-9e26-4d63-a07a-bd9a161b9199
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324425639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela
ys.3324425639
Directory /workspace/7.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_same_source.3034805734
Short name T185
Test name
Test status
Simulation time 2297851633 ps
CPU time 63.99 seconds
Started Jan 03 02:07:29 PM PST 24
Finished Jan 03 02:08:42 PM PST 24
Peak memory 553920 kb
Host smart-8479e053-87dd-4f94-92a6-34cfbc69798e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034805734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3034805734
Directory /workspace/7.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke.434065868
Short name T847
Test name
Test status
Simulation time 38493392 ps
CPU time 5.49 seconds
Started Jan 03 02:07:43 PM PST 24
Finished Jan 03 02:08:00 PM PST 24
Peak memory 552052 kb
Host smart-05d3295b-5225-43f6-9380-e02f15ad9054
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434065868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.434065868
Directory /workspace/7.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.808948352
Short name T821
Test name
Test status
Simulation time 6736921897 ps
CPU time 71.17 seconds
Started Jan 03 02:07:31 PM PST 24
Finished Jan 03 02:08:52 PM PST 24
Peak memory 551832 kb
Host smart-36c9136c-f281-4f20-84da-09e3989aea46
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808948352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.808948352
Directory /workspace/7.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.25175478
Short name T1578
Test name
Test status
Simulation time 3865943553 ps
CPU time 62.31 seconds
Started Jan 03 02:07:32 PM PST 24
Finished Jan 03 02:08:44 PM PST 24
Peak memory 551804 kb
Host smart-e7008e44-48ad-4689-94f9-9488fcc1e1a6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25175478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.25175478
Directory /workspace/7.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3154977879
Short name T1558
Test name
Test status
Simulation time 37096979 ps
CPU time 5.15 seconds
Started Jan 03 02:08:07 PM PST 24
Finished Jan 03 02:08:18 PM PST 24
Peak memory 552060 kb
Host smart-2cd214a5-8a42-453e-8dda-75271d041a84
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154977879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays
.3154977879
Directory /workspace/7.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all.1651681396
Short name T236
Test name
Test status
Simulation time 825956998 ps
CPU time 72.63 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:08:59 PM PST 24
Peak memory 555028 kb
Host smart-5b51430d-abea-4519-a1f9-e698c4ffed39
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651681396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1651681396
Directory /workspace/7.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.1533127149
Short name T1492
Test name
Test status
Simulation time 9390640814 ps
CPU time 312.21 seconds
Started Jan 03 02:07:25 PM PST 24
Finished Jan 03 02:12:49 PM PST 24
Peak memory 555048 kb
Host smart-2425c2b8-cda2-4cb5-8d0f-8ccd10acd82b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533127149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1533127149
Directory /workspace/7.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3803442176
Short name T1092
Test name
Test status
Simulation time 6130641270 ps
CPU time 384.47 seconds
Started Jan 03 02:07:36 PM PST 24
Finished Jan 03 02:14:12 PM PST 24
Peak memory 557700 kb
Host smart-815e267c-151b-403d-9951-e84acca7568c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803442176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_
with_rand_reset.3803442176
Directory /workspace/7.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.1794815101
Short name T1158
Test name
Test status
Simulation time 11587428854 ps
CPU time 574.78 seconds
Started Jan 03 02:07:24 PM PST 24
Finished Jan 03 02:17:10 PM PST 24
Peak memory 559180 kb
Host smart-50eed7c5-4705-493c-b2e7-a3beb86c70a7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794815101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all
_with_reset_error.1794815101
Directory /workspace/7.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.1204887721
Short name T234
Test name
Test status
Simulation time 74685127 ps
CPU time 6.2 seconds
Started Jan 03 02:07:44 PM PST 24
Finished Jan 03 02:08:02 PM PST 24
Peak memory 551732 kb
Host smart-8bc4bad0-93e1-4371-bad9-d4a3e76d4512
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204887721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1204887721
Directory /workspace/7.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_access_same_device.877260327
Short name T111
Test name
Test status
Simulation time 518068101 ps
CPU time 46.8 seconds
Started Jan 03 02:11:44 PM PST 24
Finished Jan 03 02:12:47 PM PST 24
Peak memory 554280 kb
Host smart-c18ddacc-8c9e-4d2d-9f52-94d014d196a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877260327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device.
877260327
Directory /workspace/70.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2684922686
Short name T300
Test name
Test status
Simulation time 37598884472 ps
CPU time 644.07 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:22:35 PM PST 24
Peak memory 554208 kb
Host smart-12fe1dd6-4b48-45ab-bf71-561fbaaa2e4e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684922686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_
device_slow_rsp.2684922686
Directory /workspace/70.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3399337094
Short name T722
Test name
Test status
Simulation time 728010312 ps
CPU time 33.05 seconds
Started Jan 03 02:11:38 PM PST 24
Finished Jan 03 02:12:27 PM PST 24
Peak memory 553836 kb
Host smart-c2b9ae2f-df5e-45c5-826c-2368b3454fc6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399337094 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add
r.3399337094
Directory /workspace/70.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_error_random.3547575705
Short name T871
Test name
Test status
Simulation time 1144405398 ps
CPU time 35.66 seconds
Started Jan 03 02:11:33 PM PST 24
Finished Jan 03 02:12:18 PM PST 24
Peak memory 553884 kb
Host smart-19e6a327-c654-4a76-94bf-ffd600a0c420
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547575705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.3547575705
Directory /workspace/70.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random.2667933398
Short name T1505
Test name
Test status
Simulation time 1013433894 ps
CPU time 37.05 seconds
Started Jan 03 02:11:20 PM PST 24
Finished Jan 03 02:12:11 PM PST 24
Peak memory 553072 kb
Host smart-16bb170e-dbe5-4cf1-814e-bb01cf74210e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667933398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.2667933398
Directory /workspace/70.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.2240585062
Short name T849
Test name
Test status
Simulation time 50892864560 ps
CPU time 532 seconds
Started Jan 03 02:11:23 PM PST 24
Finished Jan 03 02:20:27 PM PST 24
Peak memory 554196 kb
Host smart-64406296-5e9a-4471-9a7b-267714a78148
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240585062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.2240585062
Directory /workspace/70.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.4241017150
Short name T951
Test name
Test status
Simulation time 26204362137 ps
CPU time 476.38 seconds
Started Jan 03 02:11:20 PM PST 24
Finished Jan 03 02:19:30 PM PST 24
Peak memory 553932 kb
Host smart-b8a4939b-7ee0-4891-acd9-4ac6c0439a4d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241017150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.4241017150
Directory /workspace/70.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.698652516
Short name T67
Test name
Test status
Simulation time 367267864 ps
CPU time 34.38 seconds
Started Jan 03 02:11:33 PM PST 24
Finished Jan 03 02:12:17 PM PST 24
Peak memory 554108 kb
Host smart-5f1bd8f3-f6cb-42cc-8989-e38d4b521c6e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698652516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_dela
ys.698652516
Directory /workspace/70.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_same_source.656120618
Short name T808
Test name
Test status
Simulation time 413020264 ps
CPU time 29.35 seconds
Started Jan 03 02:11:23 PM PST 24
Finished Jan 03 02:12:05 PM PST 24
Peak memory 553896 kb
Host smart-dbbfb64e-e096-4628-8e59-5dc7d226d16b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656120618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.656120618
Directory /workspace/70.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke.2465850550
Short name T665
Test name
Test status
Simulation time 38147547 ps
CPU time 5.83 seconds
Started Jan 03 02:11:31 PM PST 24
Finished Jan 03 02:11:46 PM PST 24
Peak memory 551736 kb
Host smart-6bf884f8-169b-4324-ab5c-1efc26a7c600
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465850550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.2465850550
Directory /workspace/70.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.2471998124
Short name T468
Test name
Test status
Simulation time 9685098002 ps
CPU time 100.19 seconds
Started Jan 03 02:11:19 PM PST 24
Finished Jan 03 02:13:14 PM PST 24
Peak memory 551824 kb
Host smart-27c4f4b9-31e7-4883-ba68-0cc70eddbd7e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471998124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.2471998124
Directory /workspace/70.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.1052491089
Short name T583
Test name
Test status
Simulation time 4692249512 ps
CPU time 76.23 seconds
Started Jan 03 02:11:30 PM PST 24
Finished Jan 03 02:12:56 PM PST 24
Peak memory 551852 kb
Host smart-3e80e271-3664-4095-9294-e79357ea4cba
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052491089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.1052491089
Directory /workspace/70.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1266555586
Short name T1032
Test name
Test status
Simulation time 43479022 ps
CPU time 6.38 seconds
Started Jan 03 02:11:19 PM PST 24
Finished Jan 03 02:11:40 PM PST 24
Peak memory 551736 kb
Host smart-de8e8d47-04b5-454d-9d4f-46339d9c01ed
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266555586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay
s.1266555586
Directory /workspace/70.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all.2469325119
Short name T1727
Test name
Test status
Simulation time 11614453324 ps
CPU time 442.05 seconds
Started Jan 03 02:11:35 PM PST 24
Finished Jan 03 02:19:07 PM PST 24
Peak memory 555576 kb
Host smart-40bc7f55-e428-4319-8547-1c6ac3afc676
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469325119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.2469325119
Directory /workspace/70.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.1357478914
Short name T1067
Test name
Test status
Simulation time 7010298512 ps
CPU time 222.65 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:15:33 PM PST 24
Peak memory 555340 kb
Host smart-f9e1437c-cb4b-4acb-b0e5-59941b5175c3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357478914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.1357478914
Directory /workspace/70.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3947489997
Short name T1453
Test name
Test status
Simulation time 541135382 ps
CPU time 220.63 seconds
Started Jan 03 02:11:36 PM PST 24
Finished Jan 03 02:15:28 PM PST 24
Peak memory 556464 kb
Host smart-00a2e87b-73d9-4e61-b5e7-b59b758e9419
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947489997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all
_with_rand_reset.3947489997
Directory /workspace/70.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.1013748904
Short name T1664
Test name
Test status
Simulation time 664607934 ps
CPU time 165.24 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:14:36 PM PST 24
Peak memory 556940 kb
Host smart-395dc7b6-692a-4713-9bc3-aec11f887836
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013748904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al
l_with_reset_error.1013748904
Directory /workspace/70.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.966606931
Short name T438
Test name
Test status
Simulation time 617136732 ps
CPU time 26.51 seconds
Started Jan 03 02:11:34 PM PST 24
Finished Jan 03 02:12:10 PM PST 24
Peak memory 554264 kb
Host smart-804091a8-bcd3-44ba-912a-f46f4cb9c313
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966606931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.966606931
Directory /workspace/70.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_access_same_device.466077336
Short name T1614
Test name
Test status
Simulation time 1011837369 ps
CPU time 41.89 seconds
Started Jan 03 02:11:40 PM PST 24
Finished Jan 03 02:12:39 PM PST 24
Peak memory 554136 kb
Host smart-86b4d8a8-fb9a-4871-9081-f441945f99a1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466077336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device.
466077336
Directory /workspace/71.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.3989594380
Short name T971
Test name
Test status
Simulation time 126372714897 ps
CPU time 2087.14 seconds
Started Jan 03 02:11:52 PM PST 24
Finished Jan 03 02:46:51 PM PST 24
Peak memory 555080 kb
Host smart-8ed01566-a2d9-49b0-8f75-800ba2433f6f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989594380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_
device_slow_rsp.3989594380
Directory /workspace/71.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.752858034
Short name T937
Test name
Test status
Simulation time 96466607 ps
CPU time 11.76 seconds
Started Jan 03 02:11:43 PM PST 24
Finished Jan 03 02:12:11 PM PST 24
Peak memory 553864 kb
Host smart-0d12380c-b0cc-4d1d-9d4e-d356165ae6d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752858034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr
.752858034
Directory /workspace/71.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_error_random.1624890742
Short name T753
Test name
Test status
Simulation time 329138806 ps
CPU time 22.68 seconds
Started Jan 03 02:11:40 PM PST 24
Finished Jan 03 02:12:19 PM PST 24
Peak memory 552860 kb
Host smart-90bd7c22-ab8f-40f8-b80d-1fde2b9c3d1e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624890742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.1624890742
Directory /workspace/71.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random.1492078722
Short name T1319
Test name
Test status
Simulation time 2507148833 ps
CPU time 96.9 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:13:25 PM PST 24
Peak memory 553180 kb
Host smart-ce8a756b-1f5b-402e-815e-5dd5317019c1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492078722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.1492078722
Directory /workspace/71.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.819803316
Short name T529
Test name
Test status
Simulation time 12299213624 ps
CPU time 121.08 seconds
Started Jan 03 02:11:44 PM PST 24
Finished Jan 03 02:14:01 PM PST 24
Peak memory 551900 kb
Host smart-7be09e2c-bfc7-439d-b47f-d3be2d153a30
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819803316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.819803316
Directory /workspace/71.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.4270705847
Short name T1343
Test name
Test status
Simulation time 37939198448 ps
CPU time 626.73 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:22:18 PM PST 24
Peak memory 554204 kb
Host smart-ef3920e8-800e-41c5-914a-ce60bc790c18
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270705847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.4270705847
Directory /workspace/71.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.1518023267
Short name T456
Test name
Test status
Simulation time 102298591 ps
CPU time 12.2 seconds
Started Jan 03 02:11:40 PM PST 24
Finished Jan 03 02:12:09 PM PST 24
Peak memory 553884 kb
Host smart-81556d66-dc81-45df-b2d8-e5a1028ad6ac
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518023267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del
ays.1518023267
Directory /workspace/71.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_same_source.2643167527
Short name T1559
Test name
Test status
Simulation time 1330915990 ps
CPU time 35.37 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:12:25 PM PST 24
Peak memory 553860 kb
Host smart-749253b2-237d-4998-aa0a-c49b460c1643
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643167527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.2643167527
Directory /workspace/71.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke.3522110759
Short name T1830
Test name
Test status
Simulation time 191093106 ps
CPU time 8.39 seconds
Started Jan 03 02:11:36 PM PST 24
Finished Jan 03 02:11:56 PM PST 24
Peak memory 552084 kb
Host smart-01ce182d-a470-43ec-be51-903f3170e3a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522110759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.3522110759
Directory /workspace/71.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.2615002063
Short name T255
Test name
Test status
Simulation time 10082846909 ps
CPU time 96.79 seconds
Started Jan 03 02:11:38 PM PST 24
Finished Jan 03 02:13:31 PM PST 24
Peak memory 551960 kb
Host smart-6be502a5-41f3-4627-af6a-6f63abb051fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615002063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.2615002063
Directory /workspace/71.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1229410237
Short name T1244
Test name
Test status
Simulation time 5729217674 ps
CPU time 93.65 seconds
Started Jan 03 02:11:35 PM PST 24
Finished Jan 03 02:13:19 PM PST 24
Peak memory 551852 kb
Host smart-43a6a6e5-6a00-4412-bd6d-afff56c683e7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229410237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.1229410237
Directory /workspace/71.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1473444686
Short name T606
Test name
Test status
Simulation time 47300486 ps
CPU time 5.83 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:11:57 PM PST 24
Peak memory 551812 kb
Host smart-93af2c43-a02b-486e-9dc3-8a089fba19ea
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473444686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay
s.1473444686
Directory /workspace/71.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all.4000020979
Short name T747
Test name
Test status
Simulation time 5739945465 ps
CPU time 182.49 seconds
Started Jan 03 02:11:44 PM PST 24
Finished Jan 03 02:15:02 PM PST 24
Peak memory 555612 kb
Host smart-3d050075-cdf2-498a-ba30-5b86c4ba19e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000020979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.4000020979
Directory /workspace/71.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.2231570181
Short name T631
Test name
Test status
Simulation time 15394097400 ps
CPU time 505.95 seconds
Started Jan 03 02:11:47 PM PST 24
Finished Jan 03 02:20:28 PM PST 24
Peak memory 555352 kb
Host smart-a24d4ff3-ecf4-4432-846f-f51b09fb6ae8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231570181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.2231570181
Directory /workspace/71.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.4196648984
Short name T119
Test name
Test status
Simulation time 550961601 ps
CPU time 255.7 seconds
Started Jan 03 02:11:43 PM PST 24
Finished Jan 03 02:16:15 PM PST 24
Peak memory 556896 kb
Host smart-90cac534-9b8b-465b-a9da-69475044b87e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196648984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all
_with_rand_reset.4196648984
Directory /workspace/71.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.101106016
Short name T593
Test name
Test status
Simulation time 1955913393 ps
CPU time 161.11 seconds
Started Jan 03 02:11:42 PM PST 24
Finished Jan 03 02:14:39 PM PST 24
Peak memory 556316 kb
Host smart-06309f85-7c3f-4c64-a428-3868807ad7d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101106016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all
_with_reset_error.101106016
Directory /workspace/71.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.3798265004
Short name T824
Test name
Test status
Simulation time 604120539 ps
CPU time 26.43 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:12:17 PM PST 24
Peak memory 554196 kb
Host smart-f534b66a-3638-41f9-a1be-bc367c49dbbb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798265004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.3798265004
Directory /workspace/71.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_access_same_device.2508636998
Short name T291
Test name
Test status
Simulation time 1981773825 ps
CPU time 87.96 seconds
Started Jan 03 02:11:54 PM PST 24
Finished Jan 03 02:13:33 PM PST 24
Peak memory 554136 kb
Host smart-17b3b648-b778-4ace-bd59-95abe234fd00
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508636998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device
.2508636998
Directory /workspace/72.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.603704203
Short name T1772
Test name
Test status
Simulation time 723028074 ps
CPU time 29.42 seconds
Started Jan 03 02:11:19 PM PST 24
Finished Jan 03 02:12:03 PM PST 24
Peak memory 554168 kb
Host smart-d7823e53-f6e7-41f3-baa4-897186f303e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603704203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_addr
.603704203
Directory /workspace/72.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_error_random.2759135137
Short name T1448
Test name
Test status
Simulation time 1996609515 ps
CPU time 63.91 seconds
Started Jan 03 02:11:38 PM PST 24
Finished Jan 03 02:12:56 PM PST 24
Peak memory 554068 kb
Host smart-ddd09248-4541-4c1c-9d6b-58b20f3ab69e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759135137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.2759135137
Directory /workspace/72.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random.1870307060
Short name T851
Test name
Test status
Simulation time 502923852 ps
CPU time 38.77 seconds
Started Jan 03 02:11:40 PM PST 24
Finished Jan 03 02:12:35 PM PST 24
Peak memory 554124 kb
Host smart-179aa806-f664-48fc-a249-5cbc01dacd73
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870307060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.1870307060
Directory /workspace/72.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.98834420
Short name T1819
Test name
Test status
Simulation time 70954411975 ps
CPU time 720.78 seconds
Started Jan 03 02:11:40 PM PST 24
Finished Jan 03 02:23:57 PM PST 24
Peak memory 554160 kb
Host smart-5155f470-81d9-4c57-ab68-2be5b8ac297b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98834420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.98834420
Directory /workspace/72.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.1874677657
Short name T114
Test name
Test status
Simulation time 22172593180 ps
CPU time 332.49 seconds
Started Jan 03 02:11:55 PM PST 24
Finished Jan 03 02:17:38 PM PST 24
Peak memory 553112 kb
Host smart-c0715f3e-4ccb-4d10-b152-3ec80b937e5c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874677657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.1874677657
Directory /workspace/72.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.1201800031
Short name T1045
Test name
Test status
Simulation time 286190721 ps
CPU time 23.43 seconds
Started Jan 03 02:11:51 PM PST 24
Finished Jan 03 02:12:27 PM PST 24
Peak memory 554148 kb
Host smart-215ba4ed-de95-44ba-84ce-c54386b6efcc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201800031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del
ays.1201800031
Directory /workspace/72.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_same_source.3243272546
Short name T1780
Test name
Test status
Simulation time 2645163524 ps
CPU time 78.57 seconds
Started Jan 03 02:11:57 PM PST 24
Finished Jan 03 02:13:25 PM PST 24
Peak memory 554252 kb
Host smart-6041b86e-5ec0-4821-8f2c-647456abf926
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243272546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.3243272546
Directory /workspace/72.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke.2690555371
Short name T105
Test name
Test status
Simulation time 195350213 ps
CPU time 8.09 seconds
Started Jan 03 02:11:47 PM PST 24
Finished Jan 03 02:12:10 PM PST 24
Peak memory 552124 kb
Host smart-2a04cca6-6ca8-4cdd-8b5c-a2e523d82317
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690555371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.2690555371
Directory /workspace/72.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.2423805448
Short name T658
Test name
Test status
Simulation time 9616161075 ps
CPU time 96.52 seconds
Started Jan 03 02:11:32 PM PST 24
Finished Jan 03 02:13:17 PM PST 24
Peak memory 551836 kb
Host smart-a6e46e49-0e1f-42ef-aedd-0d1984dc29cc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423805448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.2423805448
Directory /workspace/72.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.3914761396
Short name T929
Test name
Test status
Simulation time 5928316493 ps
CPU time 99.77 seconds
Started Jan 03 02:11:55 PM PST 24
Finished Jan 03 02:13:46 PM PST 24
Peak memory 551836 kb
Host smart-7e119f63-0d4f-4b6d-96fb-fe9b540b1014
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914761396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.3914761396
Directory /workspace/72.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.634100417
Short name T466
Test name
Test status
Simulation time 46568199 ps
CPU time 5.9 seconds
Started Jan 03 02:11:41 PM PST 24
Finished Jan 03 02:12:03 PM PST 24
Peak memory 551992 kb
Host smart-f2ddded8-9d16-4817-8251-a668a45ad03b
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634100417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays
.634100417
Directory /workspace/72.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all.3704541975
Short name T1827
Test name
Test status
Simulation time 18928000480 ps
CPU time 627.1 seconds
Started Jan 03 02:11:31 PM PST 24
Finished Jan 03 02:22:07 PM PST 24
Peak memory 557252 kb
Host smart-1465a29d-0e35-42d1-9f08-dc2e6a7a66d9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704541975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.3704541975
Directory /workspace/72.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.2190907106
Short name T1385
Test name
Test status
Simulation time 2856127128 ps
CPU time 224.02 seconds
Started Jan 03 02:11:19 PM PST 24
Finished Jan 03 02:15:17 PM PST 24
Peak memory 555380 kb
Host smart-60faf07b-6f49-4be5-9839-2a9bc9777bc0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190907106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.2190907106
Directory /workspace/72.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2118096518
Short name T1763
Test name
Test status
Simulation time 175291222 ps
CPU time 80.73 seconds
Started Jan 03 02:11:31 PM PST 24
Finished Jan 03 02:13:01 PM PST 24
Peak memory 555360 kb
Host smart-60e701d3-5ff7-4b18-8781-72e6e39fc7f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118096518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all
_with_rand_reset.2118096518
Directory /workspace/72.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3125132753
Short name T308
Test name
Test status
Simulation time 449998658 ps
CPU time 120.38 seconds
Started Jan 03 02:11:35 PM PST 24
Finished Jan 03 02:13:46 PM PST 24
Peak memory 556216 kb
Host smart-84bad8bc-dd01-4a6a-b04a-9851393868c2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125132753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al
l_with_reset_error.3125132753
Directory /workspace/72.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.691521401
Short name T731
Test name
Test status
Simulation time 1170304067 ps
CPU time 45 seconds
Started Jan 03 02:11:22 PM PST 24
Finished Jan 03 02:12:20 PM PST 24
Peak memory 554240 kb
Host smart-35cb85a0-0866-41db-ba47-d16924e76dbc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691521401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.691521401
Directory /workspace/72.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_access_same_device.1667766014
Short name T1214
Test name
Test status
Simulation time 1337221537 ps
CPU time 53.56 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:12:41 PM PST 24
Peak memory 553184 kb
Host smart-7a82f675-639c-4bd9-8ce4-a72c567063d2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667766014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device
.1667766014
Directory /workspace/73.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.41673251
Short name T1260
Test name
Test status
Simulation time 13892826639 ps
CPU time 237.06 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:15:45 PM PST 24
Peak memory 554252 kb
Host smart-16488814-7d09-4e6c-aceb-a38ec519a949
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41673251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_de
vice_slow_rsp.41673251
Directory /workspace/73.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.917561215
Short name T1277
Test name
Test status
Simulation time 25374368 ps
CPU time 5.48 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:12:24 PM PST 24
Peak memory 551680 kb
Host smart-a590e0b4-8285-4dbf-a3a0-ad257949e363
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917561215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr
.917561215
Directory /workspace/73.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_error_random.2308629999
Short name T716
Test name
Test status
Simulation time 210799883 ps
CPU time 18.4 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:12:07 PM PST 24
Peak memory 554112 kb
Host smart-b67aa686-d7eb-4049-bf06-fabbab990266
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308629999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.2308629999
Directory /workspace/73.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random.170628843
Short name T76
Test name
Test status
Simulation time 1808719179 ps
CPU time 59.35 seconds
Started Jan 03 02:11:22 PM PST 24
Finished Jan 03 02:12:34 PM PST 24
Peak memory 553876 kb
Host smart-0402e3b6-3f31-40b8-955b-fc694f9d075d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170628843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.170628843
Directory /workspace/73.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.879989101
Short name T828
Test name
Test status
Simulation time 84833548027 ps
CPU time 939.77 seconds
Started Jan 03 02:11:39 PM PST 24
Finished Jan 03 02:27:35 PM PST 24
Peak memory 554256 kb
Host smart-8990282c-ea2f-4fc0-9b10-070c80a2ae72
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879989101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.879989101
Directory /workspace/73.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.2527072904
Short name T1414
Test name
Test status
Simulation time 39517403709 ps
CPU time 631.05 seconds
Started Jan 03 02:11:37 PM PST 24
Finished Jan 03 02:22:20 PM PST 24
Peak memory 553880 kb
Host smart-9685d531-bfe2-403f-9a16-7e61d64818b1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527072904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.2527072904
Directory /workspace/73.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.2471676375
Short name T1665
Test name
Test status
Simulation time 467525857 ps
CPU time 38.48 seconds
Started Jan 03 02:11:38 PM PST 24
Finished Jan 03 02:12:33 PM PST 24
Peak memory 554260 kb
Host smart-fdc5ea15-b602-4500-a196-b1763c7f43f7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471676375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del
ays.2471676375
Directory /workspace/73.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_same_source.1337754996
Short name T1396
Test name
Test status
Simulation time 1458821600 ps
CPU time 44.62 seconds
Started Jan 03 02:11:34 PM PST 24
Finished Jan 03 02:12:28 PM PST 24
Peak memory 553932 kb
Host smart-d3808061-6bd6-421f-9f39-a878bc02a9ae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337754996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.1337754996
Directory /workspace/73.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke.3311756957
Short name T1919
Test name
Test status
Simulation time 173522234 ps
CPU time 7.87 seconds
Started Jan 03 02:11:31 PM PST 24
Finished Jan 03 02:11:48 PM PST 24
Peak memory 551824 kb
Host smart-3ad202fd-c034-4f1d-86d3-b18a878188ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311756957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.3311756957
Directory /workspace/73.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.1576118125
Short name T1325
Test name
Test status
Simulation time 8056627917 ps
CPU time 90.88 seconds
Started Jan 03 02:11:36 PM PST 24
Finished Jan 03 02:13:18 PM PST 24
Peak memory 551952 kb
Host smart-bdbf4992-e0bf-456e-aeab-45c580e53f37
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576118125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.1576118125
Directory /workspace/73.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.293546703
Short name T724
Test name
Test status
Simulation time 4685685503 ps
CPU time 83.19 seconds
Started Jan 03 02:11:31 PM PST 24
Finished Jan 03 02:13:03 PM PST 24
Peak memory 551848 kb
Host smart-cc3761c8-bdb9-40fe-bc86-8ea31f6bdcf0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293546703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.293546703
Directory /workspace/73.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1789016910
Short name T691
Test name
Test status
Simulation time 46983475 ps
CPU time 6.34 seconds
Started Jan 03 02:11:20 PM PST 24
Finished Jan 03 02:11:40 PM PST 24
Peak memory 551752 kb
Host smart-68d135d2-90bb-4408-9530-1865e62a2d51
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789016910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay
s.1789016910
Directory /workspace/73.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all.21091344
Short name T720
Test name
Test status
Simulation time 1425614130 ps
CPU time 127.14 seconds
Started Jan 03 02:12:20 PM PST 24
Finished Jan 03 02:14:36 PM PST 24
Peak memory 555104 kb
Host smart-cca93025-69f8-456c-90d5-340c853616ef
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21091344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.21091344
Directory /workspace/73.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.3914108355
Short name T1890
Test name
Test status
Simulation time 1330910181 ps
CPU time 47.46 seconds
Started Jan 03 02:12:33 PM PST 24
Finished Jan 03 02:13:32 PM PST 24
Peak memory 554100 kb
Host smart-3c1e061e-3887-478b-a949-e6d6a0669221
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914108355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.3914108355
Directory /workspace/73.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.4136808296
Short name T47
Test name
Test status
Simulation time 2674997769 ps
CPU time 387.59 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:18:45 PM PST 24
Peak memory 557160 kb
Host smart-eeb1454d-d496-494a-9865-52d6580596fd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136808296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all
_with_rand_reset.4136808296
Directory /workspace/73.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3702137650
Short name T536
Test name
Test status
Simulation time 9075000782 ps
CPU time 849.52 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:26:33 PM PST 24
Peak memory 559180 kb
Host smart-e72ea3ad-c8d1-4cf1-8f28-f5c4c6a4fb0a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702137650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al
l_with_reset_error.3702137650
Directory /workspace/73.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.760400546
Short name T1729
Test name
Test status
Simulation time 68064995 ps
CPU time 10.91 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:12:29 PM PST 24
Peak memory 554172 kb
Host smart-8933297d-eeb7-4e67-982e-974f2ed061c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760400546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.760400546
Directory /workspace/73.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_access_same_device.223938373
Short name T315
Test name
Test status
Simulation time 1694399251 ps
CPU time 66.37 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:13:30 PM PST 24
Peak memory 554244 kb
Host smart-d0f5f40b-6c6b-473a-b197-2bbde69cd739
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223938373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device.
223938373
Directory /workspace/74.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.3658830156
Short name T1498
Test name
Test status
Simulation time 23094082608 ps
CPU time 406.88 seconds
Started Jan 03 02:12:32 PM PST 24
Finished Jan 03 02:19:30 PM PST 24
Peak memory 554248 kb
Host smart-a56743df-dfd8-43e7-a286-ccfe6d914e3c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658830156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_
device_slow_rsp.3658830156
Directory /workspace/74.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3895102699
Short name T391
Test name
Test status
Simulation time 68560999 ps
CPU time 6.08 seconds
Started Jan 03 02:12:32 PM PST 24
Finished Jan 03 02:12:50 PM PST 24
Peak memory 551636 kb
Host smart-b483b062-d743-434c-bd41-79016e6c0fbd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895102699 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add
r.3895102699
Directory /workspace/74.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_error_random.2191387152
Short name T781
Test name
Test status
Simulation time 1826650092 ps
CPU time 68.72 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:13:33 PM PST 24
Peak memory 554232 kb
Host smart-ca16af45-1249-4ca4-82e4-2d2b45ec8ad0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191387152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.2191387152
Directory /workspace/74.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random.2627337384
Short name T497
Test name
Test status
Simulation time 819484314 ps
CPU time 28.74 seconds
Started Jan 03 02:12:21 PM PST 24
Finished Jan 03 02:12:59 PM PST 24
Peak memory 554176 kb
Host smart-bd433da6-794a-46a4-8b81-ae393ce41016
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627337384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.2627337384
Directory /workspace/74.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.2328412840
Short name T1844
Test name
Test status
Simulation time 70983228077 ps
CPU time 689.97 seconds
Started Jan 03 02:12:19 PM PST 24
Finished Jan 03 02:23:56 PM PST 24
Peak memory 554020 kb
Host smart-5ef67946-64c8-4e41-bd6e-3b6dccb81b4a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328412840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.2328412840
Directory /workspace/74.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.400693136
Short name T1732
Test name
Test status
Simulation time 13744070847 ps
CPU time 232.92 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:16:44 PM PST 24
Peak memory 554184 kb
Host smart-7842d01f-19d8-41f8-9fe9-2f89aedf4500
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400693136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.400693136
Directory /workspace/74.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.712258038
Short name T1823
Test name
Test status
Simulation time 256203884 ps
CPU time 23.16 seconds
Started Jan 03 02:12:21 PM PST 24
Finished Jan 03 02:12:53 PM PST 24
Peak memory 554164 kb
Host smart-5dff6aa2-7663-4e02-b1d2-bb12cab4c919
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712258038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_dela
ys.712258038
Directory /workspace/74.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_same_source.3509232879
Short name T587
Test name
Test status
Simulation time 536272353 ps
CPU time 35.68 seconds
Started Jan 03 02:12:19 PM PST 24
Finished Jan 03 02:13:02 PM PST 24
Peak memory 554188 kb
Host smart-08dbfd0a-9da8-4c07-a472-83f0011e37b8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509232879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.3509232879
Directory /workspace/74.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke.157518099
Short name T737
Test name
Test status
Simulation time 240890282 ps
CPU time 9.64 seconds
Started Jan 03 02:12:18 PM PST 24
Finished Jan 03 02:12:34 PM PST 24
Peak memory 552064 kb
Host smart-9b6b8a6a-7eca-4b88-920a-e5f50d218ef0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157518099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.157518099
Directory /workspace/74.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.2004275829
Short name T1529
Test name
Test status
Simulation time 7259263476 ps
CPU time 82.69 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:13:44 PM PST 24
Peak memory 551728 kb
Host smart-107f27f7-f361-4184-a798-d22bc01923dd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004275829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.2004275829
Directory /workspace/74.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1180849918
Short name T916
Test name
Test status
Simulation time 6010695652 ps
CPU time 101.84 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:13:59 PM PST 24
Peak memory 552116 kb
Host smart-8ced0434-b512-4c5c-a52d-05a018b01bd4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180849918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.1180849918
Directory /workspace/74.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3151614026
Short name T1480
Test name
Test status
Simulation time 57193005 ps
CPU time 6.64 seconds
Started Jan 03 02:12:31 PM PST 24
Finished Jan 03 02:12:47 PM PST 24
Peak memory 551792 kb
Host smart-aa0ed7fa-42a1-414c-9a2a-381dcc90f93d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151614026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay
s.3151614026
Directory /workspace/74.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all.2409809387
Short name T1367
Test name
Test status
Simulation time 4689525099 ps
CPU time 167.45 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:15:37 PM PST 24
Peak memory 555144 kb
Host smart-25ea54cd-0305-4db2-be48-e50e8b20ed74
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409809387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2409809387
Directory /workspace/74.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.4250613278
Short name T864
Test name
Test status
Simulation time 3693524297 ps
CPU time 257.91 seconds
Started Jan 03 02:12:39 PM PST 24
Finished Jan 03 02:17:13 PM PST 24
Peak memory 555176 kb
Host smart-8bb617a8-1803-45d4-ad5a-109ed115435d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250613278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.4250613278
Directory /workspace/74.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1204155302
Short name T995
Test name
Test status
Simulation time 2893316866 ps
CPU time 567.47 seconds
Started Jan 03 02:12:22 PM PST 24
Finished Jan 03 02:22:00 PM PST 24
Peak memory 559040 kb
Host smart-d02b6364-6f60-44cc-8e8c-c42b3d4797e0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204155302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all
_with_rand_reset.1204155302
Directory /workspace/74.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.2303646743
Short name T798
Test name
Test status
Simulation time 2169040157 ps
CPU time 146.31 seconds
Started Jan 03 02:12:22 PM PST 24
Finished Jan 03 02:14:58 PM PST 24
Peak memory 555432 kb
Host smart-628ba79b-0d88-4a0e-bc0b-eed650425f6b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303646743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al
l_with_reset_error.2303646743
Directory /workspace/74.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.3865254072
Short name T944
Test name
Test status
Simulation time 1260636368 ps
CPU time 50.39 seconds
Started Jan 03 02:12:34 PM PST 24
Finished Jan 03 02:13:36 PM PST 24
Peak memory 554164 kb
Host smart-bd65de99-b0fa-4c02-a677-eab6cb06b7b6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865254072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.3865254072
Directory /workspace/74.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_access_same_device.2221322108
Short name T819
Test name
Test status
Simulation time 546073707 ps
CPU time 40.25 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:13:55 PM PST 24
Peak memory 554188 kb
Host smart-68a3486c-2e03-4c85-9a5c-5905b42e1984
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221322108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device
.2221322108
Directory /workspace/75.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1714178588
Short name T474
Test name
Test status
Simulation time 2763337769 ps
CPU time 43.33 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:14:00 PM PST 24
Peak memory 552168 kb
Host smart-412a94fb-0aac-4f2e-b61d-15d700abc0b8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714178588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_
device_slow_rsp.1714178588
Directory /workspace/75.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.2626692610
Short name T541
Test name
Test status
Simulation time 244253916 ps
CPU time 24.16 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:13:38 PM PST 24
Peak memory 553872 kb
Host smart-94591747-8f0c-4de3-a74b-2e6c0f9dc9dc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626692610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add
r.2626692610
Directory /workspace/75.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_error_random.196555773
Short name T566
Test name
Test status
Simulation time 2482149046 ps
CPU time 78.82 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:14:33 PM PST 24
Peak memory 553948 kb
Host smart-46657949-e4af-49b9-9fea-6c279c0ec8a3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196555773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.196555773
Directory /workspace/75.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random.2335782181
Short name T1689
Test name
Test status
Simulation time 1705135968 ps
CPU time 52.86 seconds
Started Jan 03 02:12:53 PM PST 24
Finished Jan 03 02:14:02 PM PST 24
Peak memory 554128 kb
Host smart-c2385e44-f887-4c8b-b1a3-5e5f9ea2ba94
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335782181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.2335782181
Directory /workspace/75.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.973974704
Short name T528
Test name
Test status
Simulation time 80513536223 ps
CPU time 784.74 seconds
Started Jan 03 02:12:35 PM PST 24
Finished Jan 03 02:25:53 PM PST 24
Peak memory 553992 kb
Host smart-c9ca5eb4-c5b7-4ae9-9049-1dee7be81a8f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973974704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.973974704
Directory /workspace/75.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3319548079
Short name T1119
Test name
Test status
Simulation time 52535277968 ps
CPU time 877.76 seconds
Started Jan 03 02:12:34 PM PST 24
Finished Jan 03 02:27:23 PM PST 24
Peak memory 554252 kb
Host smart-3204a2cc-794a-4c74-ab30-d6065358f313
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319548079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3319548079
Directory /workspace/75.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.974116074
Short name T89
Test name
Test status
Simulation time 312546279 ps
CPU time 26.44 seconds
Started Jan 03 02:12:45 PM PST 24
Finished Jan 03 02:13:28 PM PST 24
Peak memory 553896 kb
Host smart-e292a922-b0f3-4023-87bf-12f15313dc91
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974116074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_dela
ys.974116074
Directory /workspace/75.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_same_source.2166330709
Short name T1459
Test name
Test status
Simulation time 687169519 ps
CPU time 20.4 seconds
Started Jan 03 02:12:43 PM PST 24
Finished Jan 03 02:13:19 PM PST 24
Peak memory 554184 kb
Host smart-1d2848ee-f245-43b2-8826-9db61026de7f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166330709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.2166330709
Directory /workspace/75.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke.1059676547
Short name T1068
Test name
Test status
Simulation time 41970341 ps
CPU time 5.74 seconds
Started Jan 03 02:12:40 PM PST 24
Finished Jan 03 02:13:02 PM PST 24
Peak memory 552076 kb
Host smart-ee00149b-4848-4530-a3a7-c77ed89638bf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059676547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.1059676547
Directory /workspace/75.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.2486624320
Short name T411
Test name
Test status
Simulation time 7503039687 ps
CPU time 80.65 seconds
Started Jan 03 02:12:21 PM PST 24
Finished Jan 03 02:13:52 PM PST 24
Peak memory 552184 kb
Host smart-87c3bb7e-5059-4701-8d42-fe84af96ef23
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486624320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.2486624320
Directory /workspace/75.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.335632874
Short name T1826
Test name
Test status
Simulation time 5117398535 ps
CPU time 90.47 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:14:23 PM PST 24
Peak memory 551852 kb
Host smart-c4166a7e-3f74-4acf-956c-e4b229241117
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335632874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.335632874
Directory /workspace/75.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.1017174128
Short name T1207
Test name
Test status
Simulation time 43611393 ps
CPU time 5.84 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:12:58 PM PST 24
Peak memory 551792 kb
Host smart-8b4f3cbc-4d7a-4eca-8dc7-5eccae9136d3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017174128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay
s.1017174128
Directory /workspace/75.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all.1655705150
Short name T1454
Test name
Test status
Simulation time 2411271765 ps
CPU time 89.72 seconds
Started Jan 03 02:12:44 PM PST 24
Finished Jan 03 02:14:29 PM PST 24
Peak memory 554060 kb
Host smart-6decef18-4938-4f49-9197-3e81290e6df5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655705150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.1655705150
Directory /workspace/75.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.3000626737
Short name T1580
Test name
Test status
Simulation time 7977369823 ps
CPU time 244.32 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:17:19 PM PST 24
Peak memory 555104 kb
Host smart-b924763b-99a0-487c-88b6-fcd0362c0814
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000626737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.3000626737
Directory /workspace/75.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1400683023
Short name T1100
Test name
Test status
Simulation time 4835782079 ps
CPU time 187.13 seconds
Started Jan 03 02:12:52 PM PST 24
Finished Jan 03 02:16:15 PM PST 24
Peak memory 556084 kb
Host smart-a201b929-9b65-425e-aca7-12ef07a44ba8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400683023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al
l_with_reset_error.1400683023
Directory /workspace/75.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.533611399
Short name T1097
Test name
Test status
Simulation time 812798734 ps
CPU time 30.9 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:13:44 PM PST 24
Peak memory 554248 kb
Host smart-f156f80c-3593-47c3-8c29-25d8b5ac38f8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533611399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.533611399
Directory /workspace/75.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_access_same_device.3914043174
Short name T1661
Test name
Test status
Simulation time 1465630440 ps
CPU time 60.07 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:13:21 PM PST 24
Peak memory 554128 kb
Host smart-73148ea7-152d-453d-8e6b-b5d70e22c336
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914043174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device
.3914043174
Directory /workspace/76.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.4081030049
Short name T1189
Test name
Test status
Simulation time 123067215198 ps
CPU time 1886.21 seconds
Started Jan 03 02:12:15 PM PST 24
Finished Jan 03 02:43:46 PM PST 24
Peak memory 555348 kb
Host smart-5c3f9b06-b351-4cbf-aba7-5c98df8c3112
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081030049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_
device_slow_rsp.4081030049
Directory /workspace/76.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2152727153
Short name T723
Test name
Test status
Simulation time 238240562 ps
CPU time 24.96 seconds
Started Jan 03 02:12:15 PM PST 24
Finished Jan 03 02:12:44 PM PST 24
Peak memory 553820 kb
Host smart-0e8ec388-8287-44c7-ab12-81b71f9e6519
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152727153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add
r.2152727153
Directory /workspace/76.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_error_random.3213767296
Short name T1004
Test name
Test status
Simulation time 259836730 ps
CPU time 21.84 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:12:39 PM PST 24
Peak memory 554136 kb
Host smart-1b4b2d0c-d3d3-4f23-891c-7a6eb94b72e7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213767296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.3213767296
Directory /workspace/76.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random.4155534262
Short name T1424
Test name
Test status
Simulation time 1267817956 ps
CPU time 46.38 seconds
Started Jan 03 02:12:13 PM PST 24
Finished Jan 03 02:13:03 PM PST 24
Peak memory 554164 kb
Host smart-46b2d5b1-65e7-4d68-a62e-eb3806a0429d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155534262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.4155534262
Directory /workspace/76.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3107585580
Short name T1656
Test name
Test status
Simulation time 22703251273 ps
CPU time 239.36 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:16:24 PM PST 24
Peak memory 554324 kb
Host smart-032290e3-1b0d-4e1d-b897-2cf7e2e80e70
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107585580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3107585580
Directory /workspace/76.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.3881215009
Short name T188
Test name
Test status
Simulation time 49656295282 ps
CPU time 892.56 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:27:16 PM PST 24
Peak memory 554296 kb
Host smart-9af0bd3d-698a-4bf2-934b-36955c037ac8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881215009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.3881215009
Directory /workspace/76.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.3728842047
Short name T69
Test name
Test status
Simulation time 509536529 ps
CPU time 42.91 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:13:06 PM PST 24
Peak memory 553904 kb
Host smart-2eeedd4e-8bf3-4168-8cd0-b441bf7c0a4a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728842047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del
ays.3728842047
Directory /workspace/76.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_same_source.2060488180
Short name T78
Test name
Test status
Simulation time 2241367825 ps
CPU time 70.01 seconds
Started Jan 03 02:12:15 PM PST 24
Finished Jan 03 02:13:30 PM PST 24
Peak memory 553968 kb
Host smart-8d10a5fd-7652-46be-9b17-640941b210f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060488180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.2060488180
Directory /workspace/76.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke.4151051900
Short name T381
Test name
Test status
Simulation time 236255795 ps
CPU time 9.18 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:29 PM PST 24
Peak memory 552044 kb
Host smart-49a25ccf-09b1-4b59-9001-ae38820c1275
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151051900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.4151051900
Directory /workspace/76.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.3679108024
Short name T1506
Test name
Test status
Simulation time 6250715136 ps
CPU time 71.21 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:14:29 PM PST 24
Peak memory 551856 kb
Host smart-45733f9f-58d4-4a0b-b874-a0cd72e851d0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679108024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.3679108024
Directory /workspace/76.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.1022301372
Short name T697
Test name
Test status
Simulation time 4054535598 ps
CPU time 63.76 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:14:22 PM PST 24
Peak memory 551812 kb
Host smart-e89dfc48-372c-42b6-9e78-b3fab964c2fb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022301372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.1022301372
Directory /workspace/76.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.199424445
Short name T383
Test name
Test status
Simulation time 52037118 ps
CPU time 6.12 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:25 PM PST 24
Peak memory 552060 kb
Host smart-234ab577-68fe-44c6-af91-2f4275a1e889
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199424445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays
.199424445
Directory /workspace/76.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all.3444465413
Short name T72
Test name
Test status
Simulation time 8716684576 ps
CPU time 333.19 seconds
Started Jan 03 02:12:30 PM PST 24
Finished Jan 03 02:18:14 PM PST 24
Peak memory 555564 kb
Host smart-9637482e-2406-4596-928f-90a1859bc4e8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444465413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.3444465413
Directory /workspace/76.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.1791479368
Short name T1054
Test name
Test status
Simulation time 2284338392 ps
CPU time 160.82 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:15:32 PM PST 24
Peak memory 554096 kb
Host smart-d09850ff-a962-4e42-9abe-db4dc79eb500
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791479368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.1791479368
Directory /workspace/76.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3083743729
Short name T1821
Test name
Test status
Simulation time 4120753541 ps
CPU time 567.38 seconds
Started Jan 03 02:12:33 PM PST 24
Finished Jan 03 02:22:12 PM PST 24
Peak memory 559100 kb
Host smart-6c5c3189-8347-4151-9aea-f2ddf22b3bde
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083743729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all
_with_rand_reset.3083743729
Directory /workspace/76.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.3644908477
Short name T581
Test name
Test status
Simulation time 63915785 ps
CPU time 9.72 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:12:27 PM PST 24
Peak memory 553880 kb
Host smart-5c75c0dc-6070-4b57-8f9a-c420ab76fac5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644908477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.3644908477
Directory /workspace/76.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_access_same_device.1038567914
Short name T832
Test name
Test status
Simulation time 320810061 ps
CPU time 14.11 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:13:04 PM PST 24
Peak memory 553108 kb
Host smart-658a2869-2a8e-4c80-856d-1569f0d6f67a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038567914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device
.1038567914
Directory /workspace/77.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3720050792
Short name T1496
Test name
Test status
Simulation time 59941032931 ps
CPU time 989.12 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:29:20 PM PST 24
Peak memory 553916 kb
Host smart-82f1ac8a-a054-4798-a258-284b204cbadf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720050792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_
device_slow_rsp.3720050792
Directory /workspace/77.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.4009615687
Short name T1515
Test name
Test status
Simulation time 1338600201 ps
CPU time 48.36 seconds
Started Jan 03 02:12:53 PM PST 24
Finished Jan 03 02:13:57 PM PST 24
Peak memory 553844 kb
Host smart-55412e9d-482e-49bd-892c-8184e5bdda7b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009615687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add
r.4009615687
Directory /workspace/77.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_error_random.1981771246
Short name T504
Test name
Test status
Simulation time 2068017629 ps
CPU time 67.87 seconds
Started Jan 03 02:12:40 PM PST 24
Finished Jan 03 02:14:03 PM PST 24
Peak memory 553820 kb
Host smart-dd7ef6aa-68b2-4b13-858b-17b92fdb4cc7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981771246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.1981771246
Directory /workspace/77.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random.3033748979
Short name T1064
Test name
Test status
Simulation time 321655996 ps
CPU time 28.23 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:12:51 PM PST 24
Peak memory 554176 kb
Host smart-41f1c2fa-94ae-47dd-898f-a22cdd5fc511
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033748979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.3033748979
Directory /workspace/77.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.408616963
Short name T1306
Test name
Test status
Simulation time 78190587350 ps
CPU time 855.17 seconds
Started Jan 03 02:12:34 PM PST 24
Finished Jan 03 02:27:01 PM PST 24
Peak memory 554200 kb
Host smart-f24d2de4-a52b-4763-8f25-dc8055412c17
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408616963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.408616963
Directory /workspace/77.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.2216699190
Short name T1740
Test name
Test status
Simulation time 3505805182 ps
CPU time 57.96 seconds
Started Jan 03 02:12:35 PM PST 24
Finished Jan 03 02:13:46 PM PST 24
Peak memory 551736 kb
Host smart-047aaba8-7d40-4bef-b4c8-3d29b3660897
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216699190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.2216699190
Directory /workspace/77.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.483023776
Short name T1196
Test name
Test status
Simulation time 349621020 ps
CPU time 29.63 seconds
Started Jan 03 02:12:32 PM PST 24
Finished Jan 03 02:13:13 PM PST 24
Peak memory 553988 kb
Host smart-d5ddffed-1538-49f2-84b5-8ef0512840d2
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483023776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_dela
ys.483023776
Directory /workspace/77.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_same_source.1645360445
Short name T407
Test name
Test status
Simulation time 1452401064 ps
CPU time 40.22 seconds
Started Jan 03 02:12:35 PM PST 24
Finished Jan 03 02:13:28 PM PST 24
Peak memory 554172 kb
Host smart-ab565160-e685-45fd-88e5-ab59f57c4bd7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645360445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.1645360445
Directory /workspace/77.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke.3292232017
Short name T1146
Test name
Test status
Simulation time 218103947 ps
CPU time 9.14 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:12:33 PM PST 24
Peak memory 552012 kb
Host smart-95cef90c-98a8-4eaf-b99a-90a293b99621
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292232017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.3292232017
Directory /workspace/77.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.3143041951
Short name T1551
Test name
Test status
Simulation time 8411746332 ps
CPU time 99.3 seconds
Started Jan 03 02:12:25 PM PST 24
Finished Jan 03 02:14:15 PM PST 24
Peak memory 552156 kb
Host smart-7b0b732a-c364-469d-a4df-3f5dc4e81b2b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143041951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.3143041951
Directory /workspace/77.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1917432316
Short name T1883
Test name
Test status
Simulation time 3304854166 ps
CPU time 55.62 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:13:47 PM PST 24
Peak memory 551848 kb
Host smart-ce300470-6c75-4971-988b-86f50f5df98a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917432316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.1917432316
Directory /workspace/77.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.3551219618
Short name T1261
Test name
Test status
Simulation time 45620282 ps
CPU time 6.01 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:12:30 PM PST 24
Peak memory 552016 kb
Host smart-f529811e-18ee-4f9b-93be-b9bccfd7c043
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551219618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay
s.3551219618
Directory /workspace/77.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all.1195728958
Short name T333
Test name
Test status
Simulation time 4867589692 ps
CPU time 155.43 seconds
Started Jan 03 02:12:53 PM PST 24
Finished Jan 03 02:15:44 PM PST 24
Peak memory 556060 kb
Host smart-37ffe401-bc53-4f6a-9877-928a8dcd145f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195728958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.1195728958
Directory /workspace/77.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3603598800
Short name T1075
Test name
Test status
Simulation time 2893520047 ps
CPU time 184.03 seconds
Started Jan 03 02:12:44 PM PST 24
Finished Jan 03 02:16:04 PM PST 24
Peak memory 555148 kb
Host smart-934d07c6-f842-4bd1-8669-de5f000e7adb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603598800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.3603598800
Directory /workspace/77.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1042398300
Short name T663
Test name
Test status
Simulation time 220142614 ps
CPU time 96.08 seconds
Started Jan 03 02:12:53 PM PST 24
Finished Jan 03 02:14:45 PM PST 24
Peak memory 555044 kb
Host smart-6dbfa5e2-ca27-436f-9e3e-7badb2801317
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042398300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all
_with_rand_reset.1042398300
Directory /workspace/77.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.3733049479
Short name T748
Test name
Test status
Simulation time 8593869078 ps
CPU time 633.87 seconds
Started Jan 03 02:12:54 PM PST 24
Finished Jan 03 02:23:44 PM PST 24
Peak memory 574764 kb
Host smart-bc00d17e-9843-4c3f-8b1f-e095f46bba43
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733049479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al
l_with_reset_error.3733049479
Directory /workspace/77.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1109024735
Short name T389
Test name
Test status
Simulation time 67709073 ps
CPU time 9.77 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:13:03 PM PST 24
Peak memory 553072 kb
Host smart-95eba1d6-2414-4e56-b3b2-df02ac9a6040
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109024735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.1109024735
Directory /workspace/77.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_access_same_device.1317895015
Short name T701
Test name
Test status
Simulation time 741487082 ps
CPU time 30.37 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:13:47 PM PST 24
Peak memory 554108 kb
Host smart-ebdc3e08-b61b-4c71-8cbc-15deb88418f0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317895015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device
.1317895015
Directory /workspace/78.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2307356113
Short name T1791
Test name
Test status
Simulation time 38923256922 ps
CPU time 583.08 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:23:02 PM PST 24
Peak memory 553816 kb
Host smart-58e181d3-f8f3-4109-a3ab-1b0eaa5ebada
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307356113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_
device_slow_rsp.2307356113
Directory /workspace/78.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.1607412477
Short name T1442
Test name
Test status
Simulation time 1256966382 ps
CPU time 43.28 seconds
Started Jan 03 02:12:45 PM PST 24
Finished Jan 03 02:13:44 PM PST 24
Peak memory 554152 kb
Host smart-6bcdd8e2-34f0-474f-bcc7-344f4706b8f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607412477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add
r.1607412477
Directory /workspace/78.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_error_random.754366128
Short name T518
Test name
Test status
Simulation time 1219660085 ps
CPU time 42.08 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:13:58 PM PST 24
Peak memory 554056 kb
Host smart-df41bed9-ed2c-4bdc-aa85-8f15d40da287
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754366128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.754366128
Directory /workspace/78.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random.15230883
Short name T872
Test name
Test status
Simulation time 283075781 ps
CPU time 22.09 seconds
Started Jan 03 02:12:52 PM PST 24
Finished Jan 03 02:13:30 PM PST 24
Peak memory 553840 kb
Host smart-23fe886c-3c35-4ff5-a569-79067bbf8653
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15230883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.15230883
Directory /workspace/78.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.544295512
Short name T953
Test name
Test status
Simulation time 59303901222 ps
CPU time 614.64 seconds
Started Jan 03 02:12:45 PM PST 24
Finished Jan 03 02:23:15 PM PST 24
Peak memory 553932 kb
Host smart-51d9403c-890a-4f21-a2d9-d9e2cc8dc013
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544295512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.544295512
Directory /workspace/78.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.844918376
Short name T993
Test name
Test status
Simulation time 3730818358 ps
CPU time 60.43 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:14:20 PM PST 24
Peak memory 552096 kb
Host smart-97b63ef2-f136-4c38-84e3-97dc8256c41d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844918376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.844918376
Directory /workspace/78.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.1010700459
Short name T1631
Test name
Test status
Simulation time 383995258 ps
CPU time 32.3 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:53 PM PST 24
Peak memory 553828 kb
Host smart-a5912f4c-7ec5-49d2-a73c-1bbd71e70355
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010700459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del
ays.1010700459
Directory /workspace/78.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_same_source.3672698733
Short name T1174
Test name
Test status
Simulation time 154705999 ps
CPU time 11.96 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:31 PM PST 24
Peak memory 553836 kb
Host smart-a31b3461-a41d-498c-bb72-7cdd333ab870
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672698733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3672698733
Directory /workspace/78.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke.417604131
Short name T1604
Test name
Test status
Simulation time 45392518 ps
CPU time 5.8 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:13:19 PM PST 24
Peak memory 551828 kb
Host smart-17f57e9e-6850-45a2-b111-2e3801da1099
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417604131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.417604131
Directory /workspace/78.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.1633499040
Short name T1126
Test name
Test status
Simulation time 6001620458 ps
CPU time 64.06 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:14:17 PM PST 24
Peak memory 552124 kb
Host smart-fec55ef9-5b13-48d1-a89b-1939f92699f8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633499040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.1633499040
Directory /workspace/78.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.3473029820
Short name T1221
Test name
Test status
Simulation time 4903730680 ps
CPU time 89.69 seconds
Started Jan 03 02:12:52 PM PST 24
Finished Jan 03 02:14:38 PM PST 24
Peak memory 552072 kb
Host smart-05bfd1b8-5fdb-4ed9-8fb5-8502a0c29515
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473029820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.3473029820
Directory /workspace/78.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1933240859
Short name T1749
Test name
Test status
Simulation time 58141276 ps
CPU time 6.87 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:13:21 PM PST 24
Peak memory 552080 kb
Host smart-9db8f04c-74b1-4ebc-8761-54b1298dfe36
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933240859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay
s.1933240859
Directory /workspace/78.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all.2280739205
Short name T1807
Test name
Test status
Simulation time 10839180765 ps
CPU time 383.17 seconds
Started Jan 03 02:12:38 PM PST 24
Finished Jan 03 02:19:16 PM PST 24
Peak memory 556420 kb
Host smart-0240cd64-0603-437b-bbdc-c81f0c51b164
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280739205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.2280739205
Directory /workspace/78.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.3939498941
Short name T1751
Test name
Test status
Simulation time 2348737510 ps
CPU time 62.62 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:14:25 PM PST 24
Peak memory 553960 kb
Host smart-7fd6ca04-5fe9-4389-a4fe-109c8181bc24
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939498941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.3939498941
Directory /workspace/78.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1087979277
Short name T175
Test name
Test status
Simulation time 6214161833 ps
CPU time 687.73 seconds
Started Jan 03 02:12:38 PM PST 24
Finished Jan 03 02:24:22 PM PST 24
Peak memory 558320 kb
Host smart-d8d0d28f-130e-4a85-bd6c-b619f14dd288
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087979277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all
_with_rand_reset.1087979277
Directory /workspace/78.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.3622510458
Short name T1561
Test name
Test status
Simulation time 270679485 ps
CPU time 77.89 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:14:35 PM PST 24
Peak memory 555276 kb
Host smart-a0b6633a-6f0c-4408-a745-097a59dfb238
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622510458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al
l_with_reset_error.3622510458
Directory /workspace/78.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.4157665693
Short name T1582
Test name
Test status
Simulation time 72396629 ps
CPU time 10.39 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:13:29 PM PST 24
Peak memory 553912 kb
Host smart-0d3a3e23-790d-47fa-9ea3-242456ee4e8a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157665693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.4157665693
Directory /workspace/78.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_access_same_device.3496144699
Short name T850
Test name
Test status
Simulation time 853492898 ps
CPU time 29.96 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:12:48 PM PST 24
Peak memory 553128 kb
Host smart-e43141af-3e0f-45d0-8f51-6f5e6daeb8ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496144699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device
.3496144699
Directory /workspace/79.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.898973454
Short name T928
Test name
Test status
Simulation time 20133549876 ps
CPU time 351.32 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:18:14 PM PST 24
Peak memory 554112 kb
Host smart-0b52cb75-06a5-4a86-a397-51b8f185099b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898973454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_d
evice_slow_rsp.898973454
Directory /workspace/79.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.1713333599
Short name T1859
Test name
Test status
Simulation time 1354056086 ps
CPU time 52.03 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:13:15 PM PST 24
Peak memory 554100 kb
Host smart-48394dc1-88e3-4ee8-8ae2-3fba546e3d94
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713333599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add
r.1713333599
Directory /workspace/79.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_error_random.2776933249
Short name T1407
Test name
Test status
Simulation time 708055923 ps
CPU time 26.35 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:12:50 PM PST 24
Peak memory 553864 kb
Host smart-a5ffebc6-4cf2-4a34-a047-51174cdd9528
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776933249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.2776933249
Directory /workspace/79.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random.291557336
Short name T749
Test name
Test status
Simulation time 1870135281 ps
CPU time 62.01 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:13:27 PM PST 24
Peak memory 553912 kb
Host smart-67e8094e-874f-492c-890f-cc4846323755
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291557336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.291557336
Directory /workspace/79.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.2959975984
Short name T480
Test name
Test status
Simulation time 48915926289 ps
CPU time 539.23 seconds
Started Jan 03 02:12:35 PM PST 24
Finished Jan 03 02:21:46 PM PST 24
Peak memory 553980 kb
Host smart-b197cadc-933e-47cb-ba80-f54fca7c106c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959975984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.2959975984
Directory /workspace/79.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.3335230132
Short name T210
Test name
Test status
Simulation time 56812220228 ps
CPU time 1004.1 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:29:03 PM PST 24
Peak memory 554284 kb
Host smart-404c0d7e-69af-4739-bb7c-a4f18a8d3fb5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335230132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.3335230132
Directory /workspace/79.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.1158511457
Short name T1468
Test name
Test status
Simulation time 71621225 ps
CPU time 8.97 seconds
Started Jan 03 02:12:20 PM PST 24
Finished Jan 03 02:12:37 PM PST 24
Peak memory 552028 kb
Host smart-ebd1525c-d236-48fc-91f2-7623546663d7
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158511457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del
ays.1158511457
Directory /workspace/79.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_same_source.1443919906
Short name T597
Test name
Test status
Simulation time 1535087760 ps
CPU time 45.09 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:13:06 PM PST 24
Peak memory 554224 kb
Host smart-b48ac78f-e1ab-424a-82c6-1720fe40d1f9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443919906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.1443919906
Directory /workspace/79.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke.3059503033
Short name T1039
Test name
Test status
Simulation time 34285605 ps
CPU time 5.49 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:12:22 PM PST 24
Peak memory 551776 kb
Host smart-6e1976a5-11e1-4be0-8414-ebfc9b780e08
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059503033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.3059503033
Directory /workspace/79.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2621302051
Short name T1907
Test name
Test status
Simulation time 6794942209 ps
CPU time 71.62 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:13:29 PM PST 24
Peak memory 551876 kb
Host smart-14ca1c08-0c4f-4f83-8717-42481f33132c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621302051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.2621302051
Directory /workspace/79.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.1486944127
Short name T919
Test name
Test status
Simulation time 3966610891 ps
CPU time 69.64 seconds
Started Jan 03 02:12:15 PM PST 24
Finished Jan 03 02:13:29 PM PST 24
Peak memory 551800 kb
Host smart-eb4636bb-60d6-4569-8a53-1f36c32b72c3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486944127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.1486944127
Directory /workspace/79.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2650605998
Short name T1073
Test name
Test status
Simulation time 40217967 ps
CPU time 5.61 seconds
Started Jan 03 02:12:15 PM PST 24
Finished Jan 03 02:12:24 PM PST 24
Peak memory 552052 kb
Host smart-71ed0423-60a9-46a7-8eeb-3429cee5ed8f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650605998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay
s.2650605998
Directory /workspace/79.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all.1812081129
Short name T179
Test name
Test status
Simulation time 1579040535 ps
CPU time 148.97 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:14:47 PM PST 24
Peak memory 554264 kb
Host smart-7407df5c-7453-486a-8d6a-429104f5acd0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812081129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.1812081129
Directory /workspace/79.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.1343100991
Short name T1678
Test name
Test status
Simulation time 2699798068 ps
CPU time 175.03 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:15:14 PM PST 24
Peak memory 555308 kb
Host smart-67d72aee-e4df-474b-8888-2091926802e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343100991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.1343100991
Directory /workspace/79.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2487107554
Short name T499
Test name
Test status
Simulation time 562729380 ps
CPU time 145.43 seconds
Started Jan 03 02:12:32 PM PST 24
Finished Jan 03 02:15:08 PM PST 24
Peak memory 555856 kb
Host smart-24e3f173-7678-4877-90d3-4ab84f0bab4d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487107554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al
l_with_reset_error.2487107554
Directory /workspace/79.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.1664607160
Short name T1735
Test name
Test status
Simulation time 312377907 ps
CPU time 32.27 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:12:54 PM PST 24
Peak memory 554172 kb
Host smart-c3c79c94-b5d9-4dd7-8e2d-e54ea037d5f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664607160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.1664607160
Directory /workspace/79.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.1720230515
Short name T282
Test name
Test status
Simulation time 6188645640 ps
CPU time 286.02 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:13:08 PM PST 24
Peak memory 629124 kb
Host smart-617f832d-549b-4b8c-9743-971effd030bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720230515 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.1720230515
Directory /workspace/8.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.chip_csr_rw.3836035844
Short name T1566
Test name
Test status
Simulation time 4509774423 ps
CPU time 316.72 seconds
Started Jan 03 02:08:15 PM PST 24
Finished Jan 03 02:13:36 PM PST 24
Peak memory 580012 kb
Host smart-386e0384-dc5b-4073-96fd-fec8b5ec63a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836035844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.3836035844
Directory /workspace/8.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_access_same_device.77897670
Short name T915
Test name
Test status
Simulation time 188000675 ps
CPU time 13.94 seconds
Started Jan 03 02:07:55 PM PST 24
Finished Jan 03 02:08:20 PM PST 24
Peak memory 552808 kb
Host smart-b769fab7-c2b9-4cc9-a8da-08fecd10603e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77897670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.77897670
Directory /workspace/8.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1744053137
Short name T1471
Test name
Test status
Simulation time 42050790556 ps
CPU time 718.03 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:20:06 PM PST 24
Peak memory 554076 kb
Host smart-f547cd12-7bf7-4c4b-92b6-a95b159f4ea8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744053137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d
evice_slow_rsp.1744053137
Directory /workspace/8.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.4163165567
Short name T1129
Test name
Test status
Simulation time 741407975 ps
CPU time 29.86 seconds
Started Jan 03 02:08:17 PM PST 24
Finished Jan 03 02:08:53 PM PST 24
Peak memory 553780 kb
Host smart-12723d84-d0fe-4c3b-8e5c-3e6791bccde0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163165567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr
.4163165567
Directory /workspace/8.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_error_random.4166708384
Short name T1071
Test name
Test status
Simulation time 109504709 ps
CPU time 12.06 seconds
Started Jan 03 02:07:57 PM PST 24
Finished Jan 03 02:08:20 PM PST 24
Peak memory 553936 kb
Host smart-c3f9f215-2299-4549-ad59-1bcb1dfa5cc4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166708384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.4166708384
Directory /workspace/8.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random.2154136310
Short name T1155
Test name
Test status
Simulation time 539644870 ps
CPU time 46.12 seconds
Started Jan 03 02:07:24 PM PST 24
Finished Jan 03 02:08:22 PM PST 24
Peak memory 554224 kb
Host smart-a1f0ab05-19e9-4fe6-8096-d198032e7317
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154136310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.2154136310
Directory /workspace/8.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.3476356786
Short name T165
Test name
Test status
Simulation time 60202495793 ps
CPU time 717.73 seconds
Started Jan 03 02:07:35 PM PST 24
Finished Jan 03 02:19:43 PM PST 24
Peak memory 553972 kb
Host smart-88225468-ebd0-4d0c-a6ef-4c374e467b4a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476356786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3476356786
Directory /workspace/8.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.2094946320
Short name T1900
Test name
Test status
Simulation time 56360616616 ps
CPU time 957.01 seconds
Started Jan 03 02:07:45 PM PST 24
Finished Jan 03 02:23:54 PM PST 24
Peak memory 554256 kb
Host smart-4641890a-063a-4998-9705-84b04d605ab9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094946320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2094946320
Directory /workspace/8.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.4062382714
Short name T1479
Test name
Test status
Simulation time 343626169 ps
CPU time 28.19 seconds
Started Jan 03 02:08:02 PM PST 24
Finished Jan 03 02:08:40 PM PST 24
Peak memory 553820 kb
Host smart-dc8a99cb-7ced-4f60-ae30-36c743ef78b6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062382714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela
ys.4062382714
Directory /workspace/8.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_same_source.2664561967
Short name T220
Test name
Test status
Simulation time 2103550640 ps
CPU time 62.1 seconds
Started Jan 03 02:07:57 PM PST 24
Finished Jan 03 02:09:10 PM PST 24
Peak memory 553980 kb
Host smart-36880980-4cb2-4b12-ba02-2071393df1d6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664561967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2664561967
Directory /workspace/8.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke.604881913
Short name T1003
Test name
Test status
Simulation time 44190870 ps
CPU time 5.74 seconds
Started Jan 03 02:07:30 PM PST 24
Finished Jan 03 02:07:45 PM PST 24
Peak memory 551672 kb
Host smart-4607f65a-301b-4f99-b3ac-15fa477ed03f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604881913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.604881913
Directory /workspace/8.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.4065687195
Short name T1470
Test name
Test status
Simulation time 9210871528 ps
CPU time 97.01 seconds
Started Jan 03 02:07:22 PM PST 24
Finished Jan 03 02:09:11 PM PST 24
Peak memory 552160 kb
Host smart-caa926a0-9f1b-45d0-b97b-ace9138d623e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065687195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.4065687195
Directory /workspace/8.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.2516787194
Short name T1335
Test name
Test status
Simulation time 3927590295 ps
CPU time 62.79 seconds
Started Jan 03 02:07:58 PM PST 24
Finished Jan 03 02:09:11 PM PST 24
Peak memory 551844 kb
Host smart-38df5b5f-ec24-44e0-a34b-d69c84b4ddf6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516787194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2516787194
Directory /workspace/8.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1624839786
Short name T1843
Test name
Test status
Simulation time 57427920 ps
CPU time 6.17 seconds
Started Jan 03 02:07:47 PM PST 24
Finished Jan 03 02:08:05 PM PST 24
Peak memory 551760 kb
Host smart-05e0962f-cc4a-4868-95c9-13423a4d1d3f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624839786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays
.1624839786
Directory /workspace/8.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all.3988490106
Short name T458
Test name
Test status
Simulation time 351144294 ps
CPU time 13.35 seconds
Started Jan 03 02:08:09 PM PST 24
Finished Jan 03 02:08:27 PM PST 24
Peak memory 552108 kb
Host smart-44874dd7-31f2-42ea-bf01-e07fdd97b700
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988490106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3988490106
Directory /workspace/8.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.2863921761
Short name T1318
Test name
Test status
Simulation time 7039440823 ps
CPU time 240.12 seconds
Started Jan 03 02:08:18 PM PST 24
Finished Jan 03 02:12:25 PM PST 24
Peak memory 555132 kb
Host smart-dc967661-b125-4c75-be2f-597833bad957
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863921761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2863921761
Directory /workspace/8.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1881644408
Short name T1507
Test name
Test status
Simulation time 683363730 ps
CPU time 204.4 seconds
Started Jan 03 02:08:06 PM PST 24
Finished Jan 03 02:11:37 PM PST 24
Peak memory 556276 kb
Host smart-31c5307c-4c76-4733-a826-8217e4e48643
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881644408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_
with_rand_reset.1881644408
Directory /workspace/8.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3025520746
Short name T1441
Test name
Test status
Simulation time 3070623435 ps
CPU time 287.16 seconds
Started Jan 03 02:07:52 PM PST 24
Finished Jan 03 02:12:49 PM PST 24
Peak memory 555296 kb
Host smart-9aef3330-0afd-413a-ab04-716d1288c28c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025520746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all
_with_reset_error.3025520746
Directory /workspace/8.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.1075123905
Short name T244
Test name
Test status
Simulation time 271204062 ps
CPU time 29.34 seconds
Started Jan 03 02:07:59 PM PST 24
Finished Jan 03 02:08:38 PM PST 24
Peak memory 554224 kb
Host smart-3d3f41ac-d365-4687-a67a-7608d9621ccc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075123905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1075123905
Directory /workspace/8.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_access_same_device.761899071
Short name T1051
Test name
Test status
Simulation time 3076207981 ps
CPU time 122.97 seconds
Started Jan 03 02:12:15 PM PST 24
Finished Jan 03 02:14:22 PM PST 24
Peak memory 553160 kb
Host smart-d53406fc-589f-4ade-a96a-cc15abb63642
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761899071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device.
761899071
Directory /workspace/80.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2949488751
Short name T1016
Test name
Test status
Simulation time 50123653702 ps
CPU time 849.49 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:26:31 PM PST 24
Peak memory 554288 kb
Host smart-a4f25173-421d-43dd-9152-65ddee147ac2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949488751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_
device_slow_rsp.2949488751
Directory /workspace/80.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2582297453
Short name T382
Test name
Test status
Simulation time 1319242768 ps
CPU time 48.62 seconds
Started Jan 03 02:12:18 PM PST 24
Finished Jan 03 02:13:15 PM PST 24
Peak memory 554112 kb
Host smart-6cbcc28e-acb3-417e-ba76-ca20896dd1f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582297453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add
r.2582297453
Directory /workspace/80.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_error_random.3408908365
Short name T1269
Test name
Test status
Simulation time 2126234760 ps
CPU time 79.68 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:13:40 PM PST 24
Peak memory 553912 kb
Host smart-0487d183-8d40-45f0-a9ab-5534332b9ede
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408908365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.3408908365
Directory /workspace/80.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random.834075775
Short name T1005
Test name
Test status
Simulation time 1155052986 ps
CPU time 42.33 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:13:07 PM PST 24
Peak memory 554184 kb
Host smart-5e939f8a-4c2e-48e0-8598-61a86b939116
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834075775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.834075775
Directory /workspace/80.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.2005076278
Short name T1797
Test name
Test status
Simulation time 32023091302 ps
CPU time 346.78 seconds
Started Jan 03 02:12:18 PM PST 24
Finished Jan 03 02:18:12 PM PST 24
Peak memory 554072 kb
Host smart-f348daaf-8ceb-450a-a6b8-fb0b0f0e9293
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005076278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.2005076278
Directory /workspace/80.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.2200885977
Short name T1281
Test name
Test status
Simulation time 40576372678 ps
CPU time 708.25 seconds
Started Jan 03 02:12:33 PM PST 24
Finished Jan 03 02:24:33 PM PST 24
Peak memory 553108 kb
Host smart-3e922537-017c-4054-8074-87390d0f8b8e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200885977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.2200885977
Directory /workspace/80.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.418889389
Short name T978
Test name
Test status
Simulation time 633983528 ps
CPU time 56.65 seconds
Started Jan 03 02:12:30 PM PST 24
Finished Jan 03 02:13:37 PM PST 24
Peak memory 553896 kb
Host smart-46c0c281-9728-4b28-81be-1cbee5e52944
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418889389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_dela
ys.418889389
Directory /workspace/80.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_same_source.3504904756
Short name T1461
Test name
Test status
Simulation time 147029256 ps
CPU time 11.93 seconds
Started Jan 03 02:12:20 PM PST 24
Finished Jan 03 02:12:40 PM PST 24
Peak memory 553080 kb
Host smart-4361385c-fcbc-4266-89a8-32e14d87058f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504904756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.3504904756
Directory /workspace/80.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke.1567106670
Short name T973
Test name
Test status
Simulation time 54228226 ps
CPU time 6.55 seconds
Started Jan 03 02:12:12 PM PST 24
Finished Jan 03 02:12:22 PM PST 24
Peak memory 552104 kb
Host smart-33fe76aa-2af8-42ef-935a-0a51a260913e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567106670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1567106670
Directory /workspace/80.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.4132003323
Short name T1736
Test name
Test status
Simulation time 8507995295 ps
CPU time 89.66 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:13:52 PM PST 24
Peak memory 551804 kb
Host smart-6e579037-ca3c-4039-8087-8e376be8ca14
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132003323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.4132003323
Directory /workspace/80.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.4219716295
Short name T1314
Test name
Test status
Simulation time 5559663553 ps
CPU time 91.95 seconds
Started Jan 03 02:12:18 PM PST 24
Finished Jan 03 02:13:57 PM PST 24
Peak memory 551820 kb
Host smart-c4288faf-7760-449b-a700-3fb5632ead95
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219716295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.4219716295
Directory /workspace/80.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.4183212041
Short name T699
Test name
Test status
Simulation time 50575431 ps
CPU time 6.07 seconds
Started Jan 03 02:12:18 PM PST 24
Finished Jan 03 02:12:31 PM PST 24
Peak memory 551732 kb
Host smart-35ae4e63-5ffc-4cd3-85bf-692d86d7f99e
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183212041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay
s.4183212041
Directory /workspace/80.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all.542170576
Short name T156
Test name
Test status
Simulation time 2626978865 ps
CPU time 177.57 seconds
Started Jan 03 02:12:35 PM PST 24
Finished Jan 03 02:15:46 PM PST 24
Peak memory 555144 kb
Host smart-f47d01e3-89cf-4f9d-a13f-5854667198b9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542170576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.542170576
Directory /workspace/80.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2965067753
Short name T1598
Test name
Test status
Simulation time 213163357 ps
CPU time 18.68 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:12:35 PM PST 24
Peak memory 554936 kb
Host smart-71eabdbd-512b-462d-8ef9-93080c238531
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965067753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.2965067753
Directory /workspace/80.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.277964474
Short name T342
Test name
Test status
Simulation time 956891115 ps
CPU time 327.87 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:17:50 PM PST 24
Peak memory 556416 kb
Host smart-fd7dfed5-dfa4-4d26-8551-48116adfd12d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277964474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_
with_rand_reset.277964474
Directory /workspace/80.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1676128701
Short name T358
Test name
Test status
Simulation time 11994137715 ps
CPU time 494.64 seconds
Started Jan 03 02:12:15 PM PST 24
Finished Jan 03 02:20:34 PM PST 24
Peak memory 559060 kb
Host smart-2a3b61c1-e827-4172-9b2a-885d62080749
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676128701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al
l_with_reset_error.1676128701
Directory /workspace/80.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.118868539
Short name T1542
Test name
Test status
Simulation time 294518573 ps
CPU time 36.42 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:12:55 PM PST 24
Peak memory 554252 kb
Host smart-44c01312-4888-497b-a27e-e3c1eb6d30ba
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118868539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.118868539
Directory /workspace/80.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_access_same_device.565943434
Short name T627
Test name
Test status
Simulation time 470436217 ps
CPU time 38.31 seconds
Started Jan 03 02:12:18 PM PST 24
Finished Jan 03 02:13:04 PM PST 24
Peak memory 555132 kb
Host smart-5a1a35e2-af11-4ded-908a-5c0a05121663
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565943434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device.
565943434
Directory /workspace/81.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1435871987
Short name T932
Test name
Test status
Simulation time 138635774069 ps
CPU time 2375.56 seconds
Started Jan 03 02:12:14 PM PST 24
Finished Jan 03 02:51:54 PM PST 24
Peak memory 555456 kb
Host smart-1d08b25b-a0b8-4c85-ad22-2cccd2da94d4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435871987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_
device_slow_rsp.1435871987
Directory /workspace/81.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.933832141
Short name T1603
Test name
Test status
Simulation time 206873637 ps
CPU time 22.1 seconds
Started Jan 03 02:12:13 PM PST 24
Finished Jan 03 02:12:38 PM PST 24
Peak memory 554160 kb
Host smart-b0eb78f4-65dd-4c50-872b-fd9f2649ee2c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933832141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_addr
.933832141
Directory /workspace/81.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_error_random.1702289737
Short name T543
Test name
Test status
Simulation time 569133603 ps
CPU time 40.04 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:13:01 PM PST 24
Peak memory 554160 kb
Host smart-f6d5698e-aa81-494a-9492-f3a14935effb
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702289737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.1702289737
Directory /workspace/81.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random.354418681
Short name T418
Test name
Test status
Simulation time 480124915 ps
CPU time 19.23 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:12:41 PM PST 24
Peak memory 554144 kb
Host smart-c1cc413c-e31c-4a36-aa8b-7550e86958af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354418681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.354418681
Directory /workspace/81.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.986969474
Short name T1361
Test name
Test status
Simulation time 35792597404 ps
CPU time 366.61 seconds
Started Jan 03 02:12:13 PM PST 24
Finished Jan 03 02:18:23 PM PST 24
Peak memory 554304 kb
Host smart-b9ac97e4-a92e-4542-a22e-bdd4bc53e743
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986969474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.986969474
Directory /workspace/81.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.1859955369
Short name T92
Test name
Test status
Simulation time 55474660507 ps
CPU time 906.95 seconds
Started Jan 03 02:12:19 PM PST 24
Finished Jan 03 02:27:34 PM PST 24
Peak memory 553908 kb
Host smart-85010d1a-ba8b-498d-aabf-6d81327784e7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859955369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.1859955369
Directory /workspace/81.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.1907080164
Short name T1028
Test name
Test status
Simulation time 379218800 ps
CPU time 33.67 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:12:56 PM PST 24
Peak memory 553812 kb
Host smart-3cbd101d-0fc8-4335-8c1d-af117481593f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907080164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del
ays.1907080164
Directory /workspace/81.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_same_source.1003555592
Short name T1911
Test name
Test status
Simulation time 600181677 ps
CPU time 42.66 seconds
Started Jan 03 02:12:18 PM PST 24
Finished Jan 03 02:13:08 PM PST 24
Peak memory 553824 kb
Host smart-6d5cd4f1-2fc8-401e-8159-add08033d49a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003555592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.1003555592
Directory /workspace/81.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke.1908345272
Short name T1384
Test name
Test status
Simulation time 43993073 ps
CPU time 6 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:12:29 PM PST 24
Peak memory 551908 kb
Host smart-a3d3a77b-c034-4b7b-a71d-87580255b4ed
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908345272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.1908345272
Directory /workspace/81.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.1502930550
Short name T965
Test name
Test status
Simulation time 9402766625 ps
CPU time 96.03 seconds
Started Jan 03 02:12:19 PM PST 24
Finished Jan 03 02:14:04 PM PST 24
Peak memory 551816 kb
Host smart-3ee0b6c8-3f31-4d3c-a778-1cc5bc5a0ac9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502930550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.1502930550
Directory /workspace/81.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.303160051
Short name T1377
Test name
Test status
Simulation time 5508022123 ps
CPU time 93.77 seconds
Started Jan 03 02:12:18 PM PST 24
Finished Jan 03 02:14:00 PM PST 24
Peak memory 551872 kb
Host smart-28844e1b-3d09-48fd-8472-213f134236ec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303160051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.303160051
Directory /workspace/81.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3469750144
Short name T1743
Test name
Test status
Simulation time 46810821 ps
CPU time 6.12 seconds
Started Jan 03 02:12:28 PM PST 24
Finished Jan 03 02:12:45 PM PST 24
Peak memory 551720 kb
Host smart-cfb90bf6-1a8a-4fa6-95c6-81b0fe096bc5
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469750144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay
s.3469750144
Directory /workspace/81.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all.1481356694
Short name T1523
Test name
Test status
Simulation time 18538713043 ps
CPU time 674.07 seconds
Started Jan 03 02:12:15 PM PST 24
Finished Jan 03 02:23:33 PM PST 24
Peak memory 555368 kb
Host smart-df37359c-6edd-4fc3-85e3-d19ab0d4dbc9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481356694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.1481356694
Directory /workspace/81.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.336282465
Short name T1346
Test name
Test status
Simulation time 13709208917 ps
CPU time 490.66 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:20:34 PM PST 24
Peak memory 555732 kb
Host smart-0e24de79-9e3e-4a11-b7ee-74564adff1e3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336282465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.336282465
Directory /workspace/81.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3112357039
Short name T1675
Test name
Test status
Simulation time 7784366 ps
CPU time 14.66 seconds
Started Jan 03 02:12:16 PM PST 24
Finished Jan 03 02:12:36 PM PST 24
Peak memory 551784 kb
Host smart-2d28ac45-d29b-427c-be86-92f103b4e3f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112357039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all
_with_rand_reset.3112357039
Directory /workspace/81.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1816188815
Short name T1652
Test name
Test status
Simulation time 36487578 ps
CPU time 28.16 seconds
Started Jan 03 02:12:32 PM PST 24
Finished Jan 03 02:13:10 PM PST 24
Peak memory 553276 kb
Host smart-8fd28be7-8342-4bd7-a2a4-35de4a5da3d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816188815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al
l_with_reset_error.1816188815
Directory /workspace/81.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.3432307706
Short name T913
Test name
Test status
Simulation time 280870482 ps
CPU time 31.72 seconds
Started Jan 03 02:12:18 PM PST 24
Finished Jan 03 02:12:57 PM PST 24
Peak memory 554292 kb
Host smart-72a8f931-2fa4-4eb0-895b-847a35af6039
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432307706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.3432307706
Directory /workspace/81.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_access_same_device.4241809537
Short name T1637
Test name
Test status
Simulation time 1285435179 ps
CPU time 47.57 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:13:40 PM PST 24
Peak memory 553904 kb
Host smart-ac54614f-79b5-4be6-bcfb-cbaddcd10ae3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241809537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device
.4241809537
Directory /workspace/82.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2939989497
Short name T1405
Test name
Test status
Simulation time 2669796492 ps
CPU time 49.21 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:13:41 PM PST 24
Peak memory 551916 kb
Host smart-5a7499c1-52f9-459d-9655-804721087a29
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939989497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_
device_slow_rsp.2939989497
Directory /workspace/82.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1543611521
Short name T1125
Test name
Test status
Simulation time 482938680 ps
CPU time 19.47 seconds
Started Jan 03 02:12:19 PM PST 24
Finished Jan 03 02:12:47 PM PST 24
Peak memory 552864 kb
Host smart-44fb02ef-9c0f-4c8f-8f8b-fad6b4b9dc96
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543611521 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add
r.1543611521
Directory /workspace/82.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_error_random.1850340030
Short name T1687
Test name
Test status
Simulation time 1996613214 ps
CPU time 64.34 seconds
Started Jan 03 02:12:24 PM PST 24
Finished Jan 03 02:13:40 PM PST 24
Peak memory 553888 kb
Host smart-ddf45472-4044-4900-aa03-261ca5d7fcc9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850340030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.1850340030
Directory /workspace/82.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random.2991812719
Short name T612
Test name
Test status
Simulation time 323002246 ps
CPU time 27.81 seconds
Started Jan 03 02:12:19 PM PST 24
Finished Jan 03 02:12:56 PM PST 24
Peak memory 554196 kb
Host smart-26b3a553-3889-497b-880a-20f4fa822c9c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991812719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.2991812719
Directory /workspace/82.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.711118190
Short name T1767
Test name
Test status
Simulation time 74754258622 ps
CPU time 766.99 seconds
Started Jan 03 02:12:30 PM PST 24
Finished Jan 03 02:25:28 PM PST 24
Peak memory 554264 kb
Host smart-073785c2-4695-4098-ae97-b9272e22e7c0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711118190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.711118190
Directory /workspace/82.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.1590666725
Short name T1293
Test name
Test status
Simulation time 17101573764 ps
CPU time 301.75 seconds
Started Jan 03 02:12:19 PM PST 24
Finished Jan 03 02:17:28 PM PST 24
Peak memory 554204 kb
Host smart-16d3845b-6f18-4522-b832-cf8687b80b6f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590666725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.1590666725
Directory /workspace/82.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.1638760631
Short name T728
Test name
Test status
Simulation time 162303241 ps
CPU time 15.9 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:12:40 PM PST 24
Peak memory 554116 kb
Host smart-75925ab8-0d79-424a-b317-785eb35b2ae9
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638760631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del
ays.1638760631
Directory /workspace/82.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_same_source.4022269864
Short name T1688
Test name
Test status
Simulation time 1104992814 ps
CPU time 29.46 seconds
Started Jan 03 02:12:40 PM PST 24
Finished Jan 03 02:13:25 PM PST 24
Peak memory 554096 kb
Host smart-983fa2c1-66d8-4196-bbd1-a6813e7aec1c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022269864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.4022269864
Directory /workspace/82.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke.35098887
Short name T501
Test name
Test status
Simulation time 224035748 ps
CPU time 8.8 seconds
Started Jan 03 02:12:17 PM PST 24
Finished Jan 03 02:12:33 PM PST 24
Peak memory 551632 kb
Host smart-f3dbf87c-2bed-47ed-8e75-aa484d37dab8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35098887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.35098887
Directory /workspace/82.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.4222178481
Short name T1899
Test name
Test status
Simulation time 10732587306 ps
CPU time 110.81 seconds
Started Jan 03 02:12:35 PM PST 24
Finished Jan 03 02:14:37 PM PST 24
Peak memory 551876 kb
Host smart-d3afb6b7-2d24-4a74-a746-9ab71cf2bfe2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222178481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.4222178481
Directory /workspace/82.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.3213674254
Short name T1705
Test name
Test status
Simulation time 5410368454 ps
CPU time 92.41 seconds
Started Jan 03 02:12:34 PM PST 24
Finished Jan 03 02:14:19 PM PST 24
Peak memory 552084 kb
Host smart-b3c05d94-bda4-4e3c-81d8-860d3ed0cce3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213674254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.3213674254
Directory /workspace/82.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.4225168936
Short name T706
Test name
Test status
Simulation time 60906542 ps
CPU time 6.6 seconds
Started Jan 03 02:12:15 PM PST 24
Finished Jan 03 02:12:27 PM PST 24
Peak memory 551704 kb
Host smart-8b45e8e8-28cd-4677-b71d-f4c358a9322c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225168936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay
s.4225168936
Directory /workspace/82.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all.360853125
Short name T1643
Test name
Test status
Simulation time 10828886292 ps
CPU time 343.71 seconds
Started Jan 03 02:12:22 PM PST 24
Finished Jan 03 02:18:16 PM PST 24
Peak memory 555380 kb
Host smart-72836f13-68ad-40d7-ab57-573f8baf2691
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360853125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.360853125
Directory /workspace/82.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.4074213350
Short name T512
Test name
Test status
Simulation time 6296907416 ps
CPU time 226.65 seconds
Started Jan 03 02:12:32 PM PST 24
Finished Jan 03 02:16:29 PM PST 24
Peak memory 555060 kb
Host smart-347dac59-1676-4b6a-9426-2633c0dfb4d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074213350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.4074213350
Directory /workspace/82.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3577971372
Short name T345
Test name
Test status
Simulation time 21772047757 ps
CPU time 835.25 seconds
Started Jan 03 02:12:33 PM PST 24
Finished Jan 03 02:26:41 PM PST 24
Peak memory 559076 kb
Host smart-197e445c-e5d2-45d7-9be8-b0148f21761c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577971372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al
l_with_reset_error.3577971372
Directory /workspace/82.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.2908473645
Short name T1297
Test name
Test status
Simulation time 787160621 ps
CPU time 31.37 seconds
Started Jan 03 02:12:19 PM PST 24
Finished Jan 03 02:12:58 PM PST 24
Peak memory 553916 kb
Host smart-f98fea09-4fa8-43f8-8300-ce582813c617
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908473645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.2908473645
Directory /workspace/82.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_access_same_device.3936430543
Short name T1368
Test name
Test status
Simulation time 270103536 ps
CPU time 12.71 seconds
Started Jan 03 02:12:43 PM PST 24
Finished Jan 03 02:13:12 PM PST 24
Peak memory 551856 kb
Host smart-5d271329-e445-46c5-a497-b4f8e69502c0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936430543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device
.3936430543
Directory /workspace/83.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.1426298846
Short name T1401
Test name
Test status
Simulation time 34038359022 ps
CPU time 543.32 seconds
Started Jan 03 02:12:42 PM PST 24
Finished Jan 03 02:22:02 PM PST 24
Peak memory 554244 kb
Host smart-9273a863-d864-4b1e-abf9-d52601a89700
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426298846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_
device_slow_rsp.1426298846
Directory /workspace/83.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.873454511
Short name T1431
Test name
Test status
Simulation time 1284088973 ps
CPU time 43.08 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:13:58 PM PST 24
Peak memory 554160 kb
Host smart-dcc532ee-0463-4659-a8de-5c9a2cd25a2e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873454511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_addr
.873454511
Directory /workspace/83.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_error_random.4201098760
Short name T1891
Test name
Test status
Simulation time 2083111570 ps
CPU time 71.33 seconds
Started Jan 03 02:12:43 PM PST 24
Finished Jan 03 02:14:10 PM PST 24
Peak memory 554136 kb
Host smart-cd9d8e66-c903-49be-94e2-2e44e79083da
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201098760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.4201098760
Directory /workspace/83.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random.1896793983
Short name T797
Test name
Test status
Simulation time 230122102 ps
CPU time 11.23 seconds
Started Jan 03 02:12:39 PM PST 24
Finished Jan 03 02:13:06 PM PST 24
Peak memory 551860 kb
Host smart-00741d3d-b41c-4246-921d-03a48e790885
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896793983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1896793983
Directory /workspace/83.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.3141203456
Short name T569
Test name
Test status
Simulation time 44401699369 ps
CPU time 450.99 seconds
Started Jan 03 02:12:54 PM PST 24
Finished Jan 03 02:20:41 PM PST 24
Peak memory 554224 kb
Host smart-fc9b29ca-bf22-4dcf-a355-9ebb92575b73
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141203456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.3141203456
Directory /workspace/83.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.9808471
Short name T1243
Test name
Test status
Simulation time 65635211983 ps
CPU time 1162.56 seconds
Started Jan 03 02:12:45 PM PST 24
Finished Jan 03 02:32:23 PM PST 24
Peak memory 554288 kb
Host smart-12916c64-2ec4-49b2-aa8c-f2175418aed7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9808471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.9808471
Directory /workspace/83.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1749003702
Short name T672
Test name
Test status
Simulation time 466466056 ps
CPU time 35.91 seconds
Started Jan 03 02:12:54 PM PST 24
Finished Jan 03 02:13:46 PM PST 24
Peak memory 553004 kb
Host smart-c052ea79-bde3-4196-b400-6738d58ac31a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749003702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del
ays.1749003702
Directory /workspace/83.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_same_source.3412199683
Short name T123
Test name
Test status
Simulation time 1662946002 ps
CPU time 46.34 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:13:38 PM PST 24
Peak memory 553908 kb
Host smart-94ff168f-4fef-42c7-bc6f-8545e3fd9b1a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412199683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.3412199683
Directory /workspace/83.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke.2408229171
Short name T502
Test name
Test status
Simulation time 40299240 ps
CPU time 5.78 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:12:58 PM PST 24
Peak memory 551764 kb
Host smart-cbc8421f-49ab-4f94-a35c-f1e8b16bdeae
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408229171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.2408229171
Directory /workspace/83.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.1677059673
Short name T443
Test name
Test status
Simulation time 10441397031 ps
CPU time 106.05 seconds
Started Jan 03 02:12:53 PM PST 24
Finished Jan 03 02:14:55 PM PST 24
Peak memory 551816 kb
Host smart-1daaa152-f64a-4f57-b13f-9ae9c001fb54
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677059673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.1677059673
Directory /workspace/83.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.2530519461
Short name T966
Test name
Test status
Simulation time 5863561378 ps
CPU time 92.48 seconds
Started Jan 03 02:12:54 PM PST 24
Finished Jan 03 02:14:42 PM PST 24
Peak memory 551812 kb
Host smart-bf010bf6-2aa2-4afe-bad9-8ab9f12dc92d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530519461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.2530519461
Directory /workspace/83.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.500618370
Short name T441
Test name
Test status
Simulation time 51024450 ps
CPU time 6.24 seconds
Started Jan 03 02:12:54 PM PST 24
Finished Jan 03 02:13:16 PM PST 24
Peak memory 552028 kb
Host smart-27504fd1-d6e8-42ba-a12e-239aa783a569
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500618370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays
.500618370
Directory /workspace/83.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all.3721401286
Short name T1108
Test name
Test status
Simulation time 3301135660 ps
CPU time 119.51 seconds
Started Jan 03 02:12:45 PM PST 24
Finished Jan 03 02:15:00 PM PST 24
Peak memory 555344 kb
Host smart-67e45a02-68b2-4213-9285-7bf3282fac23
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721401286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3721401286
Directory /workspace/83.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.3519575671
Short name T324
Test name
Test status
Simulation time 11044521545 ps
CPU time 343.08 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:18:58 PM PST 24
Peak memory 555152 kb
Host smart-7258ecd3-f700-4216-ae63-e264120a3b7e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519575671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.3519575671
Directory /workspace/83.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.137932847
Short name T1142
Test name
Test status
Simulation time 377064194 ps
CPU time 83.05 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:14:38 PM PST 24
Peak memory 555348 kb
Host smart-8cc1ec47-14e4-4c7d-ab92-ab996c6a9184
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137932847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_
with_rand_reset.137932847
Directory /workspace/83.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3196678316
Short name T339
Test name
Test status
Simulation time 218987409 ps
CPU time 80.72 seconds
Started Jan 03 02:12:52 PM PST 24
Finished Jan 03 02:14:28 PM PST 24
Peak memory 554124 kb
Host smart-4b92f5cd-32c0-458e-bf1f-b3b9418f4f30
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196678316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al
l_with_reset_error.3196678316
Directory /workspace/83.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.2285847473
Short name T140
Test name
Test status
Simulation time 237420115 ps
CPU time 27.34 seconds
Started Jan 03 02:12:39 PM PST 24
Finished Jan 03 02:13:22 PM PST 24
Peak memory 553160 kb
Host smart-6be5110d-f149-4fee-b767-03ed7db5e278
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285847473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.2285847473
Directory /workspace/83.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_access_same_device.3270294354
Short name T1411
Test name
Test status
Simulation time 1527724820 ps
CPU time 61.24 seconds
Started Jan 03 02:12:22 PM PST 24
Finished Jan 03 02:13:33 PM PST 24
Peak memory 554152 kb
Host smart-ee7010a2-2b26-4538-9dd3-595768837154
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270294354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device
.3270294354
Directory /workspace/84.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2713142941
Short name T1918
Test name
Test status
Simulation time 75990823621 ps
CPU time 1279 seconds
Started Jan 03 02:12:38 PM PST 24
Finished Jan 03 02:34:13 PM PST 24
Peak memory 553960 kb
Host smart-d8f2416d-497c-46f1-89ec-7fbd7214a286
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713142941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_
device_slow_rsp.2713142941
Directory /workspace/84.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.1921417948
Short name T517
Test name
Test status
Simulation time 303366524 ps
CPU time 30.22 seconds
Started Jan 03 02:12:34 PM PST 24
Finished Jan 03 02:13:16 PM PST 24
Peak memory 554104 kb
Host smart-b7a60fdc-cf32-475f-bcae-f1e152def486
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921417948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add
r.1921417948
Directory /workspace/84.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_error_random.1277813278
Short name T886
Test name
Test status
Simulation time 820789305 ps
CPU time 28.36 seconds
Started Jan 03 02:12:21 PM PST 24
Finished Jan 03 02:13:00 PM PST 24
Peak memory 554088 kb
Host smart-e1340012-8239-4510-b10e-afb290d9168e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277813278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.1277813278
Directory /workspace/84.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random.1771515123
Short name T1254
Test name
Test status
Simulation time 1353234451 ps
CPU time 49.49 seconds
Started Jan 03 02:12:40 PM PST 24
Finished Jan 03 02:13:45 PM PST 24
Peak memory 553888 kb
Host smart-da6ab017-962e-41a1-b0c4-9494f091fec5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771515123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.1771515123
Directory /workspace/84.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1111355709
Short name T841
Test name
Test status
Simulation time 35658469343 ps
CPU time 409.24 seconds
Started Jan 03 02:12:32 PM PST 24
Finished Jan 03 02:19:32 PM PST 24
Peak memory 554216 kb
Host smart-befa65d1-8778-48e8-85ce-1464f1374cf2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111355709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1111355709
Directory /workspace/84.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.2352273589
Short name T164
Test name
Test status
Simulation time 56099293263 ps
CPU time 1059.54 seconds
Started Jan 03 02:12:21 PM PST 24
Finished Jan 03 02:30:11 PM PST 24
Peak memory 554268 kb
Host smart-30c5adb5-f606-4a72-b501-892df3c15559
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352273589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.2352273589
Directory /workspace/84.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.3702054787
Short name T1654
Test name
Test status
Simulation time 112373864 ps
CPU time 11.05 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:13:00 PM PST 24
Peak memory 553900 kb
Host smart-285423ec-e099-48bd-bb68-6b47f92382bb
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702054787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del
ays.3702054787
Directory /workspace/84.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_same_source.2277466402
Short name T1585
Test name
Test status
Simulation time 411144393 ps
CPU time 28.16 seconds
Started Jan 03 02:12:39 PM PST 24
Finished Jan 03 02:13:23 PM PST 24
Peak memory 554236 kb
Host smart-a8dc272e-dee7-43f6-833d-73c71b472cc0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277466402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.2277466402
Directory /workspace/84.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke.1333902509
Short name T483
Test name
Test status
Simulation time 171315890 ps
CPU time 7.96 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:28 PM PST 24
Peak memory 551172 kb
Host smart-264e0c54-bce8-4dea-a900-7578f8200234
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333902509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.1333902509
Directory /workspace/84.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.613452987
Short name T1347
Test name
Test status
Simulation time 8419180963 ps
CPU time 84.92 seconds
Started Jan 03 02:12:39 PM PST 24
Finished Jan 03 02:14:19 PM PST 24
Peak memory 551856 kb
Host smart-4c837743-f727-4a25-9d19-825e5f940129
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613452987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.613452987
Directory /workspace/84.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.622642290
Short name T975
Test name
Test status
Simulation time 4313799264 ps
CPU time 75.47 seconds
Started Jan 03 02:12:21 PM PST 24
Finished Jan 03 02:13:47 PM PST 24
Peak memory 552096 kb
Host smart-58e00a89-4906-4b16-a956-ca34c57ae64c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622642290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.622642290
Directory /workspace/84.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3333489960
Short name T1490
Test name
Test status
Simulation time 45928887 ps
CPU time 5.87 seconds
Started Jan 03 02:12:51 PM PST 24
Finished Jan 03 02:13:12 PM PST 24
Peak memory 551724 kb
Host smart-660dc042-3b7f-4c13-9b30-62d91d5b8f4c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333489960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay
s.3333489960
Directory /workspace/84.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all.612933134
Short name T162
Test name
Test status
Simulation time 3849938853 ps
CPU time 294.37 seconds
Started Jan 03 02:12:35 PM PST 24
Finished Jan 03 02:17:43 PM PST 24
Peak memory 555100 kb
Host smart-e2e18b78-d51b-4a84-b009-81777bed95f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612933134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.612933134
Directory /workspace/84.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.1992986628
Short name T1040
Test name
Test status
Simulation time 2632227070 ps
CPU time 86.96 seconds
Started Jan 03 02:12:21 PM PST 24
Finished Jan 03 02:13:58 PM PST 24
Peak memory 555292 kb
Host smart-b562b3ea-9d37-4d45-b0ee-66b9b4eb2fcc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992986628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.1992986628
Directory /workspace/84.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.1032358596
Short name T1404
Test name
Test status
Simulation time 637540233 ps
CPU time 208.52 seconds
Started Jan 03 02:12:38 PM PST 24
Finished Jan 03 02:16:22 PM PST 24
Peak memory 556932 kb
Host smart-fbb7c81f-b5e0-4603-be18-359f4734d78c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032358596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all
_with_rand_reset.1032358596
Directory /workspace/84.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2901583211
Short name T484
Test name
Test status
Simulation time 214659230 ps
CPU time 61.02 seconds
Started Jan 03 02:12:19 PM PST 24
Finished Jan 03 02:13:28 PM PST 24
Peak memory 555076 kb
Host smart-4fd0784d-5f90-439d-9647-1b778ee4f398
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901583211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al
l_with_reset_error.2901583211
Directory /workspace/84.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.1346057042
Short name T866
Test name
Test status
Simulation time 66993380 ps
CPU time 6.23 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:12:58 PM PST 24
Peak memory 551844 kb
Host smart-ebbeeb42-035c-4245-adff-bf06da81c4b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346057042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.1346057042
Directory /workspace/84.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_access_same_device.542422264
Short name T1855
Test name
Test status
Simulation time 394070841 ps
CPU time 32.48 seconds
Started Jan 03 02:12:38 PM PST 24
Finished Jan 03 02:13:26 PM PST 24
Peak memory 553936 kb
Host smart-300698da-0b2d-4b08-9432-c3acd5bac507
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542422264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device.
542422264
Directory /workspace/85.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3696387500
Short name T1426
Test name
Test status
Simulation time 125749292369 ps
CPU time 2168.23 seconds
Started Jan 03 02:12:42 PM PST 24
Finished Jan 03 02:49:07 PM PST 24
Peak memory 554328 kb
Host smart-46b723cf-de19-4fd0-9ffa-35e3c7d637d1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696387500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_
device_slow_rsp.3696387500
Directory /workspace/85.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2110134850
Short name T463
Test name
Test status
Simulation time 649078134 ps
CPU time 26.94 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:13:44 PM PST 24
Peak memory 553828 kb
Host smart-7f1ce40d-ec58-49d9-9ec5-8e5ac133dc20
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110134850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add
r.2110134850
Directory /workspace/85.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_error_random.2030176262
Short name T451
Test name
Test status
Simulation time 329186608 ps
CPU time 12.34 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:13:26 PM PST 24
Peak memory 553792 kb
Host smart-2c5b3b8c-594b-4746-a796-8f2ec1ddeaf0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030176262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2030176262
Directory /workspace/85.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random.364698359
Short name T1753
Test name
Test status
Simulation time 151127696 ps
CPU time 15.28 seconds
Started Jan 03 02:12:43 PM PST 24
Finished Jan 03 02:13:14 PM PST 24
Peak memory 554200 kb
Host smart-dfda6e81-f2e9-4d11-ad85-434c9cfb4842
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364698359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.364698359
Directory /workspace/85.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.1964639199
Short name T1640
Test name
Test status
Simulation time 76356644281 ps
CPU time 890.29 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:27:43 PM PST 24
Peak memory 553920 kb
Host smart-24a55ab7-fd2d-4412-87db-efeee543a663
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964639199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.1964639199
Directory /workspace/85.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.3774199919
Short name T602
Test name
Test status
Simulation time 56767843413 ps
CPU time 836.1 seconds
Started Jan 03 02:12:35 PM PST 24
Finished Jan 03 02:26:45 PM PST 24
Peak memory 553980 kb
Host smart-6f80a8b6-5617-48c6-a3de-578c3297328b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774199919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.3774199919
Directory /workspace/85.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.4205249640
Short name T755
Test name
Test status
Simulation time 179622606 ps
CPU time 15.8 seconds
Started Jan 03 02:12:35 PM PST 24
Finished Jan 03 02:13:04 PM PST 24
Peak memory 553840 kb
Host smart-4b4a676d-0be1-434c-a958-4b8ca0c7afba
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205249640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del
ays.4205249640
Directory /workspace/85.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_same_source.1871472184
Short name T1355
Test name
Test status
Simulation time 441850199 ps
CPU time 31.71 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:13:45 PM PST 24
Peak memory 554184 kb
Host smart-78d8c662-8779-4bc6-9476-136fe8e0fdb4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871472184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.1871472184
Directory /workspace/85.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke.1930787652
Short name T425
Test name
Test status
Simulation time 218477513 ps
CPU time 8.94 seconds
Started Jan 03 02:12:34 PM PST 24
Finished Jan 03 02:12:55 PM PST 24
Peak memory 552112 kb
Host smart-3426894f-acde-4259-9f5d-318909ea180a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930787652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1930787652
Directory /workspace/85.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.19210530
Short name T1323
Test name
Test status
Simulation time 6842563484 ps
CPU time 74.2 seconds
Started Jan 03 02:12:38 PM PST 24
Finished Jan 03 02:14:08 PM PST 24
Peak memory 551888 kb
Host smart-90341b36-1700-4eca-8d15-23bd837a46f7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19210530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.19210530
Directory /workspace/85.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2047506472
Short name T1694
Test name
Test status
Simulation time 5364224963 ps
CPU time 96.76 seconds
Started Jan 03 02:12:21 PM PST 24
Finished Jan 03 02:14:08 PM PST 24
Peak memory 551728 kb
Host smart-4fc8cb88-a312-4a6d-a6c8-b19684e31f81
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047506472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.2047506472
Directory /workspace/85.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.605540972
Short name T1020
Test name
Test status
Simulation time 46444903 ps
CPU time 5.74 seconds
Started Jan 03 02:12:35 PM PST 24
Finished Jan 03 02:12:53 PM PST 24
Peak memory 551744 kb
Host smart-30f61bd7-a583-436e-9d42-75953229ed5a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605540972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delays
.605540972
Directory /workspace/85.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all.4292433730
Short name T1908
Test name
Test status
Simulation time 16525765217 ps
CPU time 564.79 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:22:17 PM PST 24
Peak memory 556756 kb
Host smart-74526061-a6e2-40a9-87f5-8d4e57fa1849
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292433730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.4292433730
Directory /workspace/85.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.2104006412
Short name T860
Test name
Test status
Simulation time 7653384652 ps
CPU time 228.53 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:17:08 PM PST 24
Peak memory 555144 kb
Host smart-59bf31b5-1138-4a5c-a3d6-67001c860538
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104006412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.2104006412
Directory /workspace/85.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2203800495
Short name T1894
Test name
Test status
Simulation time 1666552827 ps
CPU time 329.81 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:18:51 PM PST 24
Peak memory 559044 kb
Host smart-f06e18bd-aa30-4e03-891d-e81d91e1e867
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203800495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all
_with_rand_reset.2203800495
Directory /workspace/85.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3594591346
Short name T1510
Test name
Test status
Simulation time 280385554 ps
CPU time 13.46 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:13:27 PM PST 24
Peak memory 553920 kb
Host smart-a33e67ac-789e-4e95-9b82-3bec8d425296
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594591346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3594591346
Directory /workspace/85.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_access_same_device.2434089528
Short name T1697
Test name
Test status
Simulation time 1522420515 ps
CPU time 94.46 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:14:55 PM PST 24
Peak memory 554232 kb
Host smart-43bafe36-87c3-4582-b4ad-f3fa2e86dec9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434089528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device
.2434089528
Directory /workspace/86.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.148934485
Short name T1035
Test name
Test status
Simulation time 75326403393 ps
CPU time 1233.91 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:33:23 PM PST 24
Peak memory 554308 kb
Host smart-674977fb-1a5d-4c13-b341-df2f9642a7d8
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148934485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_d
evice_slow_rsp.148934485
Directory /workspace/86.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3271755412
Short name T1785
Test name
Test status
Simulation time 117584704 ps
CPU time 7.49 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:28 PM PST 24
Peak memory 552088 kb
Host smart-f1c48f35-27b2-4f3e-917d-2c4c41ea8778
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271755412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add
r.3271755412
Directory /workspace/86.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_error_random.1454601638
Short name T1233
Test name
Test status
Simulation time 437823747 ps
CPU time 14.92 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:35 PM PST 24
Peak memory 554144 kb
Host smart-2e64fb2d-6f18-4acf-8bb1-67ccd60d0fb4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454601638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.1454601638
Directory /workspace/86.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random.4271133208
Short name T1795
Test name
Test status
Simulation time 1303679990 ps
CPU time 44.38 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:14:03 PM PST 24
Peak memory 554192 kb
Host smart-585ee81c-c103-497a-b62d-7eb98fbdf863
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271133208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.4271133208
Directory /workspace/86.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.4012702555
Short name T103
Test name
Test status
Simulation time 45527756320 ps
CPU time 436.59 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:20:39 PM PST 24
Peak memory 553148 kb
Host smart-f3e00217-7b71-411b-b929-0a9f74d5ed3b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012702555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.4012702555
Directory /workspace/86.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.163888897
Short name T1222
Test name
Test status
Simulation time 3978503615 ps
CPU time 65.54 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:14:23 PM PST 24
Peak memory 551896 kb
Host smart-db9172d0-1687-45da-a163-aced6177050e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163888897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.163888897
Directory /workspace/86.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.318826902
Short name T1128
Test name
Test status
Simulation time 432549849 ps
CPU time 36.09 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:13:51 PM PST 24
Peak memory 553888 kb
Host smart-eff67bd5-8fe9-40e5-a8f2-b67d7fba1843
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318826902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_dela
ys.318826902
Directory /workspace/86.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_same_source.3159117414
Short name T172
Test name
Test status
Simulation time 1018294952 ps
CPU time 27.48 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:13:50 PM PST 24
Peak memory 553848 kb
Host smart-049847fd-c600-41a5-89b2-d0676c00ef51
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159117414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.3159117414
Directory /workspace/86.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke.2948315088
Short name T486
Test name
Test status
Simulation time 234945367 ps
CPU time 9.21 seconds
Started Jan 03 02:12:52 PM PST 24
Finished Jan 03 02:13:16 PM PST 24
Peak memory 552044 kb
Host smart-0e53a485-3dca-404d-a78c-db0fa931e815
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948315088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.2948315088
Directory /workspace/86.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.2582424739
Short name T643
Test name
Test status
Simulation time 9007069311 ps
CPU time 84.67 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:14:43 PM PST 24
Peak memory 552076 kb
Host smart-d32e5642-619d-457f-99cd-b7791d25d426
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582424739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.2582424739
Directory /workspace/86.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1625148314
Short name T1271
Test name
Test status
Simulation time 5137071157 ps
CPU time 80.29 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:14:41 PM PST 24
Peak memory 552072 kb
Host smart-a7bccd56-fa03-448b-9e3b-7a562ed9a6ef
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625148314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.1625148314
Directory /workspace/86.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3718232530
Short name T1122
Test name
Test status
Simulation time 52226484 ps
CPU time 6.22 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:13:24 PM PST 24
Peak memory 551748 kb
Host smart-87518711-9bd1-4176-85f1-25aa37a0aa77
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718232530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay
s.3718232530
Directory /workspace/86.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all.439839531
Short name T90
Test name
Test status
Simulation time 5574505614 ps
CPU time 351.94 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:19:12 PM PST 24
Peak memory 558712 kb
Host smart-8c39fcdb-cec9-4975-ae29-0e375cc8a60b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439839531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.439839531
Directory /workspace/86.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.736698452
Short name T1242
Test name
Test status
Simulation time 2151698362 ps
CPU time 139.19 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:15:41 PM PST 24
Peak memory 554948 kb
Host smart-0ca692ad-56bb-40be-b693-d3a39e93a24d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736698452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.736698452
Directory /workspace/86.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.1831575113
Short name T357
Test name
Test status
Simulation time 2037247918 ps
CPU time 247.82 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:17:30 PM PST 24
Peak memory 557424 kb
Host smart-5c0a3ffe-fe54-4cae-9d3d-9b1fa615a955
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831575113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all
_with_rand_reset.1831575113
Directory /workspace/86.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1965192858
Short name T1288
Test name
Test status
Simulation time 12251411412 ps
CPU time 531.93 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:22:14 PM PST 24
Peak memory 567248 kb
Host smart-70437555-de7f-49e3-a9e4-7151d9d4759b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965192858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al
l_with_reset_error.1965192858
Directory /workspace/86.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.3834516999
Short name T1104
Test name
Test status
Simulation time 107813705 ps
CPU time 13.21 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:33 PM PST 24
Peak memory 554140 kb
Host smart-8e51a116-886a-4496-a078-1693fed39764
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834516999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.3834516999
Directory /workspace/86.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_access_same_device.2231272482
Short name T477
Test name
Test status
Simulation time 190876023 ps
CPU time 13.42 seconds
Started Jan 03 02:12:22 PM PST 24
Finished Jan 03 02:12:45 PM PST 24
Peak memory 552824 kb
Host smart-9ad49d99-c8b4-45e9-960d-f0fb8bab31fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231272482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device
.2231272482
Directory /workspace/87.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1229288181
Short name T1808
Test name
Test status
Simulation time 124221462126 ps
CPU time 2109.28 seconds
Started Jan 03 02:12:30 PM PST 24
Finished Jan 03 02:47:50 PM PST 24
Peak memory 554264 kb
Host smart-dfdd16c1-c3f2-494d-8e27-afc04bf3f37d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229288181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_
device_slow_rsp.1229288181
Directory /workspace/87.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.210349366
Short name T1849
Test name
Test status
Simulation time 25102212 ps
CPU time 5.34 seconds
Started Jan 03 02:12:32 PM PST 24
Finished Jan 03 02:12:49 PM PST 24
Peak memory 552088 kb
Host smart-6b6b81d2-3a8d-41c0-a591-c4457867160c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210349366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr
.210349366
Directory /workspace/87.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_error_random.3984013027
Short name T894
Test name
Test status
Simulation time 555468188 ps
CPU time 41.42 seconds
Started Jan 03 02:12:39 PM PST 24
Finished Jan 03 02:13:36 PM PST 24
Peak memory 552848 kb
Host smart-16f30da9-c2ed-4cd2-821d-4570aa3bb295
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984013027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.3984013027
Directory /workspace/87.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random.2277239911
Short name T1719
Test name
Test status
Simulation time 218933227 ps
CPU time 18.62 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:13:41 PM PST 24
Peak memory 553908 kb
Host smart-9480e8b5-40ad-41ba-96c3-8fe3eac1cd02
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277239911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.2277239911
Directory /workspace/87.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.2569363448
Short name T1840
Test name
Test status
Simulation time 71630585551 ps
CPU time 707.68 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:25:10 PM PST 24
Peak memory 553892 kb
Host smart-2cd423e2-188f-4c64-a88a-0bffb9a301c5
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569363448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.2569363448
Directory /workspace/87.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.83208477
Short name T1539
Test name
Test status
Simulation time 71520530707 ps
CPU time 1319.1 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:34:52 PM PST 24
Peak memory 554200 kb
Host smart-81a289db-858a-4541-9d53-52bbcae6528e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83208477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.83208477
Directory /workspace/87.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.4086892579
Short name T882
Test name
Test status
Simulation time 39094541 ps
CPU time 6.14 seconds
Started Jan 03 02:12:40 PM PST 24
Finished Jan 03 02:13:01 PM PST 24
Peak memory 551748 kb
Host smart-1026bed8-3974-4576-89f8-954016f3eb86
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086892579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del
ays.4086892579
Directory /workspace/87.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_same_source.3469533822
Short name T734
Test name
Test status
Simulation time 1483358103 ps
CPU time 42.14 seconds
Started Jan 03 02:12:32 PM PST 24
Finished Jan 03 02:13:26 PM PST 24
Peak memory 554120 kb
Host smart-14590e85-9e09-4f54-9b1e-b726ed362c45
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469533822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.3469533822
Directory /workspace/87.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke.4036720735
Short name T982
Test name
Test status
Simulation time 170813813 ps
CPU time 7.53 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:13:27 PM PST 24
Peak memory 551840 kb
Host smart-9c7c8cc4-3973-496d-a878-72239e9e119a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036720735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.4036720735
Directory /workspace/87.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.490244367
Short name T461
Test name
Test status
Simulation time 6443422910 ps
CPU time 60.07 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:14:18 PM PST 24
Peak memory 552068 kb
Host smart-b848fd87-c518-4ba2-b5a5-54f0309ad206
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490244367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.490244367
Directory /workspace/87.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.446630165
Short name T804
Test name
Test status
Simulation time 4451563894 ps
CPU time 70.26 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:14:31 PM PST 24
Peak memory 552144 kb
Host smart-bf297499-c239-4860-b2e5-39e75fbe15d0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446630165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.446630165
Directory /workspace/87.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.1336561781
Short name T881
Test name
Test status
Simulation time 45402999 ps
CPU time 6.05 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:25 PM PST 24
Peak memory 551672 kb
Host smart-49eee0fa-cb1c-41b3-9d76-228aed68f89c
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336561781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay
s.1336561781
Directory /workspace/87.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all.3694804154
Short name T1127
Test name
Test status
Simulation time 2532338505 ps
CPU time 171.4 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:15:41 PM PST 24
Peak memory 555144 kb
Host smart-a496a578-ce46-441f-83f4-889fefdd724d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694804154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.3694804154
Directory /workspace/87.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.217056344
Short name T577
Test name
Test status
Simulation time 1510373145 ps
CPU time 94.34 seconds
Started Jan 03 02:12:34 PM PST 24
Finished Jan 03 02:14:20 PM PST 24
Peak memory 554968 kb
Host smart-34152f34-f5e6-4e06-9117-29704d375931
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217056344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.217056344
Directory /workspace/87.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.4269262875
Short name T338
Test name
Test status
Simulation time 9055390512 ps
CPU time 541.94 seconds
Started Jan 03 02:12:41 PM PST 24
Finished Jan 03 02:21:59 PM PST 24
Peak memory 558708 kb
Host smart-8721bf68-5663-4604-956d-c9b754695aa9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269262875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all
_with_rand_reset.4269262875
Directory /workspace/87.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.2679306133
Short name T356
Test name
Test status
Simulation time 1408185526 ps
CPU time 202.06 seconds
Started Jan 03 02:12:53 PM PST 24
Finished Jan 03 02:16:31 PM PST 24
Peak memory 556124 kb
Host smart-7127c165-b4c2-4ad6-8a9e-ff44a82e9206
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679306133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al
l_with_reset_error.2679306133
Directory /workspace/87.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.557859454
Short name T931
Test name
Test status
Simulation time 1148339434 ps
CPU time 44.61 seconds
Started Jan 03 02:12:31 PM PST 24
Finished Jan 03 02:13:26 PM PST 24
Peak memory 554168 kb
Host smart-b880c0f1-3973-4949-a01e-29752fa26554
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557859454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.557859454
Directory /workspace/87.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_access_same_device.1594153717
Short name T556
Test name
Test status
Simulation time 526432457 ps
CPU time 41.62 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:13:58 PM PST 24
Peak memory 553948 kb
Host smart-348669be-9dbd-447a-86b0-731bd5afa413
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594153717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device
.1594153717
Directory /workspace/88.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2019506349
Short name T327
Test name
Test status
Simulation time 78495049373 ps
CPU time 1197.83 seconds
Started Jan 03 02:12:53 PM PST 24
Finished Jan 03 02:33:07 PM PST 24
Peak memory 555284 kb
Host smart-0bf373a8-d103-4a2e-a589-88a167aeb1c9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019506349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_
device_slow_rsp.2019506349
Directory /workspace/88.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1402950329
Short name T764
Test name
Test status
Simulation time 126885890 ps
CPU time 7.63 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:28 PM PST 24
Peak memory 551812 kb
Host smart-48f5fd03-6bff-476c-8f7e-18d53109d215
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402950329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add
r.1402950329
Directory /workspace/88.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_error_random.3239969431
Short name T437
Test name
Test status
Simulation time 474396609 ps
CPU time 36.05 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:13:54 PM PST 24
Peak memory 554084 kb
Host smart-7c6a75f9-e18e-4ce5-b815-d7a9a084b803
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239969431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.3239969431
Directory /workspace/88.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random.4191150356
Short name T1197
Test name
Test status
Simulation time 235365057 ps
CPU time 11.3 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:13:04 PM PST 24
Peak memory 552064 kb
Host smart-0c9d36c3-68e0-46ed-8719-b8165ffaa893
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191150356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.4191150356
Directory /workspace/88.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.3454832281
Short name T1091
Test name
Test status
Simulation time 81927873180 ps
CPU time 799.89 seconds
Started Jan 03 02:12:52 PM PST 24
Finished Jan 03 02:26:28 PM PST 24
Peak memory 554188 kb
Host smart-63faa56b-a30b-4d30-8f9c-47037e96d747
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454832281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.3454832281
Directory /workspace/88.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.2210440283
Short name T176
Test name
Test status
Simulation time 65474450104 ps
CPU time 1093.92 seconds
Started Jan 03 02:12:42 PM PST 24
Finished Jan 03 02:31:12 PM PST 24
Peak memory 554220 kb
Host smart-d1841c85-9bdd-4f57-80fa-3eeaa666b870
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210440283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.2210440283
Directory /workspace/88.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.1029335648
Short name T147
Test name
Test status
Simulation time 280692641 ps
CPU time 23.98 seconds
Started Jan 03 02:12:43 PM PST 24
Finished Jan 03 02:13:23 PM PST 24
Peak memory 554180 kb
Host smart-75fb34e5-6d20-448b-906a-3b1457e934b8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029335648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del
ays.1029335648
Directory /workspace/88.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_same_source.3713330396
Short name T462
Test name
Test status
Simulation time 78153914 ps
CPU time 8.37 seconds
Started Jan 03 02:12:42 PM PST 24
Finished Jan 03 02:13:07 PM PST 24
Peak memory 553844 kb
Host smart-6a7e08dc-a6e9-43a3-9474-adf4043a99d5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713330396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.3713330396
Directory /workspace/88.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke.1905783042
Short name T1630
Test name
Test status
Simulation time 204360642 ps
CPU time 8.99 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:13:00 PM PST 24
Peak memory 552112 kb
Host smart-e905994d-d463-45b8-bf98-0c906c7f3360
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905783042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.1905783042
Directory /workspace/88.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.2790761832
Short name T1366
Test name
Test status
Simulation time 10168599105 ps
CPU time 104.87 seconds
Started Jan 03 02:12:39 PM PST 24
Finished Jan 03 02:14:40 PM PST 24
Peak memory 552116 kb
Host smart-ac30d814-87d0-4fef-ada5-0e24636aab7a
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790761832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.2790761832
Directory /workspace/88.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.704293528
Short name T144
Test name
Test status
Simulation time 4687218807 ps
CPU time 79.4 seconds
Started Jan 03 02:12:39 PM PST 24
Finished Jan 03 02:14:14 PM PST 24
Peak memory 552164 kb
Host smart-53810978-de4a-413f-a378-8190e24824f1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704293528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.704293528
Directory /workspace/88.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2948446472
Short name T1331
Test name
Test status
Simulation time 42906256 ps
CPU time 5.92 seconds
Started Jan 03 02:12:41 PM PST 24
Finished Jan 03 02:13:03 PM PST 24
Peak memory 552080 kb
Host smart-5f017071-abfa-4581-b9a8-a6de801ff695
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948446472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay
s.2948446472
Directory /workspace/88.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all.3946435402
Short name T120
Test name
Test status
Simulation time 10953761170 ps
CPU time 321.92 seconds
Started Jan 03 02:12:43 PM PST 24
Finished Jan 03 02:18:21 PM PST 24
Peak memory 555408 kb
Host smart-ebf5352b-4b21-4212-b449-dab3628785b7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946435402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.3946435402
Directory /workspace/88.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2751760269
Short name T187
Test name
Test status
Simulation time 467210762 ps
CPU time 100.35 seconds
Started Jan 03 02:12:45 PM PST 24
Finished Jan 03 02:14:41 PM PST 24
Peak memory 556080 kb
Host smart-b1a2320f-b95c-419f-ae5f-605ec3884f8e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751760269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all
_with_rand_reset.2751760269
Directory /workspace/88.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.2903239241
Short name T1673
Test name
Test status
Simulation time 848859598 ps
CPU time 35.04 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:13:49 PM PST 24
Peak memory 553108 kb
Host smart-65abe93a-22e1-47ff-9e99-a5d0860e0e31
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903239241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.2903239241
Directory /workspace/88.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_access_same_device.2246099725
Short name T1651
Test name
Test status
Simulation time 541485521 ps
CPU time 36.54 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:13:54 PM PST 24
Peak memory 555144 kb
Host smart-96426c2a-03c8-4302-a1f0-a836346ae2bd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246099725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device
.2246099725
Directory /workspace/89.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.290514516
Short name T1711
Test name
Test status
Simulation time 13827717022 ps
CPU time 218.44 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:16:58 PM PST 24
Peak memory 553072 kb
Host smart-a7089dec-4594-49e8-8f7c-672f2c2e3022
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290514516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_d
evice_slow_rsp.290514516
Directory /workspace/89.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2493726582
Short name T675
Test name
Test status
Simulation time 156227473 ps
CPU time 17.11 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:13:40 PM PST 24
Peak memory 552848 kb
Host smart-dc4c73c1-26f9-4c2f-884f-144e7270e83e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493726582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add
r.2493726582
Directory /workspace/89.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_error_random.1682589915
Short name T1418
Test name
Test status
Simulation time 2404675913 ps
CPU time 70.56 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:14:34 PM PST 24
Peak memory 554160 kb
Host smart-ae0f32fb-918b-4b62-94ea-76ce2b42fc41
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682589915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.1682589915
Directory /workspace/89.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random.2140515112
Short name T1069
Test name
Test status
Simulation time 2108878237 ps
CPU time 72.48 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:14:30 PM PST 24
Peak memory 553912 kb
Host smart-2be8aae5-1d54-4c45-9036-b51607022969
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140515112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.2140515112
Directory /workspace/89.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.1438224559
Short name T947
Test name
Test status
Simulation time 28028264370 ps
CPU time 257.32 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:17:40 PM PST 24
Peak memory 554172 kb
Host smart-54381aa7-7a3e-4eb0-aa1e-a3846c28ad68
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438224559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.1438224559
Directory /workspace/89.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.2077891944
Short name T215
Test name
Test status
Simulation time 31828334703 ps
CPU time 495.44 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:21:37 PM PST 24
Peak memory 554252 kb
Host smart-3c58c663-e774-4bac-932f-969bfafbd14e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077891944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.2077891944
Directory /workspace/89.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.2836990055
Short name T157
Test name
Test status
Simulation time 449988712 ps
CPU time 35.19 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:13:53 PM PST 24
Peak memory 553872 kb
Host smart-f9841490-20b4-4c2a-9d2b-0de99c095139
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836990055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del
ays.2836990055
Directory /workspace/89.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_same_source.1056764603
Short name T906
Test name
Test status
Simulation time 470340352 ps
CPU time 32.57 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:13:23 PM PST 24
Peak memory 554160 kb
Host smart-d807c0a6-2311-439a-a6fa-03a7bdf205fc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056764603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.1056764603
Directory /workspace/89.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke.3882656730
Short name T1608
Test name
Test status
Simulation time 190190826 ps
CPU time 7.96 seconds
Started Jan 03 02:12:41 PM PST 24
Finished Jan 03 02:13:05 PM PST 24
Peak memory 552036 kb
Host smart-15a9d1bd-ef3d-4a38-8824-64e59ae1340d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882656730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.3882656730
Directory /workspace/89.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.3933611541
Short name T1184
Test name
Test status
Simulation time 9323006392 ps
CPU time 86.94 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:14:43 PM PST 24
Peak memory 551848 kb
Host smart-d7a5bbb7-252a-46c2-a398-c9147237cd63
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933611541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.3933611541
Directory /workspace/89.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.2103097829
Short name T817
Test name
Test status
Simulation time 6641804401 ps
CPU time 110.74 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:15:09 PM PST 24
Peak memory 552080 kb
Host smart-cb9c3bf7-6ba3-4d0c-bbff-c406099ff5b6
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103097829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.2103097829
Directory /workspace/89.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1417616585
Short name T58
Test name
Test status
Simulation time 51877692 ps
CPU time 6.04 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:28 PM PST 24
Peak memory 551772 kb
Host smart-a1609f5f-9eef-4ce5-b35f-cc8d1cd392cf
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417616585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay
s.1417616585
Directory /workspace/89.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all.2412161991
Short name T1230
Test name
Test status
Simulation time 959326564 ps
CPU time 63.78 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:14:22 PM PST 24
Peak memory 555016 kb
Host smart-de5a82db-6d2e-47a3-96e6-c66e9e98c155
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412161991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.2412161991
Directory /workspace/89.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2693250486
Short name T952
Test name
Test status
Simulation time 4698674508 ps
CPU time 146.88 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:15:50 PM PST 24
Peak memory 556284 kb
Host smart-afcc51bc-88ef-4b70-b9f7-9de6cff34366
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693250486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.2693250486
Directory /workspace/89.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.960522389
Short name T1610
Test name
Test status
Simulation time 705871079 ps
CPU time 149.45 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:15:52 PM PST 24
Peak memory 558948 kb
Host smart-6adec88b-c351-4ecd-a1c4-f2ffe09474dd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960522389 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all
_with_reset_error.960522389
Directory /workspace/89.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.2587080538
Short name T1047
Test name
Test status
Simulation time 1039165699 ps
CPU time 38.37 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:58 PM PST 24
Peak memory 554184 kb
Host smart-1df9bc21-69ee-4540-a5a4-222b98758fd8
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587080538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.2587080538
Directory /workspace/89.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.1529667392
Short name T50
Test name
Test status
Simulation time 7187058710 ps
CPU time 425.5 seconds
Started Jan 03 02:07:39 PM PST 24
Finished Jan 03 02:14:57 PM PST 24
Peak memory 624820 kb
Host smart-de9bb9ab-6165-436c-ba93-54f1d5f839e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529667392 -assert nopostproc +
UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.1529667392
Directory /workspace/9.chip_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.chip_csr_rw.1194118609
Short name T949
Test name
Test status
Simulation time 4820958874 ps
CPU time 455.59 seconds
Started Jan 03 02:08:03 PM PST 24
Finished Jan 03 02:15:47 PM PST 24
Peak memory 579988 kb
Host smart-e1a3384d-0377-47a1-b092-ce8b3b7bedd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194118609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.1194118609
Directory /workspace/9.chip_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.823854362
Short name T43
Test name
Test status
Simulation time 15263473101 ps
CPU time 1513.66 seconds
Started Jan 03 02:08:36 PM PST 24
Finished Jan 03 02:33:58 PM PST 24
Peak memory 580044 kb
Host smart-1885b60a-4369-40e3-81c7-d347c11b5412
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823854362 -assert nopostproc +UVM_TES
TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.chip_same_csr_outstanding.823854362
Directory /workspace/9.chip_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_access_same_device.3371548519
Short name T710
Test name
Test status
Simulation time 1906081923 ps
CPU time 75.24 seconds
Started Jan 03 02:08:26 PM PST 24
Finished Jan 03 02:09:50 PM PST 24
Peak memory 554188 kb
Host smart-8c942527-deca-4e05-ae99-d8002f62b88f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371548519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.
3371548519
Directory /workspace/9.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2633188882
Short name T1626
Test name
Test status
Simulation time 80632380953 ps
CPU time 1242.67 seconds
Started Jan 03 02:08:26 PM PST 24
Finished Jan 03 02:29:18 PM PST 24
Peak memory 554976 kb
Host smart-a7d03549-41f9-4483-87dd-4cede15c2a58
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633188882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d
evice_slow_rsp.2633188882
Directory /workspace/9.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.1296322330
Short name T1897
Test name
Test status
Simulation time 77366976 ps
CPU time 9.98 seconds
Started Jan 03 02:08:36 PM PST 24
Finished Jan 03 02:08:53 PM PST 24
Peak memory 554152 kb
Host smart-2aed3b24-4a11-4704-96f0-9e3425fa5a05
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296322330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr
.1296322330
Directory /workspace/9.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_error_random.3315660615
Short name T1854
Test name
Test status
Simulation time 933699117 ps
CPU time 31.95 seconds
Started Jan 03 02:08:35 PM PST 24
Finished Jan 03 02:09:15 PM PST 24
Peak memory 553876 kb
Host smart-7f778a80-2bd1-494c-b0c2-acd1e689ac3e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315660615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3315660615
Directory /workspace/9.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random.134657069
Short name T945
Test name
Test status
Simulation time 1281998882 ps
CPU time 42.8 seconds
Started Jan 03 02:08:35 PM PST 24
Finished Jan 03 02:09:25 PM PST 24
Peak memory 553928 kb
Host smart-cc3a790c-25ca-4aa9-9743-12dd4c2b9608
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134657069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.134657069
Directory /workspace/9.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.2915708463
Short name T1160
Test name
Test status
Simulation time 86009369509 ps
CPU time 902.22 seconds
Started Jan 03 02:08:18 PM PST 24
Finished Jan 03 02:23:28 PM PST 24
Peak memory 553972 kb
Host smart-91a82d3f-119f-412a-b8be-308a0cda0aea
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915708463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2915708463
Directory /workspace/9.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.1365302197
Short name T1466
Test name
Test status
Simulation time 11747863420 ps
CPU time 205.67 seconds
Started Jan 03 02:08:16 PM PST 24
Finished Jan 03 02:11:47 PM PST 24
Peak memory 554272 kb
Host smart-3029aa77-9de7-4c40-953c-989cdc9eb5b3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365302197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1365302197
Directory /workspace/9.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2783779575
Short name T522
Test name
Test status
Simulation time 305361765 ps
CPU time 25.38 seconds
Started Jan 03 02:08:26 PM PST 24
Finished Jan 03 02:09:00 PM PST 24
Peak memory 554080 kb
Host smart-90a22af6-21ee-43d1-8ca9-0cce3071e956
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783779575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela
ys.2783779575
Directory /workspace/9.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_same_source.1641863030
Short name T1548
Test name
Test status
Simulation time 2244229604 ps
CPU time 66.96 seconds
Started Jan 03 02:08:25 PM PST 24
Finished Jan 03 02:09:41 PM PST 24
Peak memory 553964 kb
Host smart-5cde6c89-ce9b-4cb8-9eeb-9adca5260043
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641863030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1641863030
Directory /workspace/9.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke.2752699878
Short name T1166
Test name
Test status
Simulation time 225042131 ps
CPU time 9.12 seconds
Started Jan 03 02:07:53 PM PST 24
Finished Jan 03 02:08:13 PM PST 24
Peak memory 551828 kb
Host smart-acdc31ed-c00c-49e0-9661-9731f7d1f0f5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752699878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2752699878
Directory /workspace/9.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.4253921085
Short name T378
Test name
Test status
Simulation time 7018052536 ps
CPU time 78.46 seconds
Started Jan 03 02:07:55 PM PST 24
Finished Jan 03 02:09:24 PM PST 24
Peak memory 552252 kb
Host smart-cc8e6a09-2397-43ce-b6c4-f4e5041f084d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253921085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4253921085
Directory /workspace/9.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1333030131
Short name T1596
Test name
Test status
Simulation time 5835642950 ps
CPU time 99.72 seconds
Started Jan 03 02:08:20 PM PST 24
Finished Jan 03 02:10:08 PM PST 24
Peak memory 551664 kb
Host smart-da9d508b-a9fa-49c7-b61a-9e53a76a2229
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333030131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1333030131
Directory /workspace/9.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.3870921477
Short name T655
Test name
Test status
Simulation time 36902861 ps
CPU time 5.42 seconds
Started Jan 03 02:08:18 PM PST 24
Finished Jan 03 02:08:30 PM PST 24
Peak memory 551752 kb
Host smart-f3243007-c21e-4727-9096-0ad7576889cc
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870921477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays
.3870921477
Directory /workspace/9.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all.3441927709
Short name T108
Test name
Test status
Simulation time 7867264142 ps
CPU time 314.21 seconds
Started Jan 03 02:07:42 PM PST 24
Finished Jan 03 02:13:08 PM PST 24
Peak memory 555232 kb
Host smart-59729d46-e538-4d29-b669-ffe2e47746ff
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441927709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3441927709
Directory /workspace/9.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1888370014
Short name T955
Test name
Test status
Simulation time 1964411472 ps
CPU time 152.89 seconds
Started Jan 03 02:07:22 PM PST 24
Finished Jan 03 02:10:07 PM PST 24
Peak memory 554976 kb
Host smart-0ada760a-b997-4d76-ba60-9d8233ecae3f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888370014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1888370014
Directory /workspace/9.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.992661928
Short name T1349
Test name
Test status
Simulation time 4591768283 ps
CPU time 323.48 seconds
Started Jan 03 02:08:07 PM PST 24
Finished Jan 03 02:13:37 PM PST 24
Peak memory 556996 kb
Host smart-a88bd6d5-4981-40d5-bb89-5ea59b452428
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992661928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_w
ith_rand_reset.992661928
Directory /workspace/9.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.717163974
Short name T341
Test name
Test status
Simulation time 11233815296 ps
CPU time 625.26 seconds
Started Jan 03 02:07:25 PM PST 24
Finished Jan 03 02:18:01 PM PST 24
Peak memory 559084 kb
Host smart-d69445fc-4e19-41fc-83fd-671ed18d5ffe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717163974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_
with_reset_error.717163974
Directory /workspace/9.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.2685871282
Short name T1345
Test name
Test status
Simulation time 163524357 ps
CPU time 18.53 seconds
Started Jan 03 02:08:57 PM PST 24
Finished Jan 03 02:09:18 PM PST 24
Peak memory 553928 kb
Host smart-966ea4e9-0c7a-470d-aa6e-4cfae0f57ed5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685871282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2685871282
Directory /workspace/9.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_access_same_device.730332976
Short name T319
Test name
Test status
Simulation time 2262164542 ps
CPU time 103.98 seconds
Started Jan 03 02:12:30 PM PST 24
Finished Jan 03 02:14:24 PM PST 24
Peak memory 555260 kb
Host smart-706ff18c-f609-42ab-a55b-927c07379e44
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730332976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device.
730332976
Directory /workspace/90.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.2970624427
Short name T1438
Test name
Test status
Simulation time 131957793589 ps
CPU time 2190.47 seconds
Started Jan 03 02:12:35 PM PST 24
Finished Jan 03 02:49:20 PM PST 24
Peak memory 554284 kb
Host smart-841842f2-4619-4710-a800-259926dbca60
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970624427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_
device_slow_rsp.2970624427
Directory /workspace/90.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3595350804
Short name T207
Test name
Test status
Simulation time 1022166926 ps
CPU time 42.1 seconds
Started Jan 03 02:12:32 PM PST 24
Finished Jan 03 02:13:25 PM PST 24
Peak memory 553820 kb
Host smart-a16b08fe-5e37-4442-887f-63e72727fab0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595350804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add
r.3595350804
Directory /workspace/90.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_error_random.2226294580
Short name T1056
Test name
Test status
Simulation time 1465701393 ps
CPU time 48.87 seconds
Started Jan 03 02:12:21 PM PST 24
Finished Jan 03 02:13:19 PM PST 24
Peak memory 553780 kb
Host smart-1da0a424-56c1-47dc-811d-74888bc0cb2d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226294580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.2226294580
Directory /workspace/90.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random.3218917398
Short name T791
Test name
Test status
Simulation time 265654159 ps
CPU time 11.37 seconds
Started Jan 03 02:12:38 PM PST 24
Finished Jan 03 02:13:05 PM PST 24
Peak memory 553096 kb
Host smart-41c7ff9b-d780-4a19-8935-811d6ef73934
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218917398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.3218917398
Directory /workspace/90.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.2488598530
Short name T1904
Test name
Test status
Simulation time 62785324384 ps
CPU time 680.42 seconds
Started Jan 03 02:12:22 PM PST 24
Finished Jan 03 02:23:53 PM PST 24
Peak memory 553116 kb
Host smart-c4086ccb-7723-406e-a622-68587995482b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488598530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.2488598530
Directory /workspace/90.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.741821137
Short name T887
Test name
Test status
Simulation time 9721318115 ps
CPU time 170.26 seconds
Started Jan 03 02:12:22 PM PST 24
Finished Jan 03 02:15:23 PM PST 24
Peak memory 553928 kb
Host smart-e59b436e-0ddd-4525-8c01-8c0772589bdb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741821137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.741821137
Directory /workspace/90.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.996939750
Short name T855
Test name
Test status
Simulation time 199317873 ps
CPU time 18.94 seconds
Started Jan 03 02:12:39 PM PST 24
Finished Jan 03 02:13:13 PM PST 24
Peak memory 554076 kb
Host smart-3d9c5f35-300c-4b79-b480-ef36f65e6cc1
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996939750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_dela
ys.996939750
Directory /workspace/90.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_same_source.4251728916
Short name T1738
Test name
Test status
Simulation time 990067471 ps
CPU time 27.55 seconds
Started Jan 03 02:12:54 PM PST 24
Finished Jan 03 02:13:37 PM PST 24
Peak memory 553856 kb
Host smart-f576f071-2bdc-4672-9f9b-6c4fd2a3c118
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251728916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.4251728916
Directory /workspace/90.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke.2195886204
Short name T1472
Test name
Test status
Simulation time 121493188 ps
CPU time 6.61 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:27 PM PST 24
Peak memory 551788 kb
Host smart-7dc39ad7-6b0f-446e-9e02-023c0bb38f48
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195886204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.2195886204
Directory /workspace/90.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.3448924508
Short name T1065
Test name
Test status
Simulation time 6917710352 ps
CPU time 69.32 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:14:31 PM PST 24
Peak memory 551852 kb
Host smart-3a21ec9e-7b9f-41e8-919e-144724f03cbb
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448924508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.3448924508
Directory /workspace/90.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.3910875641
Short name T576
Test name
Test status
Simulation time 3807939195 ps
CPU time 65.99 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:13:55 PM PST 24
Peak memory 552052 kb
Host smart-ac6bab1f-7166-443f-9c3d-5c3c97adc613
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910875641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.3910875641
Directory /workspace/90.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.3256211514
Short name T799
Test name
Test status
Simulation time 45179469 ps
CPU time 5.6 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:26 PM PST 24
Peak memory 551800 kb
Host smart-af1d4530-6708-4725-b423-820ecada142f
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256211514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay
s.3256211514
Directory /workspace/90.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all.1549492827
Short name T1176
Test name
Test status
Simulation time 4483107721 ps
CPU time 159.31 seconds
Started Jan 03 02:12:30 PM PST 24
Finished Jan 03 02:15:19 PM PST 24
Peak memory 555108 kb
Host smart-f63abf3e-1e4f-4873-aef9-accf1bb2cc9c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549492827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.1549492827
Directory /workspace/90.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.4263287874
Short name T1872
Test name
Test status
Simulation time 14368913416 ps
CPU time 510.42 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:21:20 PM PST 24
Peak memory 555364 kb
Host smart-5ac570b9-c9f4-479d-a164-62f8d9a7d1ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263287874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.4263287874
Directory /workspace/90.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.3966118742
Short name T1300
Test name
Test status
Simulation time 12143476657 ps
CPU time 1111.94 seconds
Started Jan 03 02:12:34 PM PST 24
Finished Jan 03 02:31:18 PM PST 24
Peak memory 567300 kb
Host smart-cd278d41-d26f-4513-a8f8-48ad388f79c3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966118742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all
_with_rand_reset.3966118742
Directory /workspace/90.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.2037072058
Short name T1532
Test name
Test status
Simulation time 20771264477 ps
CPU time 776.94 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:25:47 PM PST 24
Peak memory 559076 kb
Host smart-53379ec6-945a-4313-a53c-e8a8528be992
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037072058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al
l_with_reset_error.2037072058
Directory /workspace/90.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.2895317837
Short name T1002
Test name
Test status
Simulation time 314920046 ps
CPU time 35.14 seconds
Started Jan 03 02:12:31 PM PST 24
Finished Jan 03 02:13:16 PM PST 24
Peak memory 553944 kb
Host smart-0948928a-50a2-47d0-b8a9-b2d5cced42a9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895317837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.2895317837
Directory /workspace/90.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_access_same_device.60651801
Short name T622
Test name
Test status
Simulation time 2038611364 ps
CPU time 76.91 seconds
Started Jan 03 02:12:43 PM PST 24
Finished Jan 03 02:14:16 PM PST 24
Peak memory 553960 kb
Host smart-758ede3a-7729-458e-bc33-afceb7d6556f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60651801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device.60651801
Directory /workspace/91.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.889939928
Short name T153
Test name
Test status
Simulation time 29822776095 ps
CPU time 479.35 seconds
Started Jan 03 02:12:42 PM PST 24
Finished Jan 03 02:20:58 PM PST 24
Peak memory 554232 kb
Host smart-39f3bb08-2032-4b04-85db-48abd1dfb347
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889939928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_d
evice_slow_rsp.889939928
Directory /workspace/91.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3787597000
Short name T365
Test name
Test status
Simulation time 1052165648 ps
CPU time 36.34 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:57 PM PST 24
Peak memory 553860 kb
Host smart-e4462d9a-282f-462b-a578-028579e490b4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787597000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add
r.3787597000
Directory /workspace/91.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_error_random.1433853256
Short name T434
Test name
Test status
Simulation time 1592433421 ps
CPU time 47.64 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:14:02 PM PST 24
Peak memory 553912 kb
Host smart-a97a84fa-7fa0-4e89-a956-273ca2f357b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433853256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.1433853256
Directory /workspace/91.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random.2048425173
Short name T1172
Test name
Test status
Simulation time 427486867 ps
CPU time 16.02 seconds
Started Jan 03 02:12:52 PM PST 24
Finished Jan 03 02:13:24 PM PST 24
Peak memory 554132 kb
Host smart-32711d04-7550-45db-8e58-48d691310583
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048425173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.2048425173
Directory /workspace/91.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.1330774850
Short name T452
Test name
Test status
Simulation time 74537080748 ps
CPU time 767.8 seconds
Started Jan 03 02:12:42 PM PST 24
Finished Jan 03 02:25:46 PM PST 24
Peak memory 553156 kb
Host smart-76b7a44e-c479-471b-aa56-694b5d9187da
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330774850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.1330774850
Directory /workspace/91.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.3110166075
Short name T1881
Test name
Test status
Simulation time 3529769082 ps
CPU time 59.01 seconds
Started Jan 03 02:12:45 PM PST 24
Finished Jan 03 02:14:00 PM PST 24
Peak memory 551864 kb
Host smart-78e91240-a491-490b-b27f-731eaa3fb1b1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110166075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.3110166075
Directory /workspace/91.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.567477422
Short name T195
Test name
Test status
Simulation time 288183627 ps
CPU time 22.49 seconds
Started Jan 03 02:12:52 PM PST 24
Finished Jan 03 02:13:30 PM PST 24
Peak memory 554100 kb
Host smart-d990cc58-4bfc-4c4f-b51a-1d2a33e70d91
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567477422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_dela
ys.567477422
Directory /workspace/91.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_same_source.1224660036
Short name T1359
Test name
Test status
Simulation time 270110651 ps
CPU time 20.09 seconds
Started Jan 03 02:12:42 PM PST 24
Finished Jan 03 02:13:18 PM PST 24
Peak memory 553904 kb
Host smart-b9fc51dd-e6ad-4e59-82dd-6e049182f380
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224660036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.1224660036
Directory /workspace/91.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke.3577767931
Short name T1256
Test name
Test status
Simulation time 229272285 ps
CPU time 8.96 seconds
Started Jan 03 02:12:54 PM PST 24
Finished Jan 03 02:13:18 PM PST 24
Peak memory 551764 kb
Host smart-f4939c8f-a7e3-4c89-ac77-6962db9b8e1f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577767931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.3577767931
Directory /workspace/91.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.1528476656
Short name T1722
Test name
Test status
Simulation time 9302114756 ps
CPU time 95.96 seconds
Started Jan 03 02:12:35 PM PST 24
Finished Jan 03 02:14:24 PM PST 24
Peak memory 551724 kb
Host smart-f8d7898f-cbc5-42c3-886a-18b87998543e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528476656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.1528476656
Directory /workspace/91.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.2565678789
Short name T1215
Test name
Test status
Simulation time 5579522024 ps
CPU time 98.55 seconds
Started Jan 03 02:12:39 PM PST 24
Finished Jan 03 02:14:33 PM PST 24
Peak memory 552156 kb
Host smart-2ac3afc0-cd65-4844-b5af-ac3ebd34af98
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565678789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.2565678789
Directory /workspace/91.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.986199958
Short name T559
Test name
Test status
Simulation time 46552541 ps
CPU time 5.97 seconds
Started Jan 03 02:12:35 PM PST 24
Finished Jan 03 02:12:54 PM PST 24
Peak memory 551728 kb
Host smart-9261c1f7-6786-4269-88ac-47b4bf07dcce
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986199958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays
.986199958
Directory /workspace/91.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all.1705711532
Short name T796
Test name
Test status
Simulation time 1772974955 ps
CPU time 111.17 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:15:09 PM PST 24
Peak memory 554304 kb
Host smart-f08681b0-1017-49d3-a02f-6cf796af06e7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705711532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.1705711532
Directory /workspace/91.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.3929575405
Short name T563
Test name
Test status
Simulation time 3694589976 ps
CPU time 111.46 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:15:12 PM PST 24
Peak memory 554512 kb
Host smart-29f08540-4212-4858-abb6-0e8cadc64676
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929575405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.3929575405
Directory /workspace/91.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.1149812908
Short name T362
Test name
Test status
Simulation time 113941875 ps
CPU time 50.9 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:14:07 PM PST 24
Peak memory 553312 kb
Host smart-d35a8993-5e66-4207-8633-1ad26966d4ec
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149812908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all
_with_rand_reset.1149812908
Directory /workspace/91.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.1352547952
Short name T1884
Test name
Test status
Simulation time 1778544298 ps
CPU time 260.73 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:17:40 PM PST 24
Peak memory 558928 kb
Host smart-0fd07e7d-7053-482e-afdc-71c86749d750
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352547952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al
l_with_reset_error.1352547952
Directory /workspace/91.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.1273226149
Short name T565
Test name
Test status
Simulation time 298097203 ps
CPU time 35.45 seconds
Started Jan 03 02:12:42 PM PST 24
Finished Jan 03 02:13:34 PM PST 24
Peak memory 553128 kb
Host smart-5fdc5b94-8398-4424-bcb1-c75b7dad6e7f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273226149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.1273226149
Directory /workspace/91.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_access_same_device.2547207267
Short name T1110
Test name
Test status
Simulation time 116849483 ps
CPU time 13.22 seconds
Started Jan 03 02:12:39 PM PST 24
Finished Jan 03 02:13:08 PM PST 24
Peak memory 553176 kb
Host smart-a34987f6-8cbb-4c86-b0ab-2bdf400779cc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547207267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device
.2547207267
Directory /workspace/92.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.2255522252
Short name T88
Test name
Test status
Simulation time 101559905253 ps
CPU time 1488.9 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:38:10 PM PST 24
Peak memory 555268 kb
Host smart-13b46c81-02ea-40fa-9f8a-5fa5f7f64ae9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255522252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_
device_slow_rsp.2255522252
Directory /workspace/92.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.966028758
Short name T1875
Test name
Test status
Simulation time 1115184110 ps
CPU time 38.49 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:13:56 PM PST 24
Peak memory 554164 kb
Host smart-d67ca0e7-27b8-4f67-a963-452020423317
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966028758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_addr
.966028758
Directory /workspace/92.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_error_random.2408545697
Short name T1535
Test name
Test status
Simulation time 624047537 ps
CPU time 43.29 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:14:05 PM PST 24
Peak memory 552896 kb
Host smart-53b137ec-a8d4-4456-94ed-06251a51567e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408545697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.2408545697
Directory /workspace/92.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random.1040288350
Short name T1050
Test name
Test status
Simulation time 1320406907 ps
CPU time 45.42 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:14:02 PM PST 24
Peak memory 554208 kb
Host smart-543cbd99-ceca-4225-9a66-383e62489621
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040288350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.1040288350
Directory /workspace/92.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.1139490536
Short name T1021
Test name
Test status
Simulation time 88992609924 ps
CPU time 864.33 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:27:47 PM PST 24
Peak memory 553952 kb
Host smart-8731e49d-c55f-40b6-8877-d134e79423cf
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139490536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.1139490536
Directory /workspace/92.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.216493479
Short name T636
Test name
Test status
Simulation time 6862110497 ps
CPU time 107.13 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:15:08 PM PST 24
Peak memory 554172 kb
Host smart-a8c06fce-f9d4-4f3b-8eb3-818a1980de49
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216493479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.216493479
Directory /workspace/92.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.3096570595
Short name T399
Test name
Test status
Simulation time 351375077 ps
CPU time 28.27 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:49 PM PST 24
Peak memory 554152 kb
Host smart-0588c48e-04e6-4fee-8682-6bc3c7c0d619
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096570595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del
ays.3096570595
Directory /workspace/92.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_same_source.3913565191
Short name T891
Test name
Test status
Simulation time 1041535580 ps
CPU time 29.54 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:13:52 PM PST 24
Peak memory 553768 kb
Host smart-8d0cb8ef-a111-4e04-ae3f-d348929fb877
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913565191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.3913565191
Directory /workspace/92.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke.2652708543
Short name T739
Test name
Test status
Simulation time 55133401 ps
CPU time 6.3 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:27 PM PST 24
Peak memory 551612 kb
Host smart-b9bcf327-e031-424d-927a-a246d6837375
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652708543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.2652708543
Directory /workspace/92.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.2117205393
Short name T415
Test name
Test status
Simulation time 9300296976 ps
CPU time 96.76 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:14:55 PM PST 24
Peak memory 551676 kb
Host smart-13d558c4-4787-4f02-a0b8-31dcfa838326
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117205393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.2117205393
Directory /workspace/92.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.4015789150
Short name T1877
Test name
Test status
Simulation time 4032094808 ps
CPU time 64.32 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:14:21 PM PST 24
Peak memory 551860 kb
Host smart-6e456969-48e3-471f-a0c4-ed3b1fbbccec
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015789150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.4015789150
Directory /workspace/92.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2455773207
Short name T1669
Test name
Test status
Simulation time 47777637 ps
CPU time 5.96 seconds
Started Jan 03 02:12:38 PM PST 24
Finished Jan 03 02:13:00 PM PST 24
Peak memory 552060 kb
Host smart-ab15acf9-a2fc-43c6-909b-1a26eddc5d59
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455773207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay
s.2455773207
Directory /workspace/92.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all.4047906176
Short name T1845
Test name
Test status
Simulation time 3301154682 ps
CPU time 238.78 seconds
Started Jan 03 02:12:38 PM PST 24
Finished Jan 03 02:16:53 PM PST 24
Peak memory 555476 kb
Host smart-86097792-086c-4406-82da-3e2072b966f7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047906176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.4047906176
Directory /workspace/92.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.2233784057
Short name T889
Test name
Test status
Simulation time 6047989005 ps
CPU time 198.23 seconds
Started Jan 03 02:12:40 PM PST 24
Finished Jan 03 02:16:14 PM PST 24
Peak memory 555396 kb
Host smart-b41eb3a1-8311-49c2-9085-df01883baf47
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233784057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.2233784057
Directory /workspace/92.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.1480842147
Short name T1668
Test name
Test status
Simulation time 225690466 ps
CPU time 35.69 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:13:58 PM PST 24
Peak memory 555028 kb
Host smart-08bd0cd3-60f9-48ca-948c-5cb597e8e89c
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480842147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all
_with_rand_reset.1480842147
Directory /workspace/92.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.2528850656
Short name T336
Test name
Test status
Simulation time 4680049286 ps
CPU time 290.95 seconds
Started Jan 03 02:12:31 PM PST 24
Finished Jan 03 02:17:32 PM PST 24
Peak memory 558184 kb
Host smart-7a1be355-4be8-4b9f-88c4-c6a8fe81df11
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528850656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al
l_with_reset_error.2528850656
Directory /workspace/92.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.1938457764
Short name T1575
Test name
Test status
Simulation time 225584903 ps
CPU time 22.33 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:43 PM PST 24
Peak memory 553052 kb
Host smart-fe4fd8ba-1e65-4ec0-82eb-353635910bca
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938457764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.1938457764
Directory /workspace/92.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_access_same_device.2730699363
Short name T1037
Test name
Test status
Simulation time 908745783 ps
CPU time 72.11 seconds
Started Jan 03 02:12:36 PM PST 24
Finished Jan 03 02:14:02 PM PST 24
Peak memory 553840 kb
Host smart-0ae72880-5fee-4933-81f2-35e588691261
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730699363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device
.2730699363
Directory /workspace/93.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.576684349
Short name T688
Test name
Test status
Simulation time 70567606135 ps
CPU time 1154.05 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:32:07 PM PST 24
Peak memory 553916 kb
Host smart-2d45746a-d4fb-4e21-94ca-a59df8585113
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576684349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_d
evice_slow_rsp.576684349
Directory /workspace/93.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.1095677018
Short name T863
Test name
Test status
Simulation time 76555241 ps
CPU time 5.9 seconds
Started Jan 03 02:12:57 PM PST 24
Finished Jan 03 02:13:18 PM PST 24
Peak memory 551664 kb
Host smart-6425d059-09ff-4aa7-8cbe-8cea92332abc
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095677018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add
r.1095677018
Directory /workspace/93.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_error_random.1211356067
Short name T520
Test name
Test status
Simulation time 32423739 ps
CPU time 5.27 seconds
Started Jan 03 02:12:37 PM PST 24
Finished Jan 03 02:12:57 PM PST 24
Peak memory 551732 kb
Host smart-4c74b68f-f94b-436f-8684-623806a637ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211356067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.1211356067
Directory /workspace/93.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random.4060310309
Short name T262
Test name
Test status
Simulation time 2189068367 ps
CPU time 78.41 seconds
Started Jan 03 02:12:26 PM PST 24
Finished Jan 03 02:13:55 PM PST 24
Peak memory 553932 kb
Host smart-424a2e8c-6e15-4941-bf67-6ffe105938c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060310309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.4060310309
Directory /workspace/93.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.2556551269
Short name T1789
Test name
Test status
Simulation time 42953909029 ps
CPU time 480.71 seconds
Started Jan 03 02:12:38 PM PST 24
Finished Jan 03 02:20:54 PM PST 24
Peak memory 554172 kb
Host smart-83a79d1a-abdc-49a2-b3b1-bad67eaa5e14
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556551269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.2556551269
Directory /workspace/93.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.1488264583
Short name T1201
Test name
Test status
Simulation time 41761311305 ps
CPU time 686.38 seconds
Started Jan 03 02:12:41 PM PST 24
Finished Jan 03 02:24:23 PM PST 24
Peak memory 554264 kb
Host smart-e3df6ef3-aa69-4030-9c6d-139730968d8d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488264583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.1488264583
Directory /workspace/93.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.2077304200
Short name T554
Test name
Test status
Simulation time 463038218 ps
CPU time 42.82 seconds
Started Jan 03 02:12:30 PM PST 24
Finished Jan 03 02:13:23 PM PST 24
Peak memory 553928 kb
Host smart-982b0d3d-536d-4bbf-9c29-a8e9c4444c3a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077304200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del
ays.2077304200
Directory /workspace/93.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_same_source.2996299918
Short name T79
Test name
Test status
Simulation time 1595171411 ps
CPU time 45.13 seconds
Started Jan 03 02:12:33 PM PST 24
Finished Jan 03 02:13:30 PM PST 24
Peak memory 553052 kb
Host smart-1f8105a8-156b-4deb-b6fb-2c53fd0ce023
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996299918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.2996299918
Directory /workspace/93.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke.1537486922
Short name T1524
Test name
Test status
Simulation time 43086938 ps
CPU time 5.84 seconds
Started Jan 03 02:12:26 PM PST 24
Finished Jan 03 02:12:42 PM PST 24
Peak memory 552052 kb
Host smart-a20fd4bb-b55d-4e9b-b2ee-4c4a6b695f16
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537486922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.1537486922
Directory /workspace/93.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.1976045300
Short name T1563
Test name
Test status
Simulation time 8587784958 ps
CPU time 91.01 seconds
Started Jan 03 02:12:34 PM PST 24
Finished Jan 03 02:14:16 PM PST 24
Peak memory 552184 kb
Host smart-ba75b292-9996-4c2e-8cfb-82560f7a3bc9
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976045300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.1976045300
Directory /workspace/93.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.888892417
Short name T603
Test name
Test status
Simulation time 6644806603 ps
CPU time 119.84 seconds
Started Jan 03 02:12:32 PM PST 24
Finished Jan 03 02:14:42 PM PST 24
Peak memory 551860 kb
Host smart-df6d235b-4fb7-4360-8c92-0c68b994c196
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888892417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.888892417
Directory /workspace/93.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.3335421273
Short name T1001
Test name
Test status
Simulation time 49955852 ps
CPU time 5.79 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:27 PM PST 24
Peak memory 551996 kb
Host smart-41a746fd-d2e2-4010-b44b-8d40727e7e24
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335421273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay
s.3335421273
Directory /workspace/93.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all.1645798122
Short name T1462
Test name
Test status
Simulation time 3195547094 ps
CPU time 232.12 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:17:15 PM PST 24
Peak memory 554884 kb
Host smart-57fee015-671b-4cf1-b1c9-02beb475cf13
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645798122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.1645798122
Directory /workspace/93.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.335282119
Short name T905
Test name
Test status
Simulation time 829181189 ps
CPU time 78.42 seconds
Started Jan 03 02:13:16 PM PST 24
Finished Jan 03 02:15:01 PM PST 24
Peak memory 555288 kb
Host smart-0aa88138-34f0-4677-a7fd-3d241a0f14f3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335282119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.335282119
Directory /workspace/93.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.2829118465
Short name T1302
Test name
Test status
Simulation time 495467058 ps
CPU time 240.54 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:17:14 PM PST 24
Peak memory 556612 kb
Host smart-8fb2e173-39be-4375-babc-add7c991cef4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829118465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all
_with_rand_reset.2829118465
Directory /workspace/93.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2286782039
Short name T1690
Test name
Test status
Simulation time 126296732 ps
CPU time 57.93 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:14:14 PM PST 24
Peak memory 554804 kb
Host smart-f6a2b78c-c5df-412d-b592-c85cfc645a65
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286782039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al
l_with_reset_error.2286782039
Directory /workspace/93.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.1033841533
Short name T800
Test name
Test status
Simulation time 1242477135 ps
CPU time 44.86 seconds
Started Jan 03 02:12:53 PM PST 24
Finished Jan 03 02:13:54 PM PST 24
Peak memory 553896 kb
Host smart-bf9cbbae-c6d1-4fef-906d-3d323cb95784
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033841533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.1033841533
Directory /workspace/93.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_access_same_device.1177137554
Short name T167
Test name
Test status
Simulation time 3139796176 ps
CPU time 118.36 seconds
Started Jan 03 02:12:57 PM PST 24
Finished Jan 03 02:15:11 PM PST 24
Peak memory 553164 kb
Host smart-cb1aab46-3c58-4232-846a-372725595bfd
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177137554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device
.1177137554
Directory /workspace/94.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.214931458
Short name T1240
Test name
Test status
Simulation time 16066912692 ps
CPU time 275.97 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:18:18 PM PST 24
Peak memory 554268 kb
Host smart-01771a2c-0a9e-4a3a-b1a5-01414e8b1626
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214931458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_d
evice_slow_rsp.214931458
Directory /workspace/94.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3412783690
Short name T1774
Test name
Test status
Simulation time 1071891253 ps
CPU time 41.81 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:13:58 PM PST 24
Peak memory 553860 kb
Host smart-2a535a96-ea72-4398-8930-33efb37eee6b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412783690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add
r.3412783690
Directory /workspace/94.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_error_random.1343293325
Short name T907
Test name
Test status
Simulation time 1025246092 ps
CPU time 36.5 seconds
Started Jan 03 02:13:16 PM PST 24
Finished Jan 03 02:14:19 PM PST 24
Peak memory 553872 kb
Host smart-302bbd12-c54e-4114-8174-b4e0ce6036fe
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343293325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.1343293325
Directory /workspace/94.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random.3848237968
Short name T1588
Test name
Test status
Simulation time 1316567475 ps
CPU time 41.64 seconds
Started Jan 03 02:17:39 PM PST 24
Finished Jan 03 02:18:23 PM PST 24
Peak memory 553868 kb
Host smart-5d1c7221-96ce-4cc0-b07b-46225e119ff0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848237968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.3848237968
Directory /workspace/94.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.1621574886
Short name T1072
Test name
Test status
Simulation time 42798018517 ps
CPU time 447.19 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:20:41 PM PST 24
Peak memory 554280 kb
Host smart-5e43cbb1-65e3-437b-8aff-bb46b9c78b95
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621574886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.1621574886
Directory /workspace/94.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.228369327
Short name T761
Test name
Test status
Simulation time 66012460575 ps
CPU time 1079.54 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:31:14 PM PST 24
Peak memory 554024 kb
Host smart-c768f0e3-bc6d-412b-9233-2e0dcbc76b6f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228369327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.228369327
Directory /workspace/94.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.1864968235
Short name T640
Test name
Test status
Simulation time 300676518 ps
CPU time 28.11 seconds
Started Jan 03 02:13:14 PM PST 24
Finished Jan 03 02:14:09 PM PST 24
Peak memory 554244 kb
Host smart-ed7be4f9-8877-4217-9a82-781e8fd277f6
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864968235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del
ays.1864968235
Directory /workspace/94.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_same_source.978609300
Short name T717
Test name
Test status
Simulation time 554860734 ps
CPU time 38.15 seconds
Started Jan 03 02:13:17 PM PST 24
Finished Jan 03 02:14:22 PM PST 24
Peak memory 554204 kb
Host smart-686ecd90-216d-458a-a6a2-9a0cae70bbd4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978609300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.978609300
Directory /workspace/94.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke.2253089671
Short name T1178
Test name
Test status
Simulation time 166024210 ps
CPU time 8.05 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:13:50 PM PST 24
Peak memory 551748 kb
Host smart-3b82bc03-1302-4b46-a944-f34c91cd9328
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253089671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.2253089671
Directory /workspace/94.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.1966990544
Short name T1784
Test name
Test status
Simulation time 7905348261 ps
CPU time 82 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:15:04 PM PST 24
Peak memory 551788 kb
Host smart-93742efc-9244-4dec-94ab-3935f6375afc
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966990544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.1966990544
Directory /workspace/94.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.3130475570
Short name T470
Test name
Test status
Simulation time 4663651594 ps
CPU time 79.35 seconds
Started Jan 03 02:13:17 PM PST 24
Finished Jan 03 02:15:03 PM PST 24
Peak memory 552128 kb
Host smart-f06f883b-0d6a-4467-b688-e4d694712b9f
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130475570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.3130475570
Directory /workspace/94.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.2341043616
Short name T558
Test name
Test status
Simulation time 46806393 ps
CPU time 5.94 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:13:20 PM PST 24
Peak memory 552168 kb
Host smart-541fd398-9684-4e82-b671-db52ce56e744
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341043616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay
s.2341043616
Directory /workspace/94.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all.1765619329
Short name T1109
Test name
Test status
Simulation time 1454480473 ps
CPU time 58.48 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:14:16 PM PST 24
Peak memory 554292 kb
Host smart-5297e09d-21a3-4f68-99f9-58fd9f88d29f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765619329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.1765619329
Directory /workspace/94.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.1663436314
Short name T957
Test name
Test status
Simulation time 6721173347 ps
CPU time 221.92 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:17:05 PM PST 24
Peak memory 555368 kb
Host smart-45082668-aa3a-465f-ae47-9317ab2ad9cf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663436314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.1663436314
Directory /workspace/94.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.991405682
Short name T183
Test name
Test status
Simulation time 1461981780 ps
CPU time 206.49 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:16:49 PM PST 24
Peak memory 557012 kb
Host smart-9ac5b08b-b352-4e3a-b851-d1a4603ad6a2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991405682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res
et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_
with_rand_reset.991405682
Directory /workspace/94.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.3623475853
Short name T917
Test name
Test status
Simulation time 186699278 ps
CPU time 52.69 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:14:06 PM PST 24
Peak memory 555020 kb
Host smart-205ddd48-34db-4abd-848b-2902757d10a7
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623475853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al
l_with_reset_error.3623475853
Directory /workspace/94.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.2148883220
Short name T676
Test name
Test status
Simulation time 60319122 ps
CPU time 8.82 seconds
Started Jan 03 02:12:43 PM PST 24
Finished Jan 03 02:13:07 PM PST 24
Peak memory 552896 kb
Host smart-75c33289-bd61-453e-822a-f02d619cb121
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148883220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.2148883220
Directory /workspace/94.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_access_same_device.1564145561
Short name T303
Test name
Test status
Simulation time 303365154 ps
CPU time 17.95 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:13:37 PM PST 24
Peak memory 554012 kb
Host smart-56dd2932-e1fe-471b-bd04-6797797b3284
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564145561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device
.1564145561
Directory /workspace/95.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.3047424322
Short name T495
Test name
Test status
Simulation time 5282277483 ps
CPU time 85.63 seconds
Started Jan 03 02:13:16 PM PST 24
Finished Jan 03 02:15:08 PM PST 24
Peak memory 551848 kb
Host smart-e716f12f-8766-491d-8cf9-18ddd108b76b
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047424322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_
device_slow_rsp.3047424322
Directory /workspace/95.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.3033187723
Short name T405
Test name
Test status
Simulation time 305747045 ps
CPU time 14.86 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:13:28 PM PST 24
Peak memory 554116 kb
Host smart-58ff470d-0953-42b0-92f1-5176902a3aad
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033187723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add
r.3033187723
Directory /workspace/95.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_error_random.2596949113
Short name T1541
Test name
Test status
Simulation time 854985479 ps
CPU time 31.98 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:13:47 PM PST 24
Peak memory 554080 kb
Host smart-0f45af4b-7876-4b0b-ad9d-39c14170809f
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596949113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.2596949113
Directory /workspace/95.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random.2539881481
Short name T1086
Test name
Test status
Simulation time 162155628 ps
CPU time 14.83 seconds
Started Jan 03 02:13:17 PM PST 24
Finished Jan 03 02:13:59 PM PST 24
Peak memory 554160 kb
Host smart-9da49375-8786-4f0e-87fe-afd3e17da587
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539881481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.2539881481
Directory /workspace/95.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.1149269922
Short name T1593
Test name
Test status
Simulation time 77217308244 ps
CPU time 739.95 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:25:37 PM PST 24
Peak memory 553944 kb
Host smart-2d2f9780-9805-436d-8da0-b2a875ee62d7
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149269922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.1149269922
Directory /workspace/95.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.2537987791
Short name T1543
Test name
Test status
Simulation time 66258914209 ps
CPU time 1085.11 seconds
Started Jan 03 02:12:57 PM PST 24
Finished Jan 03 02:31:18 PM PST 24
Peak memory 554284 kb
Host smart-d017e06e-76f7-4231-b668-398277b131f2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537987791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.2537987791
Directory /workspace/95.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.1249031710
Short name T1501
Test name
Test status
Simulation time 37941689 ps
CPU time 6.48 seconds
Started Jan 03 02:13:16 PM PST 24
Finished Jan 03 02:13:49 PM PST 24
Peak memory 551796 kb
Host smart-a71d27aa-e75d-4c24-9f05-23f6506b327a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249031710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del
ays.1249031710
Directory /workspace/95.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_same_source.532337359
Short name T181
Test name
Test status
Simulation time 2258755319 ps
CPU time 59.45 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:14:16 PM PST 24
Peak memory 554264 kb
Host smart-530439b6-b51a-4e17-807e-999826fc110d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532337359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.532337359
Directory /workspace/95.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke.3978586073
Short name T1521
Test name
Test status
Simulation time 45181700 ps
CPU time 5.9 seconds
Started Jan 03 02:13:17 PM PST 24
Finished Jan 03 02:13:50 PM PST 24
Peak memory 551772 kb
Host smart-27bfd3c5-f74d-42e6-b822-7fd09ba3cb3b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978586073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.3978586073
Directory /workspace/95.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.3345085110
Short name T682
Test name
Test status
Simulation time 5922403895 ps
CPU time 63.01 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:14:19 PM PST 24
Peak memory 552108 kb
Host smart-71755760-615a-4ef5-b729-2b9112663cfd
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345085110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.3345085110
Directory /workspace/95.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.794953798
Short name T1620
Test name
Test status
Simulation time 4093897579 ps
CPU time 70.74 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:14:29 PM PST 24
Peak memory 551884 kb
Host smart-37f9669c-5635-4a78-84a5-d5166a7de5a0
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794953798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.794953798
Directory /workspace/95.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.685832362
Short name T1634
Test name
Test status
Simulation time 51968315 ps
CPU time 6.49 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:13:24 PM PST 24
Peak memory 551812 kb
Host smart-be7c41df-1755-4ced-900d-4649bdabff3a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685832362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays
.685832362
Directory /workspace/95.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all.2539932408
Short name T1116
Test name
Test status
Simulation time 12053647570 ps
CPU time 449.12 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:20:44 PM PST 24
Peak memory 555776 kb
Host smart-1bd76b31-0dc7-4c75-b474-8bb5d7dab9b2
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539932408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.2539932408
Directory /workspace/95.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.4216985792
Short name T419
Test name
Test status
Simulation time 898997374 ps
CPU time 67.43 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:14:28 PM PST 24
Peak memory 555240 kb
Host smart-ea8e9e37-4f30-47c7-b173-f33a90958a24
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216985792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.4216985792
Directory /workspace/95.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.2261234956
Short name T1350
Test name
Test status
Simulation time 348654163 ps
CPU time 126.94 seconds
Started Jan 03 02:13:01 PM PST 24
Finished Jan 03 02:15:26 PM PST 24
Peak memory 555096 kb
Host smart-00c81279-9199-478b-9dc7-74247cf62a1d
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261234956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all
_with_rand_reset.2261234956
Directory /workspace/95.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.720316241
Short name T344
Test name
Test status
Simulation time 107163020 ps
CPU time 40.3 seconds
Started Jan 03 02:13:03 PM PST 24
Finished Jan 03 02:14:04 PM PST 24
Peak memory 554064 kb
Host smart-49c804db-eaf8-4acb-ace2-cbc13a43c8ab
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720316241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all
_with_reset_error.720316241
Directory /workspace/95.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.4116618615
Short name T1659
Test name
Test status
Simulation time 1382590424 ps
CPU time 58 seconds
Started Jan 03 02:13:13 PM PST 24
Finished Jan 03 02:14:37 PM PST 24
Peak memory 554256 kb
Host smart-6a527abb-ae32-42a6-a929-7062f4d6653e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116618615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.4116618615
Directory /workspace/95.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_access_same_device.28032021
Short name T692
Test name
Test status
Simulation time 951544667 ps
CPU time 73.95 seconds
Started Jan 03 02:12:59 PM PST 24
Finished Jan 03 02:14:29 PM PST 24
Peak memory 553924 kb
Host smart-0a5bc86a-df9a-4acc-8a49-56c757ae58c9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28032021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device.28032021
Directory /workspace/96.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2253160087
Short name T1048
Test name
Test status
Simulation time 12907668890 ps
CPU time 226.34 seconds
Started Jan 03 02:13:03 PM PST 24
Finished Jan 03 02:17:10 PM PST 24
Peak memory 554188 kb
Host smart-b57c219d-5075-435d-a25f-f6de998f08e3
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253160087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_
device_slow_rsp.2253160087
Directory /workspace/96.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.488556128
Short name T471
Test name
Test status
Simulation time 193587896 ps
CPU time 9.81 seconds
Started Jan 03 02:13:19 PM PST 24
Finished Jan 03 02:13:55 PM PST 24
Peak memory 552184 kb
Host smart-ae5fc73b-18d2-43fa-a77d-bb7ae22ceb40
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488556128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_addr
.488556128
Directory /workspace/96.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_error_random.874265812
Short name T1595
Test name
Test status
Simulation time 1156156707 ps
CPU time 35.5 seconds
Started Jan 03 02:13:19 PM PST 24
Finished Jan 03 02:14:20 PM PST 24
Peak memory 553828 kb
Host smart-664b16c0-f126-433a-adab-929476cfb3d1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874265812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.874265812
Directory /workspace/96.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random.755944364
Short name T705
Test name
Test status
Simulation time 238140761 ps
CPU time 21.75 seconds
Started Jan 03 02:13:16 PM PST 24
Finished Jan 03 02:14:05 PM PST 24
Peak memory 553908 kb
Host smart-1378c791-a267-4e11-91fa-09007a44f9d0
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755944364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.755944364
Directory /workspace/96.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.626310434
Short name T1156
Test name
Test status
Simulation time 86283903714 ps
CPU time 987.39 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:30:09 PM PST 24
Peak memory 554232 kb
Host smart-f6147d13-9f6b-4b17-bf20-be0cd473cd3d
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626310434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.626310434
Directory /workspace/96.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.3534973806
Short name T939
Test name
Test status
Simulation time 6510298216 ps
CPU time 114.93 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:15:37 PM PST 24
Peak memory 553184 kb
Host smart-7a6c507c-280d-43a0-831f-697b96e5e46c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534973806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.3534973806
Directory /workspace/96.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.2050170896
Short name T1010
Test name
Test status
Simulation time 256677553 ps
CPU time 22.64 seconds
Started Jan 03 02:13:03 PM PST 24
Finished Jan 03 02:13:46 PM PST 24
Peak memory 554120 kb
Host smart-3127dad3-354e-46ed-8ea6-b20d0b54c53d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050170896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del
ays.2050170896
Directory /workspace/96.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_same_source.357607809
Short name T1228
Test name
Test status
Simulation time 300409521 ps
CPU time 22.08 seconds
Started Jan 03 02:13:13 PM PST 24
Finished Jan 03 02:14:02 PM PST 24
Peak memory 553072 kb
Host smart-478656e6-ae69-4184-8776-fbba8bc5eb41
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357607809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.357607809
Directory /workspace/96.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke.2958576887
Short name T963
Test name
Test status
Simulation time 45764385 ps
CPU time 5.95 seconds
Started Jan 03 02:13:02 PM PST 24
Finished Jan 03 02:13:28 PM PST 24
Peak memory 551832 kb
Host smart-c039b45a-6125-422f-852a-652d48e8b503
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958576887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.2958576887
Directory /workspace/96.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.1878901006
Short name T1750
Test name
Test status
Simulation time 6147357802 ps
CPU time 66.14 seconds
Started Jan 03 02:13:16 PM PST 24
Finished Jan 03 02:14:49 PM PST 24
Peak memory 551868 kb
Host smart-2d0af8a7-5121-4d06-8157-3aaef1b12af4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878901006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.1878901006
Directory /workspace/96.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.1715608343
Short name T1867
Test name
Test status
Simulation time 6731746793 ps
CPU time 113.22 seconds
Started Jan 03 02:13:03 PM PST 24
Finished Jan 03 02:15:16 PM PST 24
Peak memory 551784 kb
Host smart-7a6572e8-3c3a-475a-9ce7-d4b601468b9c
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715608343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.1715608343
Directory /workspace/96.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.3744574638
Short name T1512
Test name
Test status
Simulation time 47109118 ps
CPU time 5.91 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:13:47 PM PST 24
Peak memory 551812 kb
Host smart-72eacbfc-01a4-440f-aff1-b93709ade4b3
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744574638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay
s.3744574638
Directory /workspace/96.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all.1904766091
Short name T158
Test name
Test status
Simulation time 2796180515 ps
CPU time 217.54 seconds
Started Jan 03 02:13:14 PM PST 24
Finished Jan 03 02:17:18 PM PST 24
Peak memory 556004 kb
Host smart-e9b2db50-eabc-4c49-bf5a-a38f614be908
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904766091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.1904766091
Directory /workspace/96.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.4256163166
Short name T203
Test name
Test status
Simulation time 10616517527 ps
CPU time 364.95 seconds
Started Jan 03 02:13:12 PM PST 24
Finished Jan 03 02:19:43 PM PST 24
Peak memory 555348 kb
Host smart-0a40bfdb-778d-452f-ad58-06333bbf638a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256163166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.4256163166
Directory /workspace/96.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.2473111348
Short name T1375
Test name
Test status
Simulation time 535097178 ps
CPU time 169.24 seconds
Started Jan 03 02:13:19 PM PST 24
Finished Jan 03 02:16:35 PM PST 24
Peak memory 555132 kb
Host smart-2289d68e-6662-469b-9e77-d2eb8e2de38b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473111348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all
_with_rand_reset.2473111348
Directory /workspace/96.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3312710286
Short name T848
Test name
Test status
Simulation time 2583857165 ps
CPU time 259.3 seconds
Started Jan 03 02:13:22 PM PST 24
Finished Jan 03 02:18:07 PM PST 24
Peak memory 559148 kb
Host smart-0a20f0e8-0bfb-40ad-9f70-1fcebb990ae3
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312710286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al
l_with_reset_error.3312710286
Directory /workspace/96.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.708239913
Short name T942
Test name
Test status
Simulation time 137518497 ps
CPU time 15.69 seconds
Started Jan 03 02:13:00 PM PST 24
Finished Jan 03 02:13:33 PM PST 24
Peak memory 553112 kb
Host smart-c358e614-f226-40e7-86f8-2ffe06199ace
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708239913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.708239913
Directory /workspace/96.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_access_same_device.3028756773
Short name T1792
Test name
Test status
Simulation time 127748699 ps
CPU time 13.42 seconds
Started Jan 03 02:13:31 PM PST 24
Finished Jan 03 02:14:09 PM PST 24
Peak memory 553136 kb
Host smart-625303cb-f275-440e-ad19-1fee4420b2b1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028756773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device
.3028756773
Directory /workspace/97.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.3506350001
Short name T1234
Test name
Test status
Simulation time 114177519099 ps
CPU time 1891.9 seconds
Started Jan 03 02:13:19 PM PST 24
Finished Jan 03 02:45:18 PM PST 24
Peak memory 553952 kb
Host smart-17094b17-7c8c-4ca0-81da-535857c5b6a1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506350001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_
device_slow_rsp.3506350001
Directory /workspace/97.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.972815277
Short name T646
Test name
Test status
Simulation time 203313820 ps
CPU time 22.97 seconds
Started Jan 03 02:13:29 PM PST 24
Finished Jan 03 02:14:17 PM PST 24
Peak memory 553820 kb
Host smart-5e23b8f0-a34e-4602-b439-b177b2ccfa10
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972815277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_addr
.972815277
Directory /workspace/97.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_error_random.2646726313
Short name T1914
Test name
Test status
Simulation time 251208491 ps
CPU time 11.59 seconds
Started Jan 03 02:13:34 PM PST 24
Finished Jan 03 02:14:10 PM PST 24
Peak memory 552852 kb
Host smart-657dbfee-0a67-44c0-9d8f-cafdece4c339
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646726313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.2646726313
Directory /workspace/97.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random.367857532
Short name T1203
Test name
Test status
Simulation time 598898993 ps
CPU time 50.4 seconds
Started Jan 03 02:13:19 PM PST 24
Finished Jan 03 02:14:36 PM PST 24
Peak memory 553112 kb
Host smart-faca38d1-d26b-46dd-8b53-70909aa77448
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367857532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.367857532
Directory /workspace/97.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.1090436412
Short name T1223
Test name
Test status
Simulation time 17163067692 ps
CPU time 180.12 seconds
Started Jan 03 02:13:23 PM PST 24
Finished Jan 03 02:16:49 PM PST 24
Peak memory 554016 kb
Host smart-82b0c9e9-a45d-48b7-947b-a35b1176be69
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090436412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1090436412
Directory /workspace/97.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.1894730742
Short name T1123
Test name
Test status
Simulation time 19782092478 ps
CPU time 356.66 seconds
Started Jan 03 02:13:33 PM PST 24
Finished Jan 03 02:19:54 PM PST 24
Peak memory 553124 kb
Host smart-0e609f4f-b46b-4afb-9ea7-99d1ad162694
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894730742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.1894730742
Directory /workspace/97.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.174480216
Short name T909
Test name
Test status
Simulation time 445175883 ps
CPU time 36.28 seconds
Started Jan 03 02:13:18 PM PST 24
Finished Jan 03 02:14:21 PM PST 24
Peak memory 553808 kb
Host smart-4204c728-974b-49de-b3f1-28180f81c24a
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174480216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_dela
ys.174480216
Directory /workspace/97.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_same_source.39262273
Short name T1667
Test name
Test status
Simulation time 1730004642 ps
CPU time 46.42 seconds
Started Jan 03 02:13:31 PM PST 24
Finished Jan 03 02:14:42 PM PST 24
Peak memory 554168 kb
Host smart-83391a0e-3d98-4a0f-8c17-d211211fd753
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39262273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.39262273
Directory /workspace/97.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke.3722428133
Short name T637
Test name
Test status
Simulation time 157035075 ps
CPU time 7.73 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:13:50 PM PST 24
Peak memory 551804 kb
Host smart-8208a251-574c-4009-8b14-7809d9219dd5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722428133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.3722428133
Directory /workspace/97.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.3883967601
Short name T1846
Test name
Test status
Simulation time 11125174955 ps
CPU time 115 seconds
Started Jan 03 02:13:29 PM PST 24
Finished Jan 03 02:15:49 PM PST 24
Peak memory 552164 kb
Host smart-84d63711-360a-4fc5-a0e3-2a9b0745de08
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883967601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.3883967601
Directory /workspace/97.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.774006352
Short name T1745
Test name
Test status
Simulation time 4965899518 ps
CPU time 87.38 seconds
Started Jan 03 02:13:30 PM PST 24
Finished Jan 03 02:15:22 PM PST 24
Peak memory 551708 kb
Host smart-483920f6-d667-471b-a07e-af858b5d2112
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774006352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.774006352
Directory /workspace/97.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2052195791
Short name T1577
Test name
Test status
Simulation time 48361166 ps
CPU time 5.93 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:13:48 PM PST 24
Peak memory 551876 kb
Host smart-26c1aa35-2698-47e8-9b25-d746ffabf022
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052195791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay
s.2052195791
Directory /workspace/97.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all.3438233184
Short name T770
Test name
Test status
Simulation time 2080567464 ps
CPU time 174.07 seconds
Started Jan 03 02:13:29 PM PST 24
Finished Jan 03 02:16:48 PM PST 24
Peak memory 555348 kb
Host smart-11d44c56-cd85-4c8c-a100-d0a936781de1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438233184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.3438233184
Directory /workspace/97.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3311481902
Short name T332
Test name
Test status
Simulation time 12317717653 ps
CPU time 370.45 seconds
Started Jan 03 02:13:34 PM PST 24
Finished Jan 03 02:20:08 PM PST 24
Peak memory 555116 kb
Host smart-efd16e66-80c7-4070-80eb-b3a2c7bac708
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311481902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.3311481902
Directory /workspace/97.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.2280071497
Short name T1211
Test name
Test status
Simulation time 3442384422 ps
CPU time 434.78 seconds
Started Jan 03 02:13:18 PM PST 24
Finished Jan 03 02:20:59 PM PST 24
Peak memory 559132 kb
Host smart-bffab640-b9fc-4577-8f62-be761f0670e9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280071497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all
_with_rand_reset.2280071497
Directory /workspace/97.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.2893648607
Short name T311
Test name
Test status
Simulation time 5608866244 ps
CPU time 516.85 seconds
Started Jan 03 02:13:35 PM PST 24
Finished Jan 03 02:22:37 PM PST 24
Peak memory 559092 kb
Host smart-6653c927-12e3-418a-966e-3c2af264bf18
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893648607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al
l_with_reset_error.2893648607
Directory /workspace/97.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.3718481191
Short name T174
Test name
Test status
Simulation time 608798013 ps
CPU time 26.91 seconds
Started Jan 03 02:13:35 PM PST 24
Finished Jan 03 02:14:27 PM PST 24
Peak memory 553128 kb
Host smart-b7159018-61a7-480d-b88f-07538cd888f1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718481191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.3718481191
Directory /workspace/97.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_access_same_device.242277685
Short name T163
Test name
Test status
Simulation time 543340563 ps
CPU time 37.45 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:14:20 PM PST 24
Peak memory 554948 kb
Host smart-dde4b870-6113-45a1-a228-45c683cd2886
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242277685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device.
242277685
Directory /workspace/98.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.3939233349
Short name T440
Test name
Test status
Simulation time 1178164974 ps
CPU time 44.08 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:14:26 PM PST 24
Peak memory 553908 kb
Host smart-c3918b29-f97a-4388-94ac-3e1c50330801
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939233349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add
r.3939233349
Directory /workspace/98.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_error_random.2498206
Short name T465
Test name
Test status
Simulation time 2327775270 ps
CPU time 83.21 seconds
Started Jan 03 02:13:14 PM PST 24
Finished Jan 03 02:15:03 PM PST 24
Peak memory 554216 kb
Host smart-3669c6f6-4371-4a52-b272-540cac2d92ee
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.2498206
Directory /workspace/98.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random.3830560492
Short name T1279
Test name
Test status
Simulation time 1287431124 ps
CPU time 45.39 seconds
Started Jan 03 02:12:57 PM PST 24
Finished Jan 03 02:13:58 PM PST 24
Peak memory 554144 kb
Host smart-4b39e23f-d295-40f4-84e4-600cec71850b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830560492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.3830560492
Directory /workspace/98.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.1290525873
Short name T1560
Test name
Test status
Simulation time 67038833028 ps
CPU time 725.99 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:25:48 PM PST 24
Peak memory 553960 kb
Host smart-2b7999cd-7103-4110-9260-8b866db55295
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290525873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.1290525873
Directory /workspace/98.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.927350529
Short name T1262
Test name
Test status
Simulation time 64986800641 ps
CPU time 1118.6 seconds
Started Jan 03 02:12:58 PM PST 24
Finished Jan 03 02:31:52 PM PST 24
Peak memory 553980 kb
Host smart-8401dda7-2f67-4e61-9ade-9fd38a4c5a79
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927350529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.927350529
Directory /workspace/98.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1990044418
Short name T245
Test name
Test status
Simulation time 111538412 ps
CPU time 12.47 seconds
Started Jan 03 02:13:17 PM PST 24
Finished Jan 03 02:13:56 PM PST 24
Peak memory 554252 kb
Host smart-31238377-3850-4285-9258-46ebeefd46a8
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990044418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del
ays.1990044418
Directory /workspace/98.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_same_source.335419812
Short name T1286
Test name
Test status
Simulation time 84802780 ps
CPU time 9.15 seconds
Started Jan 03 02:13:30 PM PST 24
Finished Jan 03 02:14:04 PM PST 24
Peak memory 554116 kb
Host smart-80dc2acb-93e4-48b5-b738-674ea7077ad1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335419812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.335419812
Directory /workspace/98.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke.1826338469
Short name T1477
Test name
Test status
Simulation time 176751407 ps
CPU time 7.9 seconds
Started Jan 03 02:13:31 PM PST 24
Finished Jan 03 02:14:04 PM PST 24
Peak memory 552104 kb
Host smart-ddbac487-9f43-481c-a59c-7eb563d14ec9
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826338469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.1826338469
Directory /workspace/98.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.4052169638
Short name T840
Test name
Test status
Simulation time 7068735527 ps
CPU time 78.92 seconds
Started Jan 03 02:13:35 PM PST 24
Finished Jan 03 02:15:18 PM PST 24
Peak memory 551716 kb
Host smart-1315429b-4511-4671-a534-f1323bb8e0ee
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052169638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.4052169638
Directory /workspace/98.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.2644817359
Short name T1283
Test name
Test status
Simulation time 5187969453 ps
CPU time 89.19 seconds
Started Jan 03 02:13:35 PM PST 24
Finished Jan 03 02:15:29 PM PST 24
Peak memory 552104 kb
Host smart-bd5fcdf9-4fcf-4c23-bb8c-1146182ba9a1
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644817359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.2644817359
Directory /workspace/98.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2528851245
Short name T550
Test name
Test status
Simulation time 48368171 ps
CPU time 6.39 seconds
Started Jan 03 02:13:30 PM PST 24
Finished Jan 03 02:14:01 PM PST 24
Peak memory 551884 kb
Host smart-6249bf9e-bbab-4224-a6b3-913a20f01e51
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528851245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay
s.2528851245
Directory /workspace/98.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all.263172080
Short name T1696
Test name
Test status
Simulation time 678846251 ps
CPU time 50.01 seconds
Started Jan 03 02:13:19 PM PST 24
Finished Jan 03 02:14:35 PM PST 24
Peak memory 553952 kb
Host smart-adef23b0-af99-400d-aa9c-549ee4f3f63a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263172080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.263172080
Directory /workspace/98.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.3591412125
Short name T768
Test name
Test status
Simulation time 5019074198 ps
CPU time 165.63 seconds
Started Jan 03 02:13:17 PM PST 24
Finished Jan 03 02:16:30 PM PST 24
Peak memory 555408 kb
Host smart-8d4288c7-28f0-4ea4-9bb8-3d61af135fb4
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591412125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.3591412125
Directory /workspace/98.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3876959601
Short name T806
Test name
Test status
Simulation time 103522816 ps
CPU time 25.65 seconds
Started Jan 03 02:13:19 PM PST 24
Finished Jan 03 02:14:11 PM PST 24
Peak memory 552140 kb
Host smart-b8af90da-6eb5-4559-9763-6aa7d42cf37e
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876959601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all
_with_rand_reset.3876959601
Directory /workspace/98.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.974364123
Short name T1112
Test name
Test status
Simulation time 415356449 ps
CPU time 89.76 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:15:12 PM PST 24
Peak memory 555368 kb
Host smart-b310557f-d281-45c2-844b-6d8080163dfa
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974364123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all
_with_reset_error.974364123
Directory /workspace/98.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1099133320
Short name T107
Test name
Test status
Simulation time 556141404 ps
CPU time 24.63 seconds
Started Jan 03 02:13:32 PM PST 24
Finished Jan 03 02:14:20 PM PST 24
Peak memory 554200 kb
Host smart-7a2cf950-6baf-49ec-89ce-575d440be2af
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099133320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1099133320
Directory /workspace/98.xbar_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_access_same_device.794938948
Short name T709
Test name
Test status
Simulation time 2891493627 ps
CPU time 113.42 seconds
Started Jan 03 02:13:16 PM PST 24
Finished Jan 03 02:15:36 PM PST 24
Peak memory 555312 kb
Host smart-f0b228fe-7020-43aa-b4ee-a99ee587ed6b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794938948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device.
794938948
Directory /workspace/99.xbar_access_same_device/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.769888584
Short name T1291
Test name
Test status
Simulation time 60097691266 ps
CPU time 977.03 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:29:59 PM PST 24
Peak memory 553200 kb
Host smart-842bd3e9-5017-4f7c-b5cd-b32033ea11a2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769888584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_d
evice_slow_rsp.769888584
Directory /workspace/99.xbar_access_same_device_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.825461004
Short name T1152
Test name
Test status
Simulation time 820928287 ps
CPU time 32.88 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:14:15 PM PST 24
Peak memory 553880 kb
Host smart-f00aff0c-9bb2-4671-bd93-ae94cbf68b14
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825461004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr
.825461004
Directory /workspace/99.xbar_error_and_unmapped_addr/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_error_random.1233204142
Short name T1502
Test name
Test status
Simulation time 271620674 ps
CPU time 21.5 seconds
Started Jan 03 02:13:19 PM PST 24
Finished Jan 03 02:14:07 PM PST 24
Peak memory 552804 kb
Host smart-c3564c48-c82c-4e26-9572-fdeb3c3828e6
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233204142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.1233204142
Directory /workspace/99.xbar_error_random/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random.1270975668
Short name T589
Test name
Test status
Simulation time 382829281 ps
CPU time 16.16 seconds
Started Jan 03 02:13:32 PM PST 24
Finished Jan 03 02:14:13 PM PST 24
Peak memory 553816 kb
Host smart-fd034f12-da4d-44f9-8dae-f8c2fea1cedf
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270975668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.1270975668
Directory /workspace/99.xbar_random/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.1282800774
Short name T946
Test name
Test status
Simulation time 87399004285 ps
CPU time 957.95 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:29:39 PM PST 24
Peak memory 554224 kb
Host smart-894cc815-bc16-49d6-9546-e05428e49c05
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282800774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.1282800774
Directory /workspace/99.xbar_random_large_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.2559578125
Short name T256
Test name
Test status
Simulation time 60647764992 ps
CPU time 1052.62 seconds
Started Jan 03 02:13:33 PM PST 24
Finished Jan 03 02:31:30 PM PST 24
Peak memory 553888 kb
Host smart-3344a6bd-9072-4be9-8457-7445fe80214e
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559578125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.2559578125
Directory /workspace/99.xbar_random_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.1493090242
Short name T73
Test name
Test status
Simulation time 607393390 ps
CPU time 56.48 seconds
Started Jan 03 02:13:16 PM PST 24
Finished Jan 03 02:14:39 PM PST 24
Peak memory 554180 kb
Host smart-64d3eca9-5526-421f-a715-8cb6d635bb80
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493090242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del
ays.1493090242
Directory /workspace/99.xbar_random_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_same_source.3850000297
Short name T1017
Test name
Test status
Simulation time 418371073 ps
CPU time 14.49 seconds
Started Jan 03 02:13:30 PM PST 24
Finished Jan 03 02:14:09 PM PST 24
Peak memory 553864 kb
Host smart-4d67220a-4844-4975-bdc7-9360c22beb2b
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850000297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.3850000297
Directory /workspace/99.xbar_same_source/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke.1320700326
Short name T611
Test name
Test status
Simulation time 228660039 ps
CPU time 9.34 seconds
Started Jan 03 02:13:28 PM PST 24
Finished Jan 03 02:14:03 PM PST 24
Peak memory 552152 kb
Host smart-f85e4b5f-ee91-448c-a1de-5490a96b5661
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320700326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.1320700326
Directory /workspace/99.xbar_smoke/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.2293888640
Short name T229
Test name
Test status
Simulation time 6663436043 ps
CPU time 69.97 seconds
Started Jan 03 02:13:16 PM PST 24
Finished Jan 03 02:14:52 PM PST 24
Peak memory 551844 kb
Host smart-cc231278-4c4e-4cbd-b0d7-e195376051d2
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_
len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293888640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.2293888640
Directory /workspace/99.xbar_smoke_large_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3743981175
Short name T925
Test name
Test status
Simulation time 6570987606 ps
CPU time 114.96 seconds
Started Jan 03 02:13:19 PM PST 24
Finished Jan 03 02:15:40 PM PST 24
Peak memory 552184 kb
Host smart-da61625e-79db-4969-b95a-40f644d52ba4
User root
Command /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=
2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743981175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.3743981175
Directory /workspace/99.xbar_smoke_slow_rsp/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.3960157896
Short name T1304
Test name
Test status
Simulation time 42337226 ps
CPU time 5.84 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:13:47 PM PST 24
Peak memory 552000 kb
Host smart-6bbcf837-744d-430b-a643-108bf8e0218d
User root
Command /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /
workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960157896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay
s.3960157896
Directory /workspace/99.xbar_smoke_zero_delays/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all.3845310919
Short name T1836
Test name
Test status
Simulation time 4943303163 ps
CPU time 182.66 seconds
Started Jan 03 02:13:14 PM PST 24
Finished Jan 03 02:16:43 PM PST 24
Peak memory 555252 kb
Host smart-56c91481-4d86-43be-a9a3-de9c1bb1e5e1
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845310919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.3845310919
Directory /workspace/99.xbar_stress_all/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.2600689567
Short name T964
Test name
Test status
Simulation time 6836508016 ps
CPU time 220.99 seconds
Started Jan 03 02:13:18 PM PST 24
Finished Jan 03 02:17:26 PM PST 24
Peak memory 556084 kb
Host smart-f2da8f29-eb91-4331-9fa2-5b71522dda64
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600689567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.2600689567
Directory /workspace/99.xbar_stress_all_with_error/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.1090189420
Short name T1485
Test name
Test status
Simulation time 6334151726 ps
CPU time 343.98 seconds
Started Jan 03 02:13:18 PM PST 24
Finished Jan 03 02:19:29 PM PST 24
Peak memory 557180 kb
Host smart-4d64b445-187c-4fac-9fff-afc7169c0fd5
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090189420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all
_with_rand_reset.1090189420
Directory /workspace/99.xbar_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.2050088368
Short name T765
Test name
Test status
Simulation time 180283805 ps
CPU time 34.61 seconds
Started Jan 03 02:13:15 PM PST 24
Finished Jan 03 02:14:17 PM PST 24
Peak memory 555332 kb
Host smart-c7e32f1c-8f1d-4f3d-a024-ac7e337f3f57
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050088368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al
l_with_reset_error.2050088368
Directory /workspace/99.xbar_stress_all_with_reset_error/latest

Test location /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.638728403
Short name T1259
Test name
Test status
Simulation time 235985936 ps
CPU time 27.82 seconds
Started Jan 03 02:13:16 PM PST 24
Finished Jan 03 02:14:11 PM PST 24
Peak memory 553892 kb
Host smart-c87d498f-fd65-46c7-ad06-4a469027905a
User root
Command /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638728403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.638728403
Directory /workspace/99.xbar_unmapped_addr/latest

Test location /workspace/coverage/default/2.chip_jtag_mem_access.412838603
Short name T17
Test name
Test status
Simulation time 13586510672 ps
CPU time 1042.84 seconds
Started Jan 03 02:06:46 PM PST 24
Finished Jan 03 02:24:12 PM PST 24
Peak memory 595844 kb
Host smart-cb0104fe-a73a-442a-a0b3-4b1a82ab1527
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412838603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m
em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.412838603
Directory /workspace/2.chip_jtag_mem_access/latest

Test location /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2346202986
Short name T26
Test name
Test status
Simulation time 5328479822 ps
CPU time 292.87 seconds
Started Jan 03 02:03:17 PM PST 24
Finished Jan 03 02:08:25 PM PST 24
Peak memory 633540 kb
Host smart-2a0fdda9-1fcc-4d9a-8d37-2b511e82a327
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346202986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 1.chip_padctrl_attributes.2346202986
Directory /workspace/1.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3713433403
Short name T27
Test name
Test status
Simulation time 4727933560 ps
CPU time 225.31 seconds
Started Jan 03 02:03:16 PM PST 24
Finished Jan 03 02:07:13 PM PST 24
Peak memory 626116 kb
Host smart-6514e654-4067-497a-984f-a75dea10c472
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713433403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE
ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/
null -cm_name 5.chip_padctrl_attributes.3713433403
Directory /workspace/5.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.679443184
Short name T24
Test name
Test status
Simulation time 4329273264 ps
CPU time 305.08 seconds
Started Jan 03 02:03:36 PM PST 24
Finished Jan 03 02:09:50 PM PST 24
Peak memory 633820 kb
Host smart-33275af5-7abf-4c7e-88cc-425b42711040
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679443184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 8.chip_padctrl_attributes.679443184
Directory /workspace/8.chip_padctrl_attributes/latest

Test location /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.366079153
Short name T15
Test name
Test status
Simulation time 4093116887 ps
CPU time 216.59 seconds
Started Jan 03 02:03:17 PM PST 24
Finished Jan 03 02:07:09 PM PST 24
Peak memory 627448 kb
Host smart-02b3b994-7d94-4cc8-863a-55cd06126c08
User root
Command /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366079153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES
T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n
ull -cm_name 9.chip_padctrl_attributes.366079153
Directory /workspace/9.chip_padctrl_attributes/latest
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