Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	149463	1			T14	8		T15	81		T16	34
values[2]	11820	1			T15	1		T49	45		T68	1
values[3]	4596	1			T49	52		T275	75		T199	14
values[4]	2430	1			T49	20		T275	46		T199	10
values[5]	1447	1			T49	6		T275	37		T199	7
values[6]	943	1			T275	22		T199	3		T244	9
values[7]	729	1			T275	22		T199	4		T244	14
values[8]	578	1			T275	25		T199	7		T244	19
values[9]	457	1			T275	29		T199	12		T244	11
values[10]	319	1			T275	12		T199	6		T244	12
values[11]	317	1			T275	15		T199	4		T244	8
values[12]	309	1			T275	6		T199	8		T244	18
values[13]	300	1			T275	1		T199	12		T244	20
values[14]	263	1			T199	4		T244	14		T277	8
values[15]	278	1			T199	4		T244	16		T277	2
values[16]	292	1			T199	11		T244	17		T277	4
values[17]	286	1			T199	14		T244	19		T277	3
values[18]	309	1			T199	12		T244	9		T277	3
values[19]	253	1			T199	9		T244	9		T277	4
values[20]	224	1			T199	8		T244	7		T277	6
values[21]	235	1			T199	2		T244	11		T277	4
values[22]	247	1			T244	18		T277	2		T93	1
values[23]	270	1			T244	10		T277	4		T93	1
values[24]	260	1			T244	30		T277	4		T93	4
values[25]	234	1			T244	16		T277	1		T93	3
values[26]	243	1			T244	17		T277	1		T93	1
values[27]	228	1			T244	8		T277	2		T93	1
values[28]	219	1			T244	12		T277	1		T93	4
values[29]	264	1			T244	9		T277	1		T93	1
values[30]	226	1			T244	11		T277	2		T93	1
values[31]	266	1			T244	19		T277	3		T93	2
values[32]	287	1			T244	18		T277	3		T93	1
values[33]	299	1			T244	16		T277	10		T93	2
values[34]	272	1			T244	11		T277	8		T93	1
values[35]	248	1			T244	8		T277	12		T93	3
values[36]	232	1			T244	16		T277	5		T93	2
values[37]	180	1			T244	13		T277	3		T93	1
values[38]	217	1			T244	36		T277	2		T93	7
values[39]	232	1			T244	25		T277	4		T93	4
values[40]	229	1			T244	18		T277	1		T93	3
values[41]	223	1			T244	25		T277	1		T93	3
values[42]	219	1			T244	13		T277	2		T93	1
values[43]	216	1			T244	7		T277	1		T93	3
values[44]	193	1			T244	5		T277	1		T93	2
values[45]	201	1			T244	4		T277	2		T93	1
values[46]	193	1			T244	4		T277	1		T93	3
values[47]	239	1			T244	4		T277	2		T93	1
values[48]	206	1			T244	8		T277	4		T93	2
values[49]	230	1			T244	10		T277	8		T93	1
values[50]	202	1			T244	5		T277	12		T93	2
values[51]	207	1			T244	9		T277	2		T93	1
values[52]	163	1			T244	3		T277	1		T93	2
values[53]	183	1			T244	17		T277	4		T93	3
values[54]	188	1			T244	6		T277	2		T93	4
values[55]	195	1			T244	4		T277	3		T93	1
values[56]	179	1			T244	10		T277	1		T93	2
values[57]	165	1			T244	8		T93	4		T114	1
values[58]	160	1			T244	7		T93	3		T114	1
values[59]	194	1			T244	15		T93	9		T114	1
values[60]	165	1			T244	4		T93	5		T114	1
values[61]	179	1			T244	4		T93	3		T114	1
values[62]	125	1			T244	9		T93	4		T114	1
values[63]	97	1			T93	3		T114	1		T278	1
values[64]	117	1			T93	2		T114	1		T278	1
values[65]	102	1			T93	2		T114	1		T278	1
values[66]	76	1			T93	2		T114	1		T278	1
values[67]	90	1			T93	4		T114	1		T278	1
values[68]	88	1			T93	6		T114	1		T278	1
values[69]	104	1			T93	1		T114	1		T278	1
values[70]	92	1			T93	4		T114	1		T278	1
values[71]	79	1			T93	3		T114	1		T278	1
values[72]	77	1			T93	8		T114	1		T278	1
values[73]	68	1			T93	5		T114	1		T278	1
values[74]	54	1			T93	1		T114	1		T278	1
values[75]	54	1			T93	2		T114	1		T278	1
values[76]	44	1			T93	2		T114	1		T278	1
values[77]	38	1			T93	1		T114	1		T278	1
values[78]	42	1			T93	1		T114	1		T278	1
values[79]	34	1			T93	4		T114	1		T278	1
values[80]	45	1			T93	5		T114	1		T278	1
values[81]	80	1			T93	7		T114	1		T278	1
values[82]	49	1			T93	9		T114	2		T278	1
values[83]	75	1			T93	7		T114	2		T278	1
values[84]	75	1			T93	4		T114	4		T278	1
values[85]	64	1			T93	5		T114	2		T278	1
values[86]	65	1			T93	6		T114	1		T278	1
values[87]	46	1			T93	4		T114	2		T278	1
values[88]	67	1			T93	11		T114	2		T278	1
values[89]	78	1			T93	9		T114	2		T278	1
values[90]	60	1			T93	7		T114	3		T278	1
values[91]	82	1			T93	10		T114	1		T278	1
values[92]	57	1			T93	5		T114	1		T278	1
values[93]	60	1			T93	5		T114	1		T278	1
values[94]	71	1			T93	3		T114	2		T278	2
values[95]	68	1			T93	2		T114	4		T278	1
values[96]	62	1			T93	3		T114	3		T278	1
values[97]	75	1			T93	5		T114	2		T278	1
values[98]	75	1			T93	12		T114	3		T278	1
values[99]	67	1			T93	2		T114	6		T278	1
values[100]	88	1			T93	1		T114	2		T278	1
values[101]	79	1			T93	3		T114	3		T278	1
values[102]	66	1			T93	4		T114	1		T278	1
values[103]	67	1			T93	6		T114	2		T278	1
values[104]	66	1			T93	8		T114	1		T278	1
values[105]	66	1			T93	2		T114	1		T278	1
values[106]	55	1			T93	3		T114	1		T278	1
values[107]	62	1			T93	1		T114	4		T278	1
values[108]	70	1			T93	5		T114	10		T278	1
values[109]	82	1			T93	11		T114	4		T278	1
values[110]	53	1			T93	7		T114	2		T278	1
values[111]	62	1			T93	6		T114	1		T278	1
values[112]	57	1			T93	7		T114	2		T278	2
values[113]	63	1			T93	3		T114	2		T278	2
values[114]	73	1			T93	7		T114	1		T278	8
values[115]	61	1			T93	3		T114	1		T278	1
values[116]	63	1			T93	2		T114	3		T278	1
values[117]	73	1			T93	2		T114	7		T278	2
values[118]	61	1			T93	6		T114	2		T278	3
values[119]	58	1			T93	2		T114	2		T278	1
values[120]	55	1			T93	1		T114	2		T278	2
values[121]	48	1			T114	2		T278	1		T279	4
values[122]	51	1			T114	3		T278	1		T279	4
values[123]	49	1			T114	1		T278	2		T279	3
values[124]	55	1			T114	1		T278	1		T279	7
values[125]	84	1			T114	2		T278	1		T279	4
values[126]	100	1			T114	1		T278	3		T279	3
values[127]	778	1			T114	35		T278	36		T279	57
values[128]	6602	1			T114	351		T278	283		T279	471

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	163191	1			T14	6		T15	98		T16	35
values[2]	4214	1			T17	2		T56	2		T61	1
values[3]	1684	1			T77	1		T87	6		T280	31
values[4]	1156	1			T280	19		T281	1		T157	1
values[5]	905	1			T280	23		T281	1		T282	1
values[6]	790	1			T280	35		T281	1		T282	2
values[7]	704	1			T280	60		T281	1		T282	1
values[8]	657	1			T280	64		T281	1		T282	1
values[9]	573	1			T280	37		T281	1		T282	2
values[10]	523	1			T280	32		T281	1		T282	1
values[11]	519	1			T280	26		T281	1		T282	2
values[12]	451	1			T280	16		T281	1		T282	4
values[13]	450	1			T280	20		T281	1		T282	5
values[14]	404	1			T280	15		T281	1		T282	1
values[15]	408	1			T280	14		T281	1		T282	4
values[16]	443	1			T280	8		T281	1		T282	4
values[17]	448	1			T280	5		T281	1		T282	2
values[18]	447	1			T280	1		T281	1		T282	6
values[19]	425	1			T280	1		T281	1		T282	6
values[20]	451	1			T281	1		T282	4		T106	2
values[21]	436	1			T281	1		T282	1		T106	5
values[22]	404	1			T281	1		T282	1		T106	7
values[23]	340	1			T281	1		T282	1		T106	1
values[24]	244	1			T281	1		T282	1		T106	2
values[25]	189	1			T281	1		T282	3		T106	1
values[26]	189	1			T281	1		T282	2		T106	1
values[27]	121	1			T281	1		T282	1		T106	1
values[28]	117	1			T281	1		T282	4		T106	2
values[29]	117	1			T281	1		T282	3		T106	2
values[30]	98	1			T281	1		T282	2		T106	1
values[31]	97	1			T281	1		T282	1		T106	3
values[32]	78	1			T281	1		T282	1		T106	2
values[33]	63	1			T281	2		T282	2		T106	1
values[34]	56	1			T281	1		T282	2		T106	1
values[35]	60	1			T281	1		T282	1		T106	11
values[36]	64	1			T281	1		T282	1		T106	9
values[37]	67	1			T281	1		T282	4		T106	8
values[38]	69	1			T281	1		T282	3		T106	9
values[39]	61	1			T281	1		T282	1		T106	3
values[40]	76	1			T281	1		T282	5		T106	7
values[41]	72	1			T281	1		T282	4		T106	5
values[42]	71	1			T281	1		T282	1		T106	3
values[43]	69	1			T281	1		T282	4		T106	3
values[44]	68	1			T281	1		T282	1		T106	1
values[45]	66	1			T281	1		T282	3		T106	2
values[46]	56	1			T281	1		T282	1		T106	2
values[47]	75	1			T281	1		T282	3		T106	4
values[48]	84	1			T281	1		T282	2		T106	1
values[49]	91	1			T281	1		T282	6		T106	3
values[50]	95	1			T281	1		T282	1		T106	2
values[51]	65	1			T281	1		T282	2		T106	1
values[52]	78	1			T281	1		T282	1		T106	6
values[53]	68	1			T281	1		T282	2		T106	2
values[54]	64	1			T281	1		T282	2		T106	2
values[55]	77	1			T281	1		T282	4		T106	2
values[56]	66	1			T281	1		T282	3		T106	2
values[57]	69	1			T281	1		T282	9		T106	1
values[58]	54	1			T281	1		T282	4		T106	2
values[59]	64	1			T281	1		T282	9		T106	6
values[60]	61	1			T281	1		T282	3		T106	9
values[61]	62	1			T281	1		T282	1		T106	3
values[62]	61	1			T281	1		T282	4		T106	7
values[63]	62	1			T281	1		T282	4		T106	5
values[64]	60	1			T281	1		T282	5		T106	4
values[65]	65	1			T281	1		T282	2		T106	3
values[66]	52	1			T281	1		T282	1		T106	1
values[67]	51	1			T281	1		T282	2		T106	1
values[68]	64	1			T281	1		T282	2		T106	5
values[69]	58	1			T281	1		T282	4		T106	3
values[70]	57	1			T281	1		T282	2		T106	5
values[71]	68	1			T281	1		T282	3		T106	4
values[72]	64	1			T281	1		T282	2		T106	7
values[73]	69	1			T281	1		T282	3		T106	10
values[74]	65	1			T281	1		T282	4		T106	6
values[75]	62	1			T281	1		T282	2		T106	4
values[76]	62	1			T281	1		T282	4		T106	4
values[77]	52	1			T281	1		T282	2		T106	1
values[78]	72	1			T281	1		T282	2		T106	2
values[79]	66	1			T281	1		T282	1		T106	2
values[80]	79	1			T281	1		T282	3		T106	3
values[81]	58	1			T281	1		T282	5		T106	1
values[82]	65	1			T281	2		T282	2		T106	6
values[83]	87	1			T281	5		T282	6		T106	6
values[84]	86	1			T281	10		T282	2		T106	3
values[85]	73	1			T281	7		T282	2		T106	2
values[86]	77	1			T281	2		T282	2		T106	2
values[87]	69	1			T281	9		T282	1		T106	1
values[88]	79	1			T281	7		T282	8		T106	3
values[89]	74	1			T281	9		T282	4		T106	3
values[90]	77	1			T281	13		T282	5		T106	4
values[91]	80	1			T281	5		T282	2		T106	1
values[92]	78	1			T281	2		T282	1		T106	3
values[93]	89	1			T281	1		T282	2		T106	2
values[94]	93	1			T281	2		T282	6		T106	4
values[95]	77	1			T281	2		T282	4		T106	7
values[96]	76	1			T281	2		T282	2		T106	4
values[97]	75	1			T281	2		T282	2		T106	4
values[98]	82	1			T281	2		T282	2		T106	2
values[99]	82	1			T281	1		T282	4		T106	2
values[100]	86	1			T281	3		T282	2		T106	3
values[101]	90	1			T281	2		T282	3		T106	4
values[102]	92	1			T281	2		T282	6		T106	2
values[103]	84	1			T281	4		T282	6		T106	1
values[104]	67	1			T281	3		T282	3		T106	4
values[105]	80	1			T281	2		T282	7		T106	1
values[106]	81	1			T281	2		T282	8		T106	2
values[107]	87	1			T281	4		T282	4		T106	7
values[108]	92	1			T281	1		T282	7		T106	9
values[109]	91	1			T281	1		T282	7		T106	2
values[110]	99	1			T281	1		T282	11		T106	1
values[111]	92	1			T281	3		T282	1		T106	2
values[112]	99	1			T281	2		T282	6		T106	1
values[113]	103	1			T281	2		T282	4		T106	2
values[114]	103	1			T281	2		T282	2		T106	2
values[115]	109	1			T281	2		T282	4		T106	2
values[116]	96	1			T281	2		T282	1		T106	2
values[117]	106	1			T281	2		T282	3		T106	3
values[118]	107	1			T281	3		T282	4		T106	5
values[119]	97	1			T281	3		T282	2		T106	4
values[120]	77	1			T281	4		T282	2		T106	1
values[121]	83	1			T281	3		T282	5		T106	2
values[122]	111	1			T281	1		T282	2		T106	7
values[123]	140	1			T281	2		T282	5		T106	5
values[124]	240	1			T281	1		T282	9		T106	11
values[125]	471	1			T281	1		T282	25		T106	40
values[126]	842	1			T281	26		T282	39		T106	71
values[127]	2429	1			T281	109		T282	22		T106	30
values[128]	4133	1			T281	158		T282	2		T283	200

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145280	1			T14	4		T15	90		T16	36
values[2]	10143	1			T15	1		T16	1		T56	2
values[3]	3805	1			T74	1		T198	22		T75	1
values[4]	2415	1			T198	6		T75	1		T84	5
values[5]	1576	1			T198	1		T75	1		T84	9
values[6]	1016	1			T75	1		T84	8		T87	6
values[7]	713	1			T75	1		T84	8		T87	2
values[8]	585	1			T75	1		T84	8		T87	2
values[9]	531	1			T75	1		T84	4		T87	2
values[10]	523	1			T75	1		T84	7		T87	1
values[11]	389	1			T75	1		T84	5		T87	7
values[12]	461	1			T75	1		T84	22		T87	8
values[13]	388	1			T75	1		T84	9		T87	5
values[14]	384	1			T75	1		T84	7		T87	5
values[15]	320	1			T75	1		T84	4		T87	2
values[16]	326	1			T75	1		T84	4		T87	2
values[17]	330	1			T75	1		T84	6		T87	2
values[18]	293	1			T75	1		T84	8		T87	5
values[19]	338	1			T75	1		T84	12		T87	6
values[20]	343	1			T75	1		T84	13		T87	3
values[21]	280	1			T75	1		T84	4		T87	5
values[22]	282	1			T75	1		T84	3		T87	4
values[23]	282	1			T75	1		T84	3		T87	3
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