Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142196	1			T14	3		T15	82		T16	28
values[2]	8817	1			T15	1		T55	2		T61	1
values[3]	3524	1			T74	1		T81	3		T84	11
values[4]	2133	1			T84	4		T83	8		T277	2
values[5]	1381	1			T84	3		T83	10		T277	2
values[6]	1094	1			T84	19		T83	9		T277	2
values[7]	864	1			T84	11		T83	9		T277	5
values[8]	649	1			T84	3		T83	4		T277	2
values[9]	542	1			T84	3		T83	3		T277	1
values[10]	494	1			T84	12		T83	9		T277	1
values[11]	400	1			T84	10		T83	22		T277	1
values[12]	372	1			T84	6		T83	6		T277	4
values[13]	392	1			T84	5		T83	4		T277	2
values[14]	404	1			T84	5		T83	26		T277	2
values[15]	330	1			T84	9		T83	4		T277	2
values[16]	330	1			T84	3		T83	5		T277	1
values[17]	315	1			T84	7		T83	7		T277	3
values[18]	332	1			T84	5		T83	8		T277	1
values[19]	317	1			T84	3		T83	6		T277	2
values[20]	298	1			T84	7		T83	3		T277	2
values[21]	366	1			T84	24		T83	5		T277	2
values[22]	366	1			T84	5		T83	9		T277	1
values[23]	380	1			T84	4		T83	6		T277	2
values[24]	291	1			T84	2		T83	9		T277	1
values[25]	336	1			T84	3		T83	6		T277	2
values[26]	293	1			T84	7		T83	6		T277	7
values[27]	350	1			T84	5		T83	10		T277	4
values[28]	328	1			T84	20		T83	3		T277	4
values[29]	286	1			T84	7		T83	3		T277	1
values[30]	274	1			T84	3		T83	7		T277	2
values[31]	305	1			T84	5		T83	3		T277	3
values[32]	263	1			T84	3		T83	16		T277	3
values[33]	304	1			T84	5		T83	15		T277	2
values[34]	279	1			T84	11		T83	10		T277	2
values[35]	268	1			T84	4		T83	6		T277	2
values[36]	315	1			T84	7		T83	9		T277	3
values[37]	305	1			T84	13		T83	23		T277	2
values[38]	273	1			T84	5		T83	19		T277	1
values[39]	232	1			T84	7		T83	5		T277	1
values[40]	240	1			T84	7		T83	3		T277	1
values[41]	231	1			T84	5		T83	2		T277	2
values[42]	260	1			T84	7		T83	2		T277	1
values[43]	288	1			T84	3		T277	2		T285	5
values[44]	280	1			T84	4		T277	3		T285	6
values[45]	276	1			T84	4		T277	3		T285	6
values[46]	256	1			T84	8		T277	1		T285	6
values[47]	288	1			T84	5		T277	2		T285	4
values[48]	218	1			T84	10		T277	2		T285	1
values[49]	205	1			T84	7		T277	1		T285	2
values[50]	260	1			T84	26		T277	1		T285	2
values[51]	232	1			T84	5		T277	2		T285	1
values[52]	217	1			T84	6		T277	1		T285	2
values[53]	219	1			T84	5		T277	1		T285	3
values[54]	213	1			T84	4		T277	5		T285	1
values[55]	269	1			T84	7		T277	7		T285	2
values[56]	251	1			T84	15		T277	11		T285	4
values[57]	227	1			T84	3		T277	5		T285	1
values[58]	271	1			T84	2		T277	3		T285	2
values[59]	221	1			T84	19		T277	2		T285	5
values[60]	238	1			T84	16		T277	2		T285	1
values[61]	201	1			T84	8		T277	2		T285	1
values[62]	212	1			T84	3		T277	1		T285	2
values[63]	157	1			T84	2		T277	1		T285	2
values[64]	158	1			T84	5		T277	6		T285	1
values[65]	130	1			T84	9		T277	5		T285	1
values[66]	152	1			T277	4		T285	2		T324	2
values[67]	145	1			T277	11		T285	2		T324	2
values[68]	171	1			T277	27		T285	1		T324	4
values[69]	178	1			T277	12		T285	3		T324	2
values[70]	192	1			T277	7		T285	3		T324	2
values[71]	154	1			T277	5		T285	7		T324	2
values[72]	138	1			T277	12		T285	18		T324	2
values[73]	115	1			T277	5		T285	15		T324	1
values[74]	128	1			T277	6		T285	15		T324	4
values[75]	116	1			T277	2		T285	18		T324	1
values[76]	104	1			T277	9		T285	7		T324	6
values[77]	95	1			T277	18		T324	5		T320	1
values[78]	78	1			T277	7		T324	4		T320	1
values[79]	91	1			T277	4		T324	5		T320	1
values[80]	86	1			T277	9		T324	2		T320	1
values[81]	76	1			T277	6		T324	4		T320	1
values[82]	97	1			T277	12		T324	10		T320	1
values[83]	87	1			T277	7		T324	4		T320	1
values[84]	90	1			T277	13		T324	3		T320	1
values[85]	109	1			T277	6		T324	5		T320	1
values[86]	95	1			T277	10		T324	5		T320	1
values[87]	86	1			T277	5		T324	3		T320	4
values[88]	82	1			T277	2		T324	5		T320	1
values[89]	97	1			T277	2		T324	5		T320	6
values[90]	94	1			T277	7		T324	5		T320	2
values[91]	74	1			T277	4		T324	2		T320	4
values[92]	66	1			T277	3		T324	2		T320	4
values[93]	77	1			T277	3		T324	6		T320	2
values[94]	61	1			T277	2		T324	4		T320	1
values[95]	60	1			T277	2		T324	5		T320	7
values[96]	69	1			T277	7		T324	6		T320	1
values[97]	73	1			T277	6		T324	4		T320	2
values[98]	68	1			T277	2		T324	2		T320	1
values[99]	78	1			T277	2		T324	3		T320	3
values[100]	76	1			T277	9		T324	3		T320	3
values[101]	84	1			T277	4		T324	5		T320	1
values[102]	88	1			T277	4		T324	3		T320	1
values[103]	96	1			T277	11		T324	3		T320	6
values[104]	98	1			T277	1		T324	9		T320	2
values[105]	75	1			T277	4		T324	8		T320	9
values[106]	65	1			T277	2		T324	8		T320	3
values[107]	72	1			T277	10		T324	4		T320	2
values[108]	82	1			T277	7		T324	3		T320	1
values[109]	86	1			T277	11		T324	2		T320	2
values[110]	68	1			T277	7		T324	4		T320	3
values[111]	64	1			T277	2		T324	2		T320	1
values[112]	59	1			T277	3		T324	2		T320	1
values[113]	69	1			T277	4		T324	5		T320	1
values[114]	58	1			T277	2		T324	7		T320	1
values[115]	52	1			T277	3		T324	7		T320	1
values[116]	68	1			T277	1		T324	9		T320	3
values[117]	53	1			T277	6		T324	4		T320	2
values[118]	74	1			T277	8		T324	6		T320	2
values[119]	57	1			T277	3		T324	5		T320	1
values[120]	52	1			T277	1		T324	2		T320	4
values[121]	64	1			T277	2		T324	3		T320	1
values[122]	70	1			T277	6		T324	3		T320	2
values[123]	56	1			T277	4		T324	1		T320	2
values[124]	56	1			T277	2		T324	1		T320	4
values[125]	97	1			T277	6		T324	12		T320	1
values[126]	188	1			T324	30		T320	1		T225	1
values[127]	734	1			T324	57		T320	28		T225	28
values[128]	3731	1			T324	34		T320	231		T225	274