Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	491	1			T49	2		T275	1		T276	1
all_values[1]	478	1			T49	1		T72	2		T198	3
all_values[2]	519	1			T49	1		T199	1		T198	2
all_values[3]	478	1			T49	4		T275	1		T72	3
all_values[4]	448	1			T49	1		T72	2		T198	1
all_values[5]	466	1			T49	3		T72	4		T199	2
all_values[6]	445	1			T49	3		T72	2		T199	1
all_values[7]	475	1			T49	2		T275	2		T72	4
all_values[8]	493	1			T49	2		T72	3		T198	1
all_values[9]	479	1			T72	2		T198	1		T84	2
all_values[10]	487	1			T49	1		T72	3		T83	3
all_values[11]	456	1			T49	3		T72	2		T199	1
all_values[12]	528	1			T72	2		T198	1		T83	3
all_values[13]	471	1			T49	1		T363	1		T291	1
all_values[14]	467	1			T49	1		T72	1		T199	2
all_values[15]	462	1			T49	3		T72	2		T199	1
all_values[16]	510	1			T49	4		T275	1		T72	2
all_values[17]	502	1			T49	1		T72	1		T198	2
all_values[18]	469	1			T49	2		T72	2		T198	2
all_values[19]	492	1			T49	4		T72	1		T199	1
all_values[20]	428	1			T49	4		T75	1		T84	1
all_values[21]	495	1			T49	1		T72	5		T276	1
all_values[22]	475	1			T49	2		T275	1		T72	5
all_values[23]	518	1			T72	2		T363	1		T291	1
all_values[24]	462	1			T49	2		T199	1		T198	1
all_values[25]	523	1			T49	4		T275	1		T72	4
all_values[26]	502	1			T49	1		T72	2		T199	1
all_values[27]	411	1			T49	3		T72	1		T276	1
all_values[28]	492	1			T49	1		T72	2		T75	2
all_values[29]	484	1			T49	1		T72	3		T198	1
all_values[30]	477	1			T49	1		T275	1		T72	1
all_values[31]	487	1			T49	1		T72	3		T363	1
all_values[32]	440	1			T49	2		T72	1		T199	2
all_values[33]	478	1			T49	5		T72	4		T198	1
all_values[34]	479	1			T49	1		T72	1		T199	2
all_values[35]	485	1			T49	3		T72	1		T83	3
all_values[36]	482	1			T49	1		T275	1		T72	5
all_values[37]	451	1			T72	1		T276	1		T291	1
all_values[38]	471	1			T49	3		T72	1		T199	1
all_values[39]	494	1			T49	2		T198	2		T205	1
all_values[40]	458	1			T49	2		T72	1		T199	1
all_values[41]	469	1			T49	2		T72	1		T198	2
all_values[42]	499	1			T49	1		T72	1		T199	1
all_values[43]	444	1			T49	5		T72	2		T198	1
all_values[44]	456	1			T49	1		T72	2		T199	2
all_values[45]	445	1			T49	4		T72	1		T198	1
all_values[46]	472	1			T49	3		T275	1		T72	3
all_values[47]	461	1			T49	2		T72	3		T75	1
all_values[48]	491	1			T49	2		T275	1		T72	1
all_values[49]	455	1			T49	3		T72	2		T199	1