Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3619	1			T49	8		T61	5		T70	1
all_values[1]	3626	1			T49	11		T61	6		T69	2
all_values[2]	3572	1			T49	9		T61	1		T69	3
all_values[3]	3592	1			T49	13		T61	4		T69	1
all_values[4]	3676	1			T49	7		T61	5		T69	2
all_values[5]	3728	1			T49	11		T61	1		T70	1
all_values[6]	3609	1			T49	12		T61	3		T69	2
all_values[7]	3626	1			T49	11		T69	3		T70	1
all_values[8]	3638	1			T49	7		T61	3		T69	1
all_values[9]	3577	1			T49	8		T61	5		T69	3
all_values[10]	3546	1			T49	10		T61	2		T69	3
all_values[11]	3747	1			T49	14		T61	4		T69	1
all_values[12]	3543	1			T49	11		T61	4		T69	3
all_values[13]	3677	1			T49	9		T61	5		T69	3
all_values[14]	3690	1			T49	12		T61	4		T69	2
all_values[15]	3575	1			T49	15		T61	2		T69	2
all_values[16]	3724	1			T49	9		T61	4		T69	3
all_values[17]	3661	1			T49	7		T69	1		T70	2
all_values[18]	3687	1			T49	12		T61	2		T69	1
all_values[19]	3697	1			T49	11		T61	4		T69	4
all_values[20]	3572	1			T49	14		T61	5		T69	2
all_values[21]	3753	1			T49	7		T61	4		T69	1
all_values[22]	3636	1			T49	14		T61	1		T69	1
all_values[23]	3582	1			T49	11		T69	4		T72	22
all_values[24]	3707	1			T49	12		T61	2		T69	1
all_values[25]	3645	1			T49	8		T61	2		T69	4
all_values[26]	3643	1			T49	10		T61	3		T69	5
all_values[27]	3564	1			T49	7		T61	6		T70	1
all_values[28]	3633	1			T49	6		T61	4		T70	1
all_values[29]	3605	1			T49	10		T61	2		T69	6
all_values[30]	3561	1			T49	6		T61	3		T69	1
all_values[31]	3651	1			T49	15		T61	2		T70	1
all_values[32]	3633	1			T49	9		T61	2		T69	3
all_values[33]	3668	1			T49	14		T61	2		T69	4
all_values[34]	3644	1			T49	7		T61	5		T69	2
all_values[35]	3709	1			T49	9		T61	1		T69	2
all_values[36]	3629	1			T49	8		T61	2		T69	4
all_values[37]	3590	1			T49	7		T61	2		T69	2
all_values[38]	3604	1			T49	7		T61	3		T69	5
all_values[39]	3612	1			T49	17		T61	3		T69	2
all_values[40]	3644	1			T49	15		T61	1		T72	26
all_values[41]	3723	1			T49	9		T61	5		T69	4
all_values[42]	3689	1			T49	6		T61	2		T69	2
all_values[43]	3705	1			T49	10		T61	7		T69	2
all_values[44]	3618	1			T49	11		T61	4		T70	2
all_values[45]	3642	1			T49	7		T61	1		T69	1
all_values[46]	3649	1			T49	8		T61	9		T70	1
all_values[47]	3667	1			T49	11		T61	2		T69	3
all_values[48]	3643	1			T49	8		T61	1		T69	3
all_values[49]	3572	1			T49	17		T61	2		T69	4
all_values[50]	3545	1			T49	10		T61	1		T69	2
all_values[51]	3564	1			T49	8		T61	4		T69	3
all_values[52]	3659	1			T49	9		T61	5		T69	5
all_values[53]	3547	1			T49	12		T61	6		T69	1
all_values[54]	3595	1			T49	8		T61	3		T69	2
all_values[55]	3664	1			T49	10		T61	4		T69	2
all_values[56]	3548	1			T49	7		T69	2		T72	16
all_values[57]	3676	1			T49	18		T61	3		T69	3
all_values[58]	3529	1			T49	11		T61	1		T69	1
all_values[59]	3666	1			T49	15		T61	6		T69	4
all_values[60]	3703	1			T49	11		T61	6		T69	4
all_values[61]	3709	1			T49	15		T61	3		T69	1
all_values[62]	3698	1			T49	10		T61	1		T70	3
all_values[63]	3658	1			T49	7		T61	2		T69	1