Go
back
LINE 19914
EXPRESSION (dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T112,T122,T171 |
LINE 20067
EXPRESSION (dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T112,T185,T103 |
LINE 20220
EXPRESSION (dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T114,T187,T127 |
LINE 20373
EXPRESSION (dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T83,T104,T188 |
LINE 20526
EXPRESSION (dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T55,T118,T189 |
LINE 20679
EXPRESSION (dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T190,T1,T2 |
LINE 20832
EXPRESSION (dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs)
--------1-------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T78,T191,T128 |
LINE 20985
EXPRESSION (dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T192,T104,T193 |
LINE 21138
EXPRESSION (dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T194,T107,T195 |
LINE 21291
EXPRESSION (dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T103,T104,T149 |
LINE 21444
EXPRESSION (dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T117,T123,T196 |
LINE 21597
EXPRESSION (dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T77,T117,T197 |
LINE 21750
EXPRESSION (dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs)
---------1-------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T123,T144,T185 |
LINE 24538
EXPRESSION (mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T13,T19 |
1 | 1 | Covered | T12,T32,T107 |
LINE 24570
EXPRESSION (mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T20,T57 |
1 | 1 | Covered | T11,T12,T13 |
LINE 24602
EXPRESSION (mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T32,T20 |
1 | 1 | Covered | T11,T12,T19 |
LINE 24634
EXPRESSION (mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T31 |
1 | 1 | Covered | T11,T12,T13 |
LINE 24666
EXPRESSION (mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T32,T20 |
1 | 1 | Covered | T11,T13,T19 |
LINE 24698
EXPRESSION (mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T31,T57,T46 |
1 | 1 | Covered | T11,T12,T13 |
LINE 24730
EXPRESSION (mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T38,T57 |
1 | 1 | Covered | T11,T12,T13 |
LINE 24762
EXPRESSION (mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T13,T19 |
1 | 1 | Covered | T12,T32,T31 |
LINE 24794
EXPRESSION (mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T19,T32 |
1 | 1 | Covered | T12,T13,T32 |
LINE 24826
EXPRESSION (mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T38,T35 |
1 | 1 | Covered | T11,T12,T19 |
LINE 24858
EXPRESSION (mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T20,T57 |
1 | 1 | Covered | T11,T12,T13 |
LINE 24890
EXPRESSION (mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T19,T32 |
1 | 1 | Covered | T11,T69,T12 |
LINE 24922
EXPRESSION (mio_pad_sleep_en_12_we & mio_pad_sleep_regwen_12_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T20 |
1 | 1 | Covered | T11,T12,T13 |
LINE 24954
EXPRESSION (mio_pad_sleep_en_13_we & mio_pad_sleep_regwen_13_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T32,T31 |
1 | 1 | Covered | T11,T12,T19 |
LINE 24986
EXPRESSION (mio_pad_sleep_en_14_we & mio_pad_sleep_regwen_14_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T20,T57,T35 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25018
EXPRESSION (mio_pad_sleep_en_15_we & mio_pad_sleep_regwen_15_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T31,T38,T57 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25050
EXPRESSION (mio_pad_sleep_en_16_we & mio_pad_sleep_regwen_16_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T31,T20 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25082
EXPRESSION (mio_pad_sleep_en_17_we & mio_pad_sleep_regwen_17_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T31,T20 |
1 | 1 | Covered | T11,T12,T19 |
LINE 25114
EXPRESSION (mio_pad_sleep_en_18_we & mio_pad_sleep_regwen_18_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T20 |
1 | 1 | Covered | T11,T12,T89 |
LINE 25146
EXPRESSION (mio_pad_sleep_en_19_we & mio_pad_sleep_regwen_19_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T38 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25178
EXPRESSION (mio_pad_sleep_en_20_we & mio_pad_sleep_regwen_20_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T32,T20 |
1 | 1 | Covered | T12,T13,T19 |
LINE 25210
EXPRESSION (mio_pad_sleep_en_21_we & mio_pad_sleep_regwen_21_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T12,T13 |
1 | 1 | Covered | T19,T72,T182 |
LINE 25242
EXPRESSION (mio_pad_sleep_en_22_we & mio_pad_sleep_regwen_22_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T20 |
1 | 1 | Covered | T11,T61,T12 |
LINE 25274
EXPRESSION (mio_pad_sleep_en_23_we & mio_pad_sleep_regwen_23_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T13,T32 |
1 | 1 | Covered | T11,T61,T19 |
LINE 25306
EXPRESSION (mio_pad_sleep_en_24_we & mio_pad_sleep_regwen_24_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T35 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25338
EXPRESSION (mio_pad_sleep_en_25_we & mio_pad_sleep_regwen_25_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T12,T32 |
1 | 1 | Covered | T13,T19,T72 |
LINE 25370
EXPRESSION (mio_pad_sleep_en_26_we & mio_pad_sleep_regwen_26_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T32 |
1 | 1 | Covered | T11,T13,T32 |
LINE 25402
EXPRESSION (mio_pad_sleep_en_27_we & mio_pad_sleep_regwen_27_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T38,T57,T35 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25434
EXPRESSION (mio_pad_sleep_en_28_we & mio_pad_sleep_regwen_28_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T32,T31 |
1 | 1 | Covered | T11,T12,T19 |
LINE 25466
EXPRESSION (mio_pad_sleep_en_29_we & mio_pad_sleep_regwen_29_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T38,T57,T46 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25498
EXPRESSION (mio_pad_sleep_en_30_we & mio_pad_sleep_regwen_30_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T31,T35 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25530
EXPRESSION (mio_pad_sleep_en_31_we & mio_pad_sleep_regwen_31_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T19,T32 |
1 | 1 | Covered | T12,T13,T85 |
LINE 25562
EXPRESSION (mio_pad_sleep_en_32_we & mio_pad_sleep_regwen_32_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T31,T20 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25594
EXPRESSION (mio_pad_sleep_en_33_we & mio_pad_sleep_regwen_33_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T31,T20 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25626
EXPRESSION (mio_pad_sleep_en_34_we & mio_pad_sleep_regwen_34_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T12,T32 |
1 | 1 | Covered | T13,T19,T32 |
LINE 25658
EXPRESSION (mio_pad_sleep_en_35_we & mio_pad_sleep_regwen_35_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T32,T38 |
1 | 1 | Covered | T11,T12,T19 |
LINE 25690
EXPRESSION (mio_pad_sleep_en_36_we & mio_pad_sleep_regwen_36_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T19,T32 |
1 | 1 | Covered | T12,T13,T31 |
LINE 25722
EXPRESSION (mio_pad_sleep_en_37_we & mio_pad_sleep_regwen_37_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T12,T20 |
1 | 1 | Covered | T13,T19,T32 |
LINE 25754
EXPRESSION (mio_pad_sleep_en_38_we & mio_pad_sleep_regwen_38_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T31,T38 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25786
EXPRESSION (mio_pad_sleep_en_39_we & mio_pad_sleep_regwen_39_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T32,T31 |
1 | 1 | Covered | T12,T13,T19 |
LINE 25818
EXPRESSION (mio_pad_sleep_en_40_we & mio_pad_sleep_regwen_40_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T19,T32 |
1 | 1 | Covered | T11,T12,T32 |
LINE 25850
EXPRESSION (mio_pad_sleep_en_41_we & mio_pad_sleep_regwen_41_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T31,T20 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25882
EXPRESSION (mio_pad_sleep_en_42_we & mio_pad_sleep_regwen_42_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T20,T38 |
1 | 1 | Covered | T11,T13,T19 |
LINE 25914
EXPRESSION (mio_pad_sleep_en_43_we & mio_pad_sleep_regwen_43_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T35,T46 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25946
EXPRESSION (mio_pad_sleep_en_44_we & mio_pad_sleep_regwen_44_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T20 |
1 | 1 | Covered | T11,T12,T13 |
LINE 25978
EXPRESSION (mio_pad_sleep_en_45_we & mio_pad_sleep_regwen_45_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T20 |
1 | 1 | Covered | T11,T12,T13 |
LINE 26010
EXPRESSION (mio_pad_sleep_en_46_we & mio_pad_sleep_regwen_46_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T32,T20 |
1 | 1 | Covered | T12,T13,T19 |
LINE 26042
EXPRESSION (mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T13,T19 |
1 | 1 | Covered | T12,T32,T31 |
LINE 26074
EXPRESSION (mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T57,T46,T48 |
1 | 1 | Covered | T11,T12,T13 |
LINE 26106
EXPRESSION (mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T32,T31 |
1 | 1 | Covered | T11,T12,T19 |
LINE 26138
EXPRESSION (mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T31,T20 |
1 | 1 | Covered | T11,T12,T13 |
LINE 26170
EXPRESSION (mio_pad_sleep_mode_4_we & mio_pad_sleep_regwen_4_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T32,T31 |
1 | 1 | Covered | T11,T61,T13 |
LINE 26202
EXPRESSION (mio_pad_sleep_mode_5_we & mio_pad_sleep_regwen_5_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T31,T57 |
1 | 1 | Covered | T11,T12,T13 |
LINE 26234
EXPRESSION (mio_pad_sleep_mode_6_we & mio_pad_sleep_regwen_6_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T57,T46 |
1 | 1 | Covered | T11,T56,T13 |
LINE 26266
EXPRESSION (mio_pad_sleep_mode_7_we & mio_pad_sleep_regwen_7_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T19,T32 |
1 | 1 | Covered | T12,T13,T182 |
LINE 26298
EXPRESSION (mio_pad_sleep_mode_8_we & mio_pad_sleep_regwen_8_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T12,T19 |
1 | 1 | Covered | T13,T32,T20 |
LINE 26330
EXPRESSION (mio_pad_sleep_mode_9_we & mio_pad_sleep_regwen_9_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T31,T35 |
1 | 1 | Covered | T11,T13,T19 |
LINE 26362
EXPRESSION (mio_pad_sleep_mode_10_we & mio_pad_sleep_regwen_10_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T13,T32 |
1 | 1 | Covered | T12,T19,T32 |
LINE 26394
EXPRESSION (mio_pad_sleep_mode_11_we & mio_pad_sleep_regwen_11_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T19,T32 |
1 | 1 | Covered | T11,T12,T32 |
LINE 26426
EXPRESSION (mio_pad_sleep_mode_12_we & mio_pad_sleep_regwen_12_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T20 |
1 | 1 | Covered | T11,T12,T13 |
LINE 26458
EXPRESSION (mio_pad_sleep_mode_13_we & mio_pad_sleep_regwen_13_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T32,T31 |
1 | 1 | Covered | T11,T12,T19 |
LINE 26490
EXPRESSION (mio_pad_sleep_mode_14_we & mio_pad_sleep_regwen_14_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T31,T38 |
1 | 1 | Covered | T11,T12,T13 |
LINE 26522
EXPRESSION (mio_pad_sleep_mode_15_we & mio_pad_sleep_regwen_15_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T13,T19 |
1 | 1 | Covered | T12,T32,T20 |
LINE 26554
EXPRESSION (mio_pad_sleep_mode_16_we & mio_pad_sleep_regwen_16_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T31,T57 |
1 | 1 | Covered | T11,T12,T13 |
LINE 26586
EXPRESSION (mio_pad_sleep_mode_17_we & mio_pad_sleep_regwen_17_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T20,T57 |
1 | 1 | Covered | T11,T12,T19 |
LINE 26618
EXPRESSION (mio_pad_sleep_mode_18_we & mio_pad_sleep_regwen_18_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T32,T31 |
1 | 1 | Covered | T12,T13,T19 |
LINE 26650
EXPRESSION (mio_pad_sleep_mode_19_we & mio_pad_sleep_regwen_19_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T19,T32 |
1 | 1 | Covered | T11,T13,T85 |
LINE 26682
EXPRESSION (mio_pad_sleep_mode_20_we & mio_pad_sleep_regwen_20_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T19,T32 |
1 | 1 | Covered | T12,T13,T32 |
LINE 26714
EXPRESSION (mio_pad_sleep_mode_21_we & mio_pad_sleep_regwen_21_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T12,T13 |
1 | 1 | Covered | T99,T120,T20 |
LINE 26746
EXPRESSION (mio_pad_sleep_mode_22_we & mio_pad_sleep_regwen_22_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T19,T32 |
1 | 1 | Covered | T12,T13,T31 |
LINE 26778
EXPRESSION (mio_pad_sleep_mode_23_we & mio_pad_sleep_regwen_23_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T32,T31 |
1 | 1 | Covered | T11,T12,T19 |
LINE 26810
EXPRESSION (mio_pad_sleep_mode_24_we & mio_pad_sleep_regwen_24_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T19,T32 |
1 | 1 | Covered | T12,T13,T32 |
LINE 26842
EXPRESSION (mio_pad_sleep_mode_25_we & mio_pad_sleep_regwen_25_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T32,T31 |
1 | 1 | Covered | T11,T13,T19 |
LINE 26874
EXPRESSION (mio_pad_sleep_mode_26_we & mio_pad_sleep_regwen_26_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T12,T32 |
1 | 1 | Covered | T13,T19,T83 |
LINE 26906
EXPRESSION (mio_pad_sleep_mode_27_we & mio_pad_sleep_regwen_27_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T38,T35,T46 |
1 | 1 | Covered | T11,T12,T13 |
LINE 26938
EXPRESSION (mio_pad_sleep_mode_28_we & mio_pad_sleep_regwen_28_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T19,T32 |
1 | 1 | Covered | T11,T12,T87 |
LINE 26970
EXPRESSION (mio_pad_sleep_mode_29_we & mio_pad_sleep_regwen_29_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T38,T57 |
1 | 1 | Covered | T11,T12,T13 |
LINE 27002
EXPRESSION (mio_pad_sleep_mode_30_we & mio_pad_sleep_regwen_30_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T32,T35 |
1 | 1 | Covered | T11,T12,T19 |
LINE 27034
EXPRESSION (mio_pad_sleep_mode_31_we & mio_pad_sleep_regwen_31_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T12,T19 |
1 | 1 | Covered | T13,T85,T98 |
LINE 27066
EXPRESSION (mio_pad_sleep_mode_32_we & mio_pad_sleep_regwen_32_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T32,T20 |
1 | 1 | Covered | T11,T13,T19 |
LINE 27098
EXPRESSION (mio_pad_sleep_mode_33_we & mio_pad_sleep_regwen_33_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T20,T46,T48 |
1 | 1 | Covered | T11,T12,T13 |
LINE 27130
EXPRESSION (mio_pad_sleep_mode_34_we & mio_pad_sleep_regwen_34_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T12,T32 |
1 | 1 | Covered | T13,T19,T32 |
LINE 27162
EXPRESSION (mio_pad_sleep_mode_35_we & mio_pad_sleep_regwen_35_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T19,T32 |
1 | 1 | Covered | T11,T12,T32 |
LINE 27194
EXPRESSION (mio_pad_sleep_mode_36_we & mio_pad_sleep_regwen_36_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T13,T19 |
1 | 1 | Covered | T12,T31,T112 |
LINE 27226
EXPRESSION (mio_pad_sleep_mode_37_we & mio_pad_sleep_regwen_37_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T12,T19 |
1 | 1 | Covered | T13,T79,T32 |
LINE 27258
EXPRESSION (mio_pad_sleep_mode_38_we & mio_pad_sleep_regwen_38_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T19,T32 |
1 | 1 | Covered | T11,T12,T32 |
LINE 27290
EXPRESSION (mio_pad_sleep_mode_39_we & mio_pad_sleep_regwen_39_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T32,T31 |
1 | 1 | Covered | T12,T13,T19 |
LINE 27322
EXPRESSION (mio_pad_sleep_mode_40_we & mio_pad_sleep_regwen_40_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T13,T32 |
1 | 1 | Covered | T11,T19,T32 |
LINE 27354
EXPRESSION (mio_pad_sleep_mode_41_we & mio_pad_sleep_regwen_41_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T32,T31 |
1 | 1 | Covered | T11,T13,T19 |
LINE 27386
EXPRESSION (mio_pad_sleep_mode_42_we & mio_pad_sleep_regwen_42_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T12,T19 |
1 | 1 | Covered | T13,T32,T31 |
LINE 27418
EXPRESSION (mio_pad_sleep_mode_43_we & mio_pad_sleep_regwen_43_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T19,T38 |
1 | 1 | Covered | T11,T12,T32 |
LINE 27450
EXPRESSION (mio_pad_sleep_mode_44_we & mio_pad_sleep_regwen_44_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T57,T35 |
1 | 1 | Covered | T11,T12,T13 |
LINE 27482
EXPRESSION (mio_pad_sleep_mode_45_we & mio_pad_sleep_regwen_45_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T20,T57 |
1 | 1 | Covered | T56,T12,T13 |
LINE 27514
EXPRESSION (mio_pad_sleep_mode_46_we & mio_pad_sleep_regwen_46_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T20,T35 |
1 | 1 | Covered | T11,T12,T13 |
LINE 28445
EXPRESSION (dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T32,T20 |
1 | 1 | Covered | T12,T13,T19 |
LINE 28477
EXPRESSION (dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T38 |
1 | 1 | Covered | T11,T12,T13 |
LINE 28509
EXPRESSION (dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T19,T32 |
1 | 1 | Covered | T12,T13,T20 |
LINE 28541
EXPRESSION (dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T31,T38 |
1 | 1 | Covered | T11,T12,T13 |
LINE 28573
EXPRESSION (dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T31,T38 |
1 | 1 | Covered | T11,T12,T13 |
LINE 28605
EXPRESSION (dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T19,T32 |
1 | 1 | Covered | T11,T12,T32 |
LINE 28637
EXPRESSION (dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T57,T46 |
1 | 1 | Covered | T11,T12,T13 |
LINE 28669
EXPRESSION (dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T31 |
1 | 1 | Covered | T11,T69,T12 |
LINE 28701
EXPRESSION (dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T19,T31 |
1 | 1 | Covered | T11,T12,T32 |
LINE 28733
EXPRESSION (dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs)
----------1---------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T31 |
1 | 1 | Covered | T11,T12,T13 |
LINE 28765
EXPRESSION (dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T31 |
1 | 1 | Covered | T11,T12,T13 |
LINE 28797
EXPRESSION (dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T19,T31 |
1 | 1 | Covered | T11,T12,T85 |
LINE 28829
EXPRESSION (dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T20,T57 |
1 | 1 | Covered | T11,T12,T19 |
LINE 28861
EXPRESSION (dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T12,T19 |
1 | 1 | Covered | T13,T32,T31 |
LINE 28893
EXPRESSION (dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T13,T32 |
1 | 1 | Covered | T11,T19,T20 |
LINE 28925
EXPRESSION (dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T38 |
1 | 1 | Covered | T11,T12,T13 |
LINE 28957
EXPRESSION (dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T32,T20 |
1 | 1 | Covered | T12,T13,T19 |
LINE 28989
EXPRESSION (dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T20 |
1 | 1 | Covered | T11,T12,T13 |
LINE 29021
EXPRESSION (dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T32,T31 |
1 | 1 | Covered | T12,T13,T19 |
LINE 29053
EXPRESSION (dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T31,T35 |
1 | 1 | Covered | T11,T12,T13 |
LINE 29085
EXPRESSION (dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T38 |
1 | 1 | Covered | T11,T12,T13 |
LINE 29117
EXPRESSION (dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T38,T57 |
1 | 1 | Covered | T11,T12,T13 |
LINE 29149
EXPRESSION (dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T19,T57 |
1 | 1 | Covered | T11,T12,T32 |
LINE 29181
EXPRESSION (dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T32,T38,T35 |
1 | 1 | Covered | T11,T12,T13 |
LINE 29213
EXPRESSION (dio_pad_sleep_mode_8_we & dio_pad_sleep_regwen_8_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T19,T31 |
1 | 1 | Covered | T12,T13,T71 |
LINE 29245
EXPRESSION (dio_pad_sleep_mode_9_we & dio_pad_sleep_regwen_9_qs)
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T31 |
1 | 1 | Covered | T11,T12,T13 |
LINE 29277
EXPRESSION (dio_pad_sleep_mode_10_we & dio_pad_sleep_regwen_10_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T32,T57 |
1 | 1 | Covered | T12,T13,T19 |
LINE 29309
EXPRESSION (dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T31,T35 |
1 | 1 | Covered | T11,T12,T13 |
LINE 29341
EXPRESSION (dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T13,T32,T31 |
1 | 1 | Covered | T11,T12,T19 |
LINE 29373
EXPRESSION (dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T11,T12,T19 |
1 | 1 | Covered | T13,T32,T31 |
LINE 29405
EXPRESSION (dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T12,T13,T32 |
1 | 1 | Covered | T11,T19,T31 |
LINE 29437
EXPRESSION (dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T19,T32,T38 |
1 | 1 | Covered | T11,T12,T13 |
LINE 29701
EXPRESSION (aon_wkup_detector_en_0_we & aon_wkup_detector_en_0_regwen)
------------1------------ --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T11,T19,T32 |
1 | 1 | Covered | T12,T13,T31 |
LINE 29734
EXPRESSION (aon_wkup_detector_en_1_we & aon_wkup_detector_en_1_regwen)
------------1------------ --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T13,T31,T57 |
1 | 1 | Covered | T11,T12,T19 |
LINE 29767
EXPRESSION (aon_wkup_detector_en_2_we & aon_wkup_detector_en_2_regwen)
------------1------------ --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T19,T38,T35 |
1 | 1 | Covered | T11,T12,T13 |