Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145214	1			T11	29		T12	1687		T13	103
values[2]	12656	1			T11	1		T12	305		T30	1
values[3]	5576	1			T12	13		T30	1		T58	59
values[4]	3141	1			T12	1		T30	1		T58	15
values[5]	1881	1			T30	1		T58	6		T239	5
values[6]	1221	1			T30	1		T58	7		T239	5
values[7]	812	1			T30	1		T58	2		T239	6
values[8]	640	1			T30	1		T239	15		T60	5
values[9]	476	1			T30	1		T239	5		T60	9
values[10]	425	1			T30	1		T239	3		T60	3
values[11]	360	1			T30	1		T239	9		T60	5
values[12]	358	1			T30	1		T239	3		T60	3
values[13]	282	1			T30	1		T239	3		T60	3
values[14]	277	1			T30	1		T239	6		T60	19
values[15]	291	1			T30	1		T239	3		T60	8
values[16]	273	1			T30	1		T239	8		T60	2
values[17]	260	1			T30	1		T239	16		T60	3
values[18]	321	1			T30	1		T239	9		T60	5
values[19]	250	1			T30	1		T239	5		T60	3
values[20]	288	1			T30	1		T239	5		T60	5
values[21]	298	1			T30	1		T239	12		T60	8
values[22]	275	1			T30	1		T239	15		T60	15
values[23]	243	1			T30	1		T239	5		T60	7
values[24]	250	1			T30	1		T239	4		T60	5
values[25]	290	1			T30	1		T239	5		T60	17
values[26]	251	1			T30	1		T239	3		T60	13
values[27]	240	1			T30	1		T239	7		T60	5
values[28]	311	1			T30	1		T239	8		T60	7
values[29]	309	1			T30	1		T239	4		T60	8
values[30]	324	1			T30	1		T239	8		T60	6
values[31]	294	1			T30	1		T239	15		T60	5
values[32]	265	1			T30	1		T239	5		T60	9
values[33]	248	1			T30	1		T239	16		T60	11
values[34]	258	1			T30	1		T239	4		T60	22
values[35]	305	1			T30	1		T239	5		T60	14
values[36]	289	1			T30	1		T239	5		T60	14
values[37]	276	1			T30	1		T239	4		T60	7
values[38]	320	1			T30	1		T239	11		T60	6
values[39]	244	1			T30	1		T239	5		T60	5
values[40]	269	1			T30	1		T239	6		T60	3
values[41]	243	1			T30	1		T239	10		T60	3
values[42]	241	1			T30	1		T239	9		T60	4
values[43]	226	1			T30	1		T239	10		T60	4
values[44]	234	1			T30	1		T239	5		T60	4
values[45]	224	1			T30	1		T239	11		T60	7
values[46]	274	1			T30	1		T239	3		T60	6
values[47]	255	1			T30	1		T239	4		T60	3
values[48]	267	1			T30	1		T60	7		T62	2
values[49]	239	1			T30	1		T60	2		T62	2
values[50]	233	1			T30	1		T62	2		T250	1
values[51]	217	1			T30	1		T62	2		T250	5
values[52]	201	1			T30	1		T62	2		T250	6
values[53]	205	1			T30	1		T62	2		T250	12
values[54]	180	1			T30	1		T62	2		T250	6
values[55]	154	1			T30	1		T62	2		T250	3
values[56]	203	1			T30	1		T62	2		T250	13
values[57]	177	1			T30	1		T62	2		T250	4
values[58]	155	1			T30	1		T62	2		T250	4
values[59]	148	1			T30	1		T62	2		T250	1
values[60]	169	1			T30	1		T62	2		T250	1
values[61]	226	1			T30	1		T62	2		T250	2
values[62]	135	1			T30	1		T62	2		T97	3
values[63]	142	1			T30	1		T62	2		T97	5
values[64]	143	1			T30	1		T62	2		T97	9
values[65]	150	1			T30	1		T62	2		T97	5
values[66]	148	1			T30	1		T62	3		T97	5
values[67]	129	1			T30	1		T62	2		T97	10
values[68]	112	1			T30	1		T62	2		T97	6
values[69]	122	1			T30	1		T62	2		T97	9
values[70]	88	1			T30	1		T62	2		T97	3
values[71]	90	1			T30	1		T62	2		T97	9
values[72]	78	1			T30	1		T62	2		T97	4
values[73]	80	1			T30	1		T62	2		T97	11
values[74]	70	1			T30	1		T62	2		T97	3
values[75]	93	1			T30	1		T62	2		T97	4
values[76]	93	1			T30	1		T62	2		T97	3
values[77]	74	1			T30	1		T62	2		T97	4
values[78]	79	1			T30	1		T62	2		T346	1
values[79]	61	1			T30	1		T62	2		T346	1
values[80]	74	1			T30	1		T62	2		T346	1
values[81]	82	1			T30	1		T62	2		T346	1
values[82]	73	1			T30	1		T62	2		T346	1
values[83]	64	1			T30	1		T62	2		T346	1
values[84]	54	1			T30	1		T62	2		T346	1
values[85]	52	1			T30	1		T62	2		T346	1
values[86]	51	1			T30	1		T62	2		T346	2
values[87]	67	1			T30	1		T62	2		T346	1
values[88]	67	1			T30	1		T62	2		T346	1
values[89]	54	1			T30	1		T62	2		T346	3
values[90]	67	1			T30	1		T62	2		T346	5
values[91]	57	1			T30	1		T62	2		T346	3
values[92]	60	1			T30	1		T62	3		T346	4
values[93]	64	1			T30	1		T62	2		T346	4
values[94]	47	1			T30	1		T62	4		T346	1
values[95]	56	1			T30	1		T62	4		T346	2
values[96]	70	1			T30	1		T62	3		T346	6
values[97]	74	1			T30	1		T62	4		T346	1
values[98]	61	1			T30	1		T62	3		T346	8
values[99]	56	1			T30	1		T62	3		T346	4
values[100]	76	1			T30	1		T62	4		T346	2
values[101]	80	1			T30	1		T62	2		T346	1
values[102]	66	1			T30	1		T62	6		T346	1
values[103]	76	1			T30	1		T62	3		T346	1
values[104]	61	1			T30	1		T62	2		T346	5
values[105]	61	1			T30	1		T62	2		T346	2
values[106]	55	1			T30	2		T62	2		T346	2
values[107]	55	1			T30	1		T62	3		T346	3
values[108]	53	1			T30	1		T62	3		T346	11
values[109]	63	1			T30	1		T62	2		T346	6
values[110]	48	1			T30	1		T62	4		T346	1
values[111]	63	1			T30	1		T62	3		T346	2
values[112]	75	1			T30	1		T62	3		T346	2
values[113]	61	1			T30	1		T62	2		T346	1
values[114]	78	1			T30	7		T62	3		T346	2
values[115]	83	1			T30	3		T62	2		T346	3
values[116]	63	1			T30	2		T62	7		T346	3
values[117]	61	1			T30	1		T62	7		T346	2
values[118]	64	1			T30	4		T62	2		T346	1
values[119]	60	1			T30	3		T62	4		T346	1
values[120]	72	1			T30	2		T62	3		T346	1
values[121]	83	1			T30	2		T62	2		T346	1
values[122]	73	1			T30	2		T62	2		T346	1
values[123]	57	1			T30	3		T62	2		T346	1
values[124]	80	1			T30	2		T62	3		T346	1
values[125]	68	1			T30	1		T62	3		T346	1
values[126]	140	1			T30	3		T62	7		T346	2
values[127]	904	1			T30	40		T62	42		T346	27
values[128]	7145	1			T30	294		T62	637		T346	342