Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	160009	1			T11	41		T12	480		T13	97
values[2]	5161	1			T11	2		T12	1		T30	1
values[3]	2640	1			T30	1		T327	26		T62	1
values[4]	1911	1			T30	1		T327	33		T62	1
values[5]	1619	1			T30	1		T327	26		T62	1
values[6]	1341	1			T30	1		T327	23		T62	1
values[7]	1102	1			T30	1		T327	22		T62	1
values[8]	874	1			T30	1		T327	28		T62	1
values[9]	655	1			T30	1		T327	23		T62	1
values[10]	617	1			T30	1		T327	23		T62	1
values[11]	601	1			T30	1		T327	16		T62	1
values[12]	470	1			T30	1		T327	19		T62	1
values[13]	372	1			T30	1		T327	11		T62	1
values[14]	379	1			T30	1		T327	11		T62	1
values[15]	360	1			T30	1		T327	17		T62	1
values[16]	362	1			T30	1		T327	28		T62	1
values[17]	320	1			T30	1		T327	21		T62	1
values[18]	303	1			T30	1		T327	22		T62	1
values[19]	301	1			T30	1		T327	20		T62	1
values[20]	324	1			T30	1		T327	28		T62	1
values[21]	298	1			T30	1		T327	6		T62	1
values[22]	295	1			T30	1		T327	5		T62	1
values[23]	272	1			T30	1		T327	1		T62	1
values[24]	249	1			T30	1		T62	1		T109	45
values[25]	253	1			T30	1		T62	1		T109	38
values[26]	260	1			T30	1		T62	1		T109	22
values[27]	254	1			T30	1		T62	1		T109	16
values[28]	233	1			T30	1		T62	1		T109	25
values[29]	162	1			T30	1		T62	1		T109	26
values[30]	148	1			T30	1		T62	1		T109	18
values[31]	140	1			T30	1		T62	1		T109	10
values[32]	126	1			T30	1		T62	1		T109	9
values[33]	114	1			T30	1		T62	1		T109	1
values[34]	100	1			T30	1		T62	1		T334	1
values[35]	109	1			T30	1		T62	2		T334	1
values[36]	112	1			T30	1		T62	1		T334	1
values[37]	87	1			T30	1		T62	1		T334	1
values[38]	85	1			T30	1		T62	1		T334	1
values[39]	86	1			T30	1		T62	1		T334	1
values[40]	90	1			T30	1		T62	1		T334	1
values[41]	123	1			T30	1		T62	2		T334	1
values[42]	124	1			T30	1		T62	1		T334	1
values[43]	111	1			T30	1		T62	1		T334	1
values[44]	92	1			T30	1		T62	1		T334	1
values[45]	73	1			T30	1		T62	1		T334	1
values[46]	71	1			T30	1		T62	1		T334	1
values[47]	69	1			T30	1		T62	1		T334	1
values[48]	75	1			T30	1		T62	1		T334	1
values[49]	60	1			T30	1		T62	1		T334	1
values[50]	65	1			T30	1		T62	1		T334	1
values[51]	66	1			T30	1		T62	1		T334	1
values[52]	56	1			T30	1		T62	1		T334	1
values[53]	55	1			T30	1		T62	1		T334	1
values[54]	45	1			T30	1		T62	1		T334	1
values[55]	49	1			T30	1		T62	1		T334	1
values[56]	51	1			T30	1		T62	1		T334	1
values[57]	55	1			T30	1		T62	1		T334	1
values[58]	47	1			T30	1		T62	1		T334	1
values[59]	43	1			T30	1		T62	1		T334	1
values[60]	55	1			T30	1		T62	1		T334	1
values[61]	48	1			T30	1		T62	1		T334	1
values[62]	51	1			T30	1		T62	1		T334	1
values[63]	60	1			T30	1		T62	1		T334	1
values[64]	55	1			T30	1		T62	1		T334	1
values[65]	56	1			T30	1		T62	1		T334	1
values[66]	58	1			T30	1		T62	1		T334	1
values[67]	50	1			T30	1		T62	1		T334	1
values[68]	46	1			T30	1		T62	1		T334	1
values[69]	42	1			T30	1		T62	1		T334	1
values[70]	54	1			T30	1		T62	1		T334	1
values[71]	54	1			T30	1		T62	1		T334	1
values[72]	50	1			T30	1		T62	1		T334	1
values[73]	50	1			T30	1		T62	1		T334	1
values[74]	64	1			T30	1		T62	1		T334	1
values[75]	62	1			T30	1		T62	1		T334	1
values[76]	64	1			T30	1		T62	1		T334	1
values[77]	70	1			T30	1		T62	1		T334	1
values[78]	53	1			T30	1		T62	1		T334	1
values[79]	64	1			T30	1		T62	1		T334	1
values[80]	71	1			T30	1		T62	1		T334	1
values[81]	82	1			T30	1		T62	1		T334	1
values[82]	60	1			T30	1		T62	1		T334	1
values[83]	68	1			T30	1		T62	1		T334	1
values[84]	78	1			T30	1		T62	1		T334	1
values[85]	64	1			T30	1		T62	1		T334	1
values[86]	62	1			T30	1		T62	1		T334	1
values[87]	58	1			T30	1		T62	1		T334	1
values[88]	71	1			T30	1		T62	1		T334	1
values[89]	60	1			T30	2		T62	1		T334	1
values[90]	71	1			T30	1		T62	1		T334	1
values[91]	70	1			T30	2		T62	1		T334	5
values[92]	78	1			T30	2		T62	1		T334	8
values[93]	71	1			T30	4		T62	1		T334	5
values[94]	88	1			T30	2		T62	1		T334	1
values[95]	74	1			T30	2		T62	1		T334	1
values[96]	81	1			T30	1		T62	1		T334	3
values[97]	79	1			T30	1		T62	1		T334	6
values[98]	83	1			T30	2		T62	1		T334	3
values[99]	72	1			T30	3		T62	1		T334	3
values[100]	84	1			T30	5		T62	3		T334	3
values[101]	84	1			T30	5		T62	7		T334	2
values[102]	73	1			T30	1		T62	3		T334	3
values[103]	74	1			T30	1		T62	6		T334	3
values[104]	70	1			T30	1		T62	1		T334	4
values[105]	106	1			T30	3		T62	2		T334	4
values[106]	91	1			T30	3		T62	3		T334	2
values[107]	102	1			T30	3		T62	3		T334	1
values[108]	97	1			T30	2		T62	1		T334	2
values[109]	93	1			T30	2		T62	2		T334	1
values[110]	93	1			T30	2		T62	3		T334	1
values[111]	112	1			T30	1		T62	5		T334	2
values[112]	104	1			T30	3		T62	1		T334	1
values[113]	125	1			T30	6		T62	1		T334	3
values[114]	105	1			T30	1		T62	1		T334	3
values[115]	81	1			T30	2		T62	1		T334	2
values[116]	97	1			T30	2		T62	1		T334	1
values[117]	86	1			T30	2		T62	2		T334	2
values[118]	87	1			T30	1		T62	2		T334	1
values[119]	96	1			T30	1		T62	2		T334	1
values[120]	74	1			T30	1		T62	2		T334	1
values[121]	68	1			T30	4		T62	2		T334	5
values[122]	94	1			T30	2		T62	1		T334	4
values[123]	107	1			T30	1		T62	1		T334	1
values[124]	132	1			T30	2		T62	1		T334	2
values[125]	248	1			T30	2		T62	2		T334	1
values[126]	511	1			T30	12		T62	12		T334	20
values[127]	1618	1			T30	117		T62	115		T334	98
values[128]	3126	1			T30	192		T62	221		T334	239