Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142397	1			T11	48		T12	873		T13	114
values[2]	8646	1			T11	2		T12	83		T30	2
values[3]	2947	1			T12	15		T30	2		T85	37
values[4]	1665	1			T12	5		T30	2		T85	13
values[5]	1037	1			T12	8		T30	2		T85	13
values[6]	769	1			T12	1		T30	2		T85	6
values[7]	606	1			T12	4		T30	2		T85	10
values[8]	468	1			T12	7		T30	2		T85	7
values[9]	407	1			T12	4		T30	2		T85	7
values[10]	386	1			T12	2		T30	2		T85	23
values[11]	293	1			T12	4		T30	2		T91	10
values[12]	302	1			T12	4		T30	2		T91	3
values[13]	342	1			T12	1		T30	2		T91	8
values[14]	278	1			T30	2		T91	5		T236	9
values[15]	258	1			T30	2		T91	16		T236	6
values[16]	290	1			T30	2		T91	4		T236	9
values[17]	243	1			T30	2		T91	3		T236	9
values[18]	308	1			T30	2		T91	4		T236	13
values[19]	254	1			T30	2		T91	7		T236	3
values[20]	270	1			T30	2		T91	7		T236	3
values[21]	267	1			T30	2		T91	17		T236	7
values[22]	259	1			T30	2		T91	7		T236	8
values[23]	281	1			T30	2		T91	3		T236	15
values[24]	238	1			T30	2		T91	5		T236	5
values[25]	275	1			T30	2		T91	3		T236	3
values[26]	301	1			T30	2		T91	3		T236	7
values[27]	238	1			T30	2		T91	2		T236	3
values[28]	257	1			T30	2		T91	10		T236	8
values[29]	248	1			T30	2		T91	14		T236	13
values[30]	264	1			T30	2		T91	13		T236	8
values[31]	266	1			T30	2		T91	11		T236	8
values[32]	245	1			T30	2		T91	14		T236	2
values[33]	234	1			T30	2		T91	9		T236	5
values[34]	239	1			T30	2		T91	5		T236	7
values[35]	248	1			T30	2		T91	6		T236	7
values[36]	245	1			T30	2		T91	8		T236	10
values[37]	218	1			T30	2		T91	5		T236	5
values[38]	223	1			T30	2		T91	11		T236	11
values[39]	195	1			T30	2		T91	5		T236	5
values[40]	265	1			T30	2		T91	6		T236	22
values[41]	260	1			T30	2		T91	3		T236	6
values[42]	218	1			T30	2		T91	5		T236	5
values[43]	271	1			T30	2		T91	5		T236	4
values[44]	228	1			T30	2		T91	7		T236	14
values[45]	254	1			T30	2		T91	7		T236	4
values[46]	241	1			T30	2		T91	7		T236	5
values[47]	219	1			T30	2		T91	8		T236	4
values[48]	252	1			T30	2		T91	13		T236	13
values[49]	271	1			T30	2		T91	9		T236	11
values[50]	251	1			T30	2		T91	14		T236	8
values[51]	226	1			T30	2		T91	5		T236	5
values[52]	230	1			T30	2		T91	9		T236	7
values[53]	196	1			T30	2		T91	3		T236	5
values[54]	214	1			T30	2		T91	9		T236	6
values[55]	187	1			T30	2		T91	8		T236	3
values[56]	196	1			T30	2		T91	7		T236	5
values[57]	178	1			T30	2		T91	5		T236	3
values[58]	189	1			T30	2		T91	5		T236	2
values[59]	163	1			T30	2		T91	6		T236	4
values[60]	138	1			T30	2		T91	8		T236	12
values[61]	177	1			T30	2		T91	17		T236	4
values[62]	161	1			T30	2		T91	9		T236	8
values[63]	175	1			T30	2		T91	5		T236	4
values[64]	159	1			T30	2		T91	6		T236	18
values[65]	169	1			T30	2		T91	3		T236	8
values[66]	138	1			T30	2		T91	13		T236	13
values[67]	108	1			T30	2		T91	5		T236	10
values[68]	111	1			T30	2		T236	11		T95	2
values[69]	95	1			T30	2		T95	2		T350	1
values[70]	72	1			T30	2		T95	2		T350	1
values[71]	72	1			T30	2		T95	2		T350	1
values[72]	80	1			T30	2		T95	2		T350	1
values[73]	73	1			T30	2		T95	2		T350	1
values[74]	83	1			T30	2		T95	2		T350	1
values[75]	69	1			T30	2		T95	2		T350	1
values[76]	73	1			T30	2		T95	2		T350	1
values[77]	63	1			T30	2		T95	2		T350	1
values[78]	53	1			T30	2		T95	2		T350	1
values[79]	56	1			T30	2		T95	2		T350	1
values[80]	46	1			T30	2		T95	2		T350	1
values[81]	82	1			T30	2		T95	2		T350	1
values[82]	73	1			T30	2		T95	2		T350	1
values[83]	114	1			T30	2		T95	2		T350	1
values[84]	74	1			T30	2		T95	2		T350	1
values[85]	71	1			T30	3		T95	2		T350	1
values[86]	72	1			T30	2		T95	2		T350	1
values[87]	64	1			T30	2		T95	2		T350	1
values[88]	63	1			T30	2		T95	5		T350	1
values[89]	58	1			T30	2		T95	6		T350	1
values[90]	77	1			T30	2		T95	7		T350	1
values[91]	77	1			T30	2		T95	6		T350	1
values[92]	67	1			T30	2		T95	3		T350	1
values[93]	58	1			T30	2		T95	6		T350	1
values[94]	68	1			T30	2		T95	2		T350	1
values[95]	53	1			T30	2		T95	4		T350	1
values[96]	67	1			T30	2		T95	4		T350	1
values[97]	62	1			T30	2		T95	2		T350	1
values[98]	81	1			T30	2		T95	7		T350	1
values[99]	77	1			T30	2		T95	5		T350	1
values[100]	89	1			T30	2		T95	10		T350	1
values[101]	78	1			T30	2		T95	3		T350	1
values[102]	77	1			T30	2		T95	5		T350	1
values[103]	64	1			T30	2		T95	5		T350	1
values[104]	62	1			T30	2		T95	3		T350	2
values[105]	65	1			T30	2		T95	5		T350	1
values[106]	69	1			T30	2		T95	3		T350	1
values[107]	61	1			T30	2		T95	5		T350	1
values[108]	50	1			T30	3		T95	2		T350	1
values[109]	63	1			T30	4		T95	9		T350	1
values[110]	68	1			T30	2		T95	8		T350	1
values[111]	70	1			T30	5		T95	5		T350	1
values[112]	72	1			T30	5		T95	5		T350	1
values[113]	63	1			T30	2		T95	4		T350	1
values[114]	59	1			T30	2		T95	3		T350	1
values[115]	59	1			T30	3		T95	2		T350	1
values[116]	51	1			T30	3		T95	3		T350	1
values[117]	48	1			T30	3		T95	2		T350	1
values[118]	65	1			T30	5		T95	4		T350	1
values[119]	70	1			T30	3		T95	7		T350	1
values[120]	49	1			T30	3		T95	3		T350	1
values[121]	60	1			T30	5		T95	4		T350	1
values[122]	58	1			T30	8		T95	6		T350	3
values[123]	61	1			T30	5		T95	3		T350	1
values[124]	69	1			T30	8		T95	4		T350	2
values[125]	68	1			T30	2		T95	4		T350	1
values[126]	117	1			T30	4		T95	3		T350	4
values[127]	784	1			T30	54		T95	52		T350	31
values[128]	6734	1			T30	655		T95	594		T350	281