Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	157980	1			T11	38		T12	933		T13	117
values[2]	4081	1			T11	3		T12	52		T30	1
values[3]	1914	1			T12	20		T30	1		T58	82
values[4]	1384	1			T12	5		T30	1		T58	74
values[5]	1076	1			T12	2		T30	1		T58	78
values[6]	875	1			T30	1		T58	50		T282	5
values[7]	666	1			T30	1		T58	14		T282	12
values[8]	591	1			T30	1		T58	3		T282	15
values[9]	486	1			T30	1		T282	10		T274	8
values[10]	459	1			T30	1		T282	2		T274	4
values[11]	449	1			T30	1		T274	10		T339	23
values[12]	391	1			T30	1		T274	2		T339	21
values[13]	354	1			T30	1		T274	3		T339	20
values[14]	358	1			T30	1		T274	3		T339	56
values[15]	410	1			T30	1		T274	2		T339	48
values[16]	449	1			T30	1		T274	1		T339	76
values[17]	456	1			T30	1		T274	4		T339	57
values[18]	363	1			T30	1		T274	18		T339	34
values[19]	295	1			T30	1		T274	9		T339	17
values[20]	293	1			T30	1		T274	3		T339	4
values[21]	276	1			T30	1		T274	3		T339	6
values[22]	247	1			T30	1		T274	5		T339	2
values[23]	204	1			T30	1		T274	2		T334	1
values[24]	231	1			T30	1		T274	15		T334	1
values[25]	291	1			T30	1		T274	11		T334	1
values[26]	254	1			T30	1		T274	17		T334	1
values[27]	201	1			T30	1		T274	14		T334	1
values[28]	221	1			T30	1		T274	8		T334	1
values[29]	226	1			T30	1		T274	27		T334	1
values[30]	186	1			T30	1		T274	21		T334	1
values[31]	192	1			T30	1		T274	30		T334	1
values[32]	226	1			T30	1		T274	33		T334	1
values[33]	227	1			T30	1		T274	46		T334	1
values[34]	231	1			T30	1		T274	41		T334	1
values[35]	223	1			T30	1		T274	39		T334	1
values[36]	157	1			T30	1		T274	17		T334	1
values[37]	138	1			T30	1		T274	19		T334	1
values[38]	141	1			T30	1		T274	17		T334	1
values[39]	127	1			T30	1		T274	10		T334	1
values[40]	124	1			T30	1		T274	3		T334	1
values[41]	140	1			T30	1		T274	8		T334	1
values[42]	98	1			T30	1		T274	4		T334	1
values[43]	99	1			T30	1		T274	3		T334	1
values[44]	81	1			T30	1		T334	1		T340	4
values[45]	91	1			T30	1		T334	1		T340	1
values[46]	85	1			T30	1		T334	1		T340	2
values[47]	89	1			T30	1		T334	1		T340	1
values[48]	102	1			T30	1		T334	1		T340	4
values[49]	75	1			T30	1		T334	1		T340	1
values[50]	78	1			T30	1		T334	1		T340	2
values[51]	79	1			T30	1		T334	1		T340	2
values[52]	81	1			T30	1		T334	1		T340	1
values[53]	82	1			T30	1		T334	1		T340	4
values[54]	88	1			T30	1		T334	1		T340	3
values[55]	77	1			T30	1		T334	1		T340	1
values[56]	70	1			T30	1		T334	1		T340	3
values[57]	70	1			T30	2		T334	1		T340	5
values[58]	74	1			T30	1		T334	1		T340	1
values[59]	72	1			T30	1		T334	1		T340	1
values[60]	71	1			T30	1		T334	1		T340	1
values[61]	80	1			T30	1		T334	1		T340	6
values[62]	90	1			T30	1		T334	1		T340	11
values[63]	84	1			T30	1		T334	1		T340	4
values[64]	77	1			T30	1		T334	1		T340	6
values[65]	77	1			T30	1		T334	1		T340	2
values[66]	74	1			T30	1		T334	1		T340	2
values[67]	69	1			T30	1		T334	1		T340	2
values[68]	68	1			T30	1		T334	1		T340	1
values[69]	76	1			T30	1		T334	1		T340	3
values[70]	62	1			T30	1		T334	1		T340	2
values[71]	62	1			T30	1		T334	1		T340	1
values[72]	73	1			T30	1		T334	1		T340	1
values[73]	74	1			T30	1		T334	1		T340	1
values[74]	71	1			T30	1		T334	1		T340	2
values[75]	73	1			T30	1		T334	1		T340	3
values[76]	89	1			T30	1		T334	1		T340	6
values[77]	107	1			T30	1		T334	1		T340	5
values[78]	107	1			T30	1		T334	1		T340	5
values[79]	101	1			T30	1		T334	1		T340	3
values[80]	88	1			T30	1		T334	1		T340	2
values[81]	101	1			T30	1		T334	1		T340	1
values[82]	103	1			T30	1		T334	1		T340	2
values[83]	89	1			T30	1		T334	1		T340	2
values[84]	72	1			T30	1		T334	1		T340	1
values[85]	98	1			T30	1		T334	1		T340	5
values[86]	96	1			T30	1		T334	1		T340	2
values[87]	111	1			T30	1		T334	1		T340	1
values[88]	101	1			T30	1		T334	1		T340	2
values[89]	89	1			T30	1		T334	1		T340	1
values[90]	89	1			T30	1		T334	1		T340	3
values[91]	91	1			T30	1		T334	1		T340	5
values[92]	130	1			T30	1		T334	1		T340	2
values[93]	110	1			T30	1		T334	1		T340	2
values[94]	101	1			T30	1		T334	1		T340	1
values[95]	122	1			T30	1		T334	1		T340	6
values[96]	123	1			T30	1		T334	1		T340	7
values[97]	133	1			T30	1		T334	1		T340	3
values[98]	119	1			T30	1		T334	1		T340	3
values[99]	112	1			T30	1		T334	3		T340	1
values[100]	111	1			T30	1		T334	2		T340	3
values[101]	115	1			T30	1		T334	1		T340	5
values[102]	136	1			T30	1		T334	6		T340	4
values[103]	122	1			T30	1		T334	3		T340	2
values[104]	119	1			T30	1		T334	3		T340	2
values[105]	119	1			T30	1		T334	2		T340	6
values[106]	122	1			T30	1		T334	4		T340	2
values[107]	111	1			T30	1		T334	1		T340	1
values[108]	134	1			T30	1		T334	1		T340	2
values[109]	131	1			T30	1		T334	1		T340	4
values[110]	115	1			T30	1		T334	1		T340	4
values[111]	118	1			T30	1		T334	2		T340	4
values[112]	131	1			T30	1		T334	1		T340	9
values[113]	139	1			T30	1		T334	3		T340	6
values[114]	147	1			T30	1		T334	8		T340	3
values[115]	148	1			T30	1		T334	3		T340	2
values[116]	141	1			T30	1		T334	4		T340	8
values[117]	155	1			T30	4		T334	3		T340	8
values[118]	136	1			T30	1		T334	1		T340	15
values[119]	146	1			T30	3		T334	1		T340	8
values[120]	153	1			T30	1		T334	1		T340	3
values[121]	127	1			T30	1		T334	1		T340	2
values[122]	157	1			T30	3		T334	2		T340	4
values[123]	159	1			T30	2		T334	4		T340	10
values[124]	278	1			T30	1		T334	1		T340	26
values[125]	511	1			T30	3		T334	5		T340	40
values[126]	1113	1			T30	14		T334	11		T340	40
values[127]	3124	1			T30	99		T334	99		T340	41
values[128]	5278	1			T30	186		T334	212		T340	3