Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127685 |
1 |
|
|
T11 |
30 |
|
T12 |
281 |
|
T13 |
50 |
| auto[1] |
64842 |
1 |
|
|
T11 |
2 |
|
T12 |
163 |
|
T13 |
38 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50010 |
1 |
|
|
T11 |
14 |
|
T12 |
47 |
|
T13 |
39 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
134939 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57588 |
1 |
|
|
T11 |
9 |
|
T12 |
107 |
|
T13 |
26 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15571 |
1 |
|
|
T11 |
4 |
|
T12 |
10 |
|
T13 |
12 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129179 |
1 |
|
|
T11 |
13 |
|
T12 |
1314 |
|
T13 |
119 |
| auto[1] |
68683 |
1 |
|
|
T11 |
24 |
|
T12 |
179 |
|
T13 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50146 |
1 |
|
|
T11 |
9 |
|
T12 |
182 |
|
T13 |
37 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
138991 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58871 |
1 |
|
|
T11 |
8 |
|
T12 |
387 |
|
T13 |
50 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15671 |
1 |
|
|
T11 |
2 |
|
T12 |
39 |
|
T13 |
15 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123975 |
1 |
|
|
T11 |
42 |
|
T12 |
162 |
|
T13 |
67 |
| auto[1] |
69147 |
1 |
|
|
T12 |
306 |
|
T13 |
56 |
|
T31 |
18 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49860 |
1 |
|
|
T11 |
15 |
|
T12 |
51 |
|
T13 |
36 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
135625 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57497 |
1 |
|
|
T11 |
8 |
|
T12 |
122 |
|
T13 |
35 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15342 |
1 |
|
|
T11 |
3 |
|
T12 |
12 |
|
T13 |
6 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128542 |
1 |
|
|
T11 |
37 |
|
T12 |
515 |
|
T13 |
116 |
| auto[1] |
63026 |
1 |
|
|
T11 |
2 |
|
T12 |
445 |
|
T31 |
33 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49753 |
1 |
|
|
T11 |
18 |
|
T12 |
128 |
|
T13 |
44 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
134407 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57161 |
1 |
|
|
T11 |
8 |
|
T12 |
227 |
|
T13 |
33 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15746 |
1 |
|
|
T11 |
4 |
|
T12 |
39 |
|
T13 |
13 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125458 |
1 |
|
|
T11 |
52 |
|
T12 |
146 |
|
T13 |
70 |
| auto[1] |
68840 |
1 |
|
|
T12 |
317 |
|
T13 |
49 |
|
T31 |
24 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49546 |
1 |
|
|
T11 |
14 |
|
T12 |
47 |
|
T13 |
44 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
136840 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57458 |
1 |
|
|
T11 |
13 |
|
T12 |
119 |
|
T13 |
42 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15438 |
1 |
|
|
T11 |
1 |
|
T12 |
12 |
|
T13 |
22 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125382 |
1 |
|
|
T11 |
45 |
|
T12 |
378 |
|
T13 |
28 |
| auto[1] |
67530 |
1 |
|
|
T11 |
5 |
|
T12 |
93 |
|
T13 |
66 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49221 |
1 |
|
|
T11 |
12 |
|
T12 |
55 |
|
T13 |
28 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
135477 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57435 |
1 |
|
|
T11 |
15 |
|
T12 |
96 |
|
T13 |
28 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15414 |
1 |
|
|
T11 |
2 |
|
T12 |
13 |
|
T13 |
9 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134025 |
1 |
|
|
T11 |
23 |
|
T12 |
312 |
|
T13 |
111 |
| auto[1] |
74871 |
1 |
|
|
T11 |
18 |
|
T12 |
119 |
|
T13 |
5 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
53543 |
1 |
|
|
T11 |
15 |
|
T12 |
48 |
|
T13 |
48 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
146506 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
62390 |
1 |
|
|
T11 |
18 |
|
T12 |
114 |
|
T13 |
37 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16717 |
1 |
|
|
T11 |
3 |
|
T12 |
14 |
|
T13 |
14 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124888 |
1 |
|
|
T11 |
40 |
|
T12 |
695 |
|
T13 |
47 |
| auto[1] |
69501 |
1 |
|
|
T11 |
1 |
|
T12 |
271 |
|
T13 |
56 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49242 |
1 |
|
|
T11 |
16 |
|
T12 |
123 |
|
T13 |
32 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
136256 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58133 |
1 |
|
|
T11 |
18 |
|
T12 |
231 |
|
T13 |
42 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15619 |
1 |
|
|
T11 |
5 |
|
T12 |
32 |
|
T13 |
15 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130027 |
1 |
|
|
T11 |
17 |
|
T12 |
168 |
|
T13 |
53 |
| auto[1] |
66397 |
1 |
|
|
T11 |
27 |
|
T12 |
315 |
|
T13 |
69 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
51204 |
1 |
|
|
T11 |
13 |
|
T12 |
56 |
|
T13 |
45 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137254 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
59170 |
1 |
|
|
T11 |
13 |
|
T12 |
108 |
|
T13 |
33 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16046 |
1 |
|
|
T11 |
2 |
|
T12 |
15 |
|
T13 |
12 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135771 |
1 |
|
|
T11 |
35 |
|
T12 |
425 |
|
T13 |
57 |
| auto[1] |
69845 |
1 |
|
|
T11 |
9 |
|
T12 |
27 |
|
T13 |
71 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
52040 |
1 |
|
|
T11 |
15 |
|
T12 |
60 |
|
T13 |
39 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
144425 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
61191 |
1 |
|
|
T11 |
16 |
|
T12 |
110 |
|
T13 |
39 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16371 |
1 |
|
|
T11 |
3 |
|
T12 |
13 |
|
T13 |
9 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128063 |
1 |
|
|
T11 |
32 |
|
T12 |
1004 |
|
T13 |
52 |
| auto[1] |
68169 |
1 |
|
|
T11 |
9 |
|
T12 |
8 |
|
T13 |
65 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50106 |
1 |
|
|
T11 |
17 |
|
T12 |
139 |
|
T13 |
42 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137568 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58664 |
1 |
|
|
T11 |
16 |
|
T12 |
279 |
|
T13 |
37 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15664 |
1 |
|
|
T11 |
10 |
|
T12 |
38 |
|
T13 |
13 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1000866 |
1 |
|
|
T11 |
161 |
|
T12 |
4260 |
|
T13 |
566 |
| auto[1] |
522485 |
1 |
|
|
T11 |
138 |
|
T12 |
1706 |
|
T13 |
310 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
394795 |
1 |
|
|
T11 |
93 |
|
T12 |
762 |
|
T13 |
300 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
1057107 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
466244 |
1 |
|
|
T11 |
114 |
|
T12 |
1457 |
|
T13 |
293 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
126061 |
1 |
|
|
T11 |
29 |
|
T12 |
196 |
|
T13 |
97 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126005 |
1 |
|
|
T11 |
31 |
|
T12 |
860 |
|
T13 |
99 |
| auto[1] |
66914 |
1 |
|
|
T11 |
10 |
|
T12 |
101 |
|
T13 |
13 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50015 |
1 |
|
|
T11 |
5 |
|
T12 |
122 |
|
T13 |
42 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
135101 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57818 |
1 |
|
|
T11 |
9 |
|
T12 |
244 |
|
T13 |
34 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15672 |
1 |
|
|
T11 |
2 |
|
T12 |
31 |
|
T13 |
15 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129046 |
1 |
|
|
T11 |
22 |
|
T12 |
321 |
|
T13 |
33 |
| auto[1] |
64856 |
1 |
|
|
T11 |
6 |
|
T12 |
613 |
|
T13 |
80 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
48772 |
1 |
|
|
T11 |
7 |
|
T12 |
114 |
|
T13 |
44 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
136176 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
57726 |
1 |
|
|
T11 |
15 |
|
T12 |
234 |
|
T13 |
29 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15254 |
1 |
|
|
T11 |
5 |
|
T12 |
31 |
|
T13 |
10 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126722 |
1 |
|
|
T11 |
28 |
|
T12 |
731 |
|
T13 |
82 |
| auto[1] |
70118 |
1 |
|
|
T11 |
15 |
|
T12 |
741 |
|
T13 |
42 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49691 |
1 |
|
|
T11 |
13 |
|
T12 |
182 |
|
T13 |
45 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137142 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
59698 |
1 |
|
|
T11 |
17 |
|
T12 |
402 |
|
T13 |
44 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15597 |
1 |
|
|
T11 |
4 |
|
T12 |
45 |
|
T13 |
21 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126579 |
1 |
|
|
T11 |
41 |
|
T12 |
629 |
|
T13 |
101 |
| auto[1] |
70061 |
1 |
|
|
T11 |
1 |
|
T12 |
186 |
|
T13 |
21 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50253 |
1 |
|
|
T11 |
12 |
|
T12 |
98 |
|
T13 |
43 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137892 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58748 |
1 |
|
|
T11 |
17 |
|
T12 |
211 |
|
T13 |
39 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15747 |
1 |
|
|
T11 |
8 |
|
T12 |
29 |
|
T13 |
15 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124555 |
1 |
|
|
T11 |
39 |
|
T12 |
453 |
|
T13 |
99 |
| auto[1] |
69968 |
1 |
|
|
T11 |
5 |
|
T12 |
560 |
|
T13 |
19 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50406 |
1 |
|
|
T11 |
15 |
|
T12 |
139 |
|
T13 |
33 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
136127 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58396 |
1 |
|
|
T11 |
13 |
|
T12 |
262 |
|
T13 |
36 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16065 |
1 |
|
|
T11 |
5 |
|
T12 |
37 |
|
T13 |
10 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121522 |
1 |
|
|
T11 |
36 |
|
T12 |
192 |
|
T13 |
69 |
| auto[1] |
65172 |
1 |
|
|
T11 |
16 |
|
T12 |
263 |
|
T13 |
54 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49222 |
1 |
|
|
T11 |
19 |
|
T12 |
61 |
|
T13 |
42 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
131005 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
55689 |
1 |
|
|
T11 |
17 |
|
T12 |
118 |
|
T13 |
43 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15421 |
1 |
|
|
T11 |
8 |
|
T12 |
20 |
|
T13 |
15 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134726 |
1 |
|
|
T11 |
24 |
|
T12 |
500 |
|
T13 |
39 |
| auto[1] |
70076 |
1 |
|
|
T11 |
12 |
|
T12 |
11 |
|
T13 |
75 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
53409 |
1 |
|
|
T11 |
12 |
|
T12 |
59 |
|
T13 |
47 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
143398 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
61404 |
1 |
|
|
T11 |
12 |
|
T12 |
139 |
|
T13 |
45 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16774 |
1 |
|
|
T11 |
4 |
|
T12 |
10 |
|
T13 |
18 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
125927 |
1 |
|
|
T11 |
14 |
|
T12 |
585 |
|
T13 |
52 |
| auto[1] |
64098 |
1 |
|
|
T11 |
22 |
|
T12 |
396 |
|
T13 |
82 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
49842 |
1 |
|
|
T11 |
15 |
|
T12 |
130 |
|
T13 |
38 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
131864 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58161 |
1 |
|
|
T11 |
13 |
|
T12 |
244 |
|
T13 |
36 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15869 |
1 |
|
|
T11 |
5 |
|
T12 |
35 |
|
T13 |
14 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127456 |
1 |
|
|
T11 |
18 |
|
T12 |
659 |
|
T13 |
113 |
| auto[1] |
67427 |
1 |
|
|
T11 |
16 |
|
T12 |
308 |
|
T13 |
12 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50613 |
1 |
|
|
T11 |
9 |
|
T12 |
113 |
|
T13 |
44 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
136721 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58162 |
1 |
|
|
T11 |
12 |
|
T12 |
216 |
|
T13 |
42 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15723 |
1 |
|
|
T11 |
4 |
|
T12 |
28 |
|
T13 |
17 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136857 |
1 |
|
|
T11 |
43 |
|
T12 |
198 |
|
T13 |
80 |
| auto[1] |
72162 |
1 |
|
|
T11 |
1 |
|
T12 |
281 |
|
T13 |
30 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
54664 |
1 |
|
|
T11 |
17 |
|
T12 |
50 |
|
T13 |
42 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
144971 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
64048 |
1 |
|
|
T11 |
9 |
|
T12 |
134 |
|
T13 |
38 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
17541 |
1 |
|
|
T11 |
4 |
|
T12 |
14 |
|
T13 |
16 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129591 |
1 |
|
|
T11 |
10 |
|
T12 |
268 |
|
T13 |
107 |
| auto[1] |
67852 |
1 |
|
|
T11 |
28 |
|
T12 |
211 |
|
T13 |
2 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
51097 |
1 |
|
|
T11 |
11 |
|
T12 |
53 |
|
T13 |
34 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137383 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
60060 |
1 |
|
|
T11 |
13 |
|
T12 |
115 |
|
T13 |
35 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16126 |
1 |
|
|
T11 |
6 |
|
T12 |
14 |
|
T13 |
6 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121254 |
1 |
|
|
T11 |
37 |
|
T12 |
905 |
|
T13 |
33 |
| auto[1] |
64812 |
1 |
|
|
T11 |
2 |
|
T12 |
133 |
|
T13 |
63 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
47892 |
1 |
|
|
T11 |
13 |
|
T12 |
125 |
|
T13 |
31 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
130242 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
55824 |
1 |
|
|
T11 |
13 |
|
T12 |
287 |
|
T13 |
30 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15165 |
1 |
|
|
T11 |
5 |
|
T12 |
38 |
|
T13 |
8 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126782 |
1 |
|
|
T11 |
26 |
|
T12 |
1450 |
|
T13 |
43 |
| auto[1] |
71271 |
1 |
|
|
T11 |
4 |
|
T12 |
556 |
|
T13 |
60 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
50973 |
1 |
|
|
T11 |
8 |
|
T12 |
260 |
|
T13 |
33 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
139183 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
58870 |
1 |
|
|
T11 |
14 |
|
T12 |
490 |
|
T13 |
34 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
15691 |
1 |
|
|
T11 |
4 |
|
T12 |
57 |
|
T13 |
16 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133541 |
1 |
|
|
T11 |
34 |
|
T12 |
239 |
|
T13 |
82 |
| auto[1] |
64589 |
1 |
|
|
T12 |
235 |
|
T13 |
38 |
|
T31 |
17 |
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
52299 |
1 |
|
|
T11 |
11 |
|
T12 |
60 |
|
T13 |
45 |
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| others |
137108 |
Excluded |
Covered bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| biggest_size |
61022 |
1 |
|
|
T11 |
13 |
|
T12 |
103 |
|
T13 |
40 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| values[0x1] |
biggest_size |
16768 |
1 |
|
|
T11 |
6 |
|
T12 |
11 |
|
T13 |
16 |
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
124377 |
1 |
|
|
T11 |
19 |
|
T12 |
196 |
|
T13 |
74 |
| auto[1] |
62246 |
1 |
|
|
T11 |
6 |
|
T12 |
287 |
|
T13 |
45 |