Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	493	1			T30	1		T91	2		T236	1
all_values[1]	457	1			T85	3		T58	1		T91	1
all_values[2]	449	1			T85	1		T58	1		T364	1
all_values[3]	508	1			T30	1		T85	4		T237	3
all_values[4]	471	1			T85	3		T58	1		T236	2
all_values[5]	460	1			T12	2		T91	1		T364	1
all_values[6]	532	1			T12	3		T85	4		T58	1
all_values[7]	470	1			T12	1		T30	1		T85	2
all_values[8]	436	1			T12	1		T30	2		T85	2
all_values[9]	471	1			T12	1		T85	2		T91	2
all_values[10]	492	1			T12	2		T85	3		T237	2
all_values[11]	435	1			T12	1		T85	2		T237	3
all_values[12]	492	1			T12	2		T85	2		T91	2
all_values[13]	505	1			T85	5		T58	2		T236	1
all_values[14]	505	1			T85	2		T58	1		T237	1
all_values[15]	454	1			T12	1		T85	1		T237	3
all_values[16]	468	1			T85	2		T237	4		T325	1
all_values[17]	528	1			T12	1		T85	3		T91	1
all_values[18]	511	1			T85	4		T236	3		T237	1
all_values[19]	534	1			T85	3		T58	1		T364	1
all_values[20]	514	1			T85	7		T58	1		T91	1
all_values[21]	485	1			T85	2		T58	1		T237	2
all_values[22]	484	1			T30	1		T85	1		T58	1
all_values[23]	488	1			T85	4		T58	1		T91	1
all_values[24]	482	1			T85	1		T237	1		T59	3
all_values[25]	487	1			T30	1		T85	4		T237	4
all_values[26]	463	1			T85	2		T237	1		T333	1
all_values[27]	481	1			T12	1		T85	4		T364	1
all_values[28]	532	1			T12	1		T30	1		T85	1
all_values[29]	459	1			T85	3		T58	2		T364	1
all_values[30]	518	1			T12	3		T30	1		T58	2
all_values[31]	495	1			T85	2		T236	1		T237	2
all_values[32]	517	1			T12	1		T30	2		T85	2
all_values[33]	501	1			T12	1		T30	1		T85	1
all_values[34]	452	1			T85	4		T364	3		T237	2
all_values[35]	479	1			T30	1		T85	4		T58	1
all_values[36]	498	1			T12	1		T85	4		T236	2
all_values[37]	469	1			T323	2		T66	1		T60	4
all_values[38]	496	1			T85	2		T58	2		T364	2
all_values[39]	481	1			T85	3		T58	4		T237	2
all_values[40]	485	1			T12	1		T85	1		T91	1
all_values[41]	483	1			T12	1		T85	4		T58	1
all_values[42]	506	1			T30	1		T85	3		T58	3
all_values[43]	506	1			T85	1		T236	1		T364	5
all_values[44]	477	1			T12	1		T58	1		T91	1
all_values[45]	469	1			T12	1		T30	2		T85	5
all_values[46]	486	1			T12	1		T30	1		T85	2
all_values[47]	436	1			T85	2		T236	1		T237	3
all_values[48]	490	1			T85	1		T91	1		T236	1
all_values[49]	511	1			T85	5		T58	1		T236	1