Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3718	1			T12	5		T85	22		T58	6
all_values[1]	3758	1			T12	4		T85	21		T58	12
all_values[2]	3870	1			T12	5		T85	21		T58	13
all_values[3]	3760	1			T12	2		T85	31		T58	8
all_values[4]	3686	1			T12	3		T85	28		T58	5
all_values[5]	3842	1			T12	3		T85	21		T58	8
all_values[6]	3890	1			T12	4		T85	25		T58	6
all_values[7]	3861	1			T12	4		T85	27		T58	13
all_values[8]	3712	1			T12	6		T85	27		T58	11
all_values[9]	3841	1			T12	12		T85	23		T58	8
all_values[10]	3882	1			T12	1		T85	29		T58	11
all_values[11]	3867	1			T12	7		T85	22		T58	11
all_values[12]	3755	1			T12	5		T85	29		T58	7
all_values[13]	3883	1			T12	5		T85	22		T58	12
all_values[14]	3752	1			T12	6		T85	27		T58	7
all_values[15]	3752	1			T12	6		T85	17		T58	10
all_values[16]	3882	1			T12	5		T85	20		T58	8
all_values[17]	3745	1			T12	3		T85	25		T58	8
all_values[18]	3807	1			T12	1		T85	26		T58	9
all_values[19]	3781	1			T12	3		T85	18		T58	11
all_values[20]	3776	1			T12	4		T85	28		T58	6
all_values[21]	3747	1			T12	6		T85	30		T58	10
all_values[22]	3768	1			T12	3		T85	21		T58	7
all_values[23]	3909	1			T85	25		T58	8		T364	5
all_values[24]	3766	1			T12	6		T85	19		T58	8
all_values[25]	3648	1			T12	3		T85	28		T58	5
all_values[26]	3822	1			T12	6		T85	23		T58	14
all_values[27]	3780	1			T12	1		T85	26		T58	9
all_values[28]	3693	1			T12	4		T85	17		T58	5
all_values[29]	3831	1			T12	1		T85	16		T364	7
all_values[30]	3813	1			T12	5		T85	23		T58	9
all_values[31]	3853	1			T12	3		T85	29		T58	6
all_values[32]	3826	1			T12	3		T85	23		T58	10
all_values[33]	3887	1			T12	11		T85	25		T58	4
all_values[34]	3830	1			T12	8		T85	25		T58	6
all_values[35]	3784	1			T12	7		T85	28		T58	6
all_values[36]	3771	1			T12	5		T85	22		T58	15
all_values[37]	3807	1			T12	4		T85	23		T58	3
all_values[38]	3756	1			T12	1		T85	29		T58	5
all_values[39]	3832	1			T12	5		T85	26		T58	3
all_values[40]	3850	1			T12	4		T85	24		T58	9
all_values[41]	3954	1			T12	3		T85	27		T58	13
all_values[42]	3679	1			T12	9		T85	32		T58	4
all_values[43]	3800	1			T12	1		T85	21		T58	4
all_values[44]	3749	1			T12	4		T85	29		T58	4
all_values[45]	3827	1			T12	1		T85	34		T58	11
all_values[46]	3710	1			T12	2		T85	23		T58	12
all_values[47]	3746	1			T12	6		T85	19		T58	7
all_values[48]	3726	1			T12	6		T85	24		T58	11
all_values[49]	3810	1			T12	3		T85	26		T58	8
all_values[50]	3813	1			T12	4		T85	21		T58	6
all_values[51]	3683	1			T12	4		T85	25		T58	6
all_values[52]	3847	1			T12	3		T85	38		T58	5
all_values[53]	3739	1			T12	5		T85	29		T58	9
all_values[54]	3702	1			T12	5		T85	23		T58	8
all_values[55]	3713	1			T12	6		T85	25		T58	13
all_values[56]	3860	1			T12	4		T85	36		T58	10
all_values[57]	3747	1			T12	4		T85	28		T58	6
all_values[58]	3768	1			T12	3		T85	22		T58	6
all_values[59]	3754	1			T12	3		T85	24		T58	7
all_values[60]	3799	1			T12	4		T85	34		T58	6
all_values[61]	3816	1			T12	3		T85	30		T58	8
all_values[62]	3784	1			T12	1		T85	38		T58	6
all_values[63]	3874	1			T12	4		T85	27		T58	11