Unified Coverage Report :: Cond split page

Go back

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T13
1	1	Covered	T3,T38,T14

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T12,T31,T85
1	0	0	Not Covered

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T12,T31,T85
0	1	0	Covered	T38,T39,T103
1	0	0	Covered	T11,T13,T56

 LINE       16120
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO0_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T11,T12

 LINE       16121
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO1_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16122
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO2_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16123
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO3_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16124
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO4_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16125
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO5_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16126
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO6_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16127
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO7_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16128
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO8_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16129
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO9_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16130
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO10_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16131
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO11_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16132
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO12_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16133
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO13_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16134
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO14_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16135
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO15_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16136
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO16_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16137
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO17_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16138
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO18_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16139
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO19_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T14,T39

 LINE       16140
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO20_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16141
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO21_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16142
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO22_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16143
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO23_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16144
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO24_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16145
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO25_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16146
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO26_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16147
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO27_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16148
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO28_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16149
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO29_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16150
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO30_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16151
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO31_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16152
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO32_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16153
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO33_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16154
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO34_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16155
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO35_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16156
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO36_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16157
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO37_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16158
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO38_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16159
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO39_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16160
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO40_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16161
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO41_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16162
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO42_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16163
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO43_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16164
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO44_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16165
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO45_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16166
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO46_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T14,T39

 LINE       16167
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO47_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16168
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO48_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16169
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO49_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16170
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO50_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16171
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO51_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16172
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO52_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16173
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO53_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16174
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO54_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16175
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO55_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16176
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO56_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16177
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO57_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16178
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO58_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16179
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO59_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16180
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO60_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16181
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO61_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16182
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO62_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16183
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO63_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16184
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO64_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16185
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO65_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16186
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO66_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16187
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO67_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16188
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO68_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16189
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO69_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16190
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO70_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16191
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO71_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16192
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO72_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T14,T39

 LINE       16193
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO73_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16194
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO74_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16195
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO75_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16196
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO76_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16197
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO77_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16198
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO78_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16199
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO79_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16200
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO80_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16201
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO81_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16202
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO82_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16203
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO83_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16204
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO84_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16205
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO85_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16206
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO86_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16207
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO87_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16208
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO88_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16209
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO89_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16210
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO90_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16211
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO91_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16212
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO92_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16213
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO93_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16214
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO94_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16215
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO95_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16216
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO96_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16217
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO97_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16218
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO98_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16219
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO99_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16220
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO100_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16221
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO101_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16222
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO102_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16223
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO103_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T14,T39

 LINE       16224
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO104_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16225
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO105_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16226
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO106_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16227
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO107_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16228
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO108_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16229
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO109_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16230
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO110_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16231
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO111_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16232
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO112_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16233
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO113_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16234
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO114_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16235
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO115_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16236
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO116_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16237
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO117_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16238
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO118_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16239
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO119_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16240
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO120_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16241
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO121_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16242
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO122_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16243
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO123_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16244
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO124_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T14,T39

 LINE       16245
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO125_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16246
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO126_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16247
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO127_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16248
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO128_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16249
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO129_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16250
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO130_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16251
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO131_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16252
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO132_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16253
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO133_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16254
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO134_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16255
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO135_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16256
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO136_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16257
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO137_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16258
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO138_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T14,T39

 LINE       16259
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO139_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16260
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO140_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16261
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO141_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16262
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO142_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16263
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO143_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16264
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO144_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16265
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO145_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16266
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO146_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16267
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO147_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16268
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO148_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16269
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO149_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16270
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO150_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16271
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO151_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16272
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO152_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16273
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO153_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16274
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO154_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16275
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO155_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16276
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO156_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16277
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO157_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16278
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO158_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16279
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO159_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16280
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO160_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16281
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO161_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16282
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO162_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16283
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO163_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16284
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO164_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T14,T39

 LINE       16285
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO165_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16286
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO166_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16287
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO167_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16288
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO168_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16289
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO169_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16290
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO170_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16291
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO171_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16292
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO172_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16293
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO173_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T14,T39

 LINE       16294
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO174_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16295
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO175_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16296
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO176_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16297
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO177_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16298
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO178_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16299
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_PRIO179_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16300
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_0_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16301
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_1_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16302
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_2_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16303
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_3_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16304
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_4_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16305
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IP_5_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16306
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_0_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16307
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_1_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16308
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_2_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16309
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_3_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14

 LINE       16310
 EXPRESSION (reg_addr == rv_plic_reg_pkg::RV_PLIC_IE0_4_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T3,T38,T14