Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	140199	1			T11	172		T12	11		T13	23
values[2]	8313	1			T13	2		T14	5		T28	70
values[3]	3034	1			T28	69		T68	3		T55	3
values[4]	1707	1			T28	31		T55	1		T312	2
values[5]	1090	1			T28	27		T55	2		T312	2
values[6]	692	1			T28	20		T55	5		T312	2
values[7]	522	1			T28	16		T55	10		T312	2
values[8]	431	1			T28	16		T55	6		T312	2
values[9]	391	1			T28	13		T55	3		T312	2
values[10]	318	1			T28	12		T55	1		T312	2
values[11]	315	1			T28	9		T55	4		T312	2
values[12]	291	1			T28	3		T55	3		T312	2
values[13]	291	1			T55	2		T312	2		T313	3
values[14]	299	1			T55	2		T312	2		T313	7
values[15]	300	1			T55	3		T312	2		T313	8
values[16]	323	1			T55	1		T312	2		T313	2
values[17]	292	1			T55	1		T312	2		T313	4
values[18]	254	1			T55	2		T312	2		T313	1
values[19]	283	1			T55	3		T312	2		T313	4
values[20]	249	1			T55	3		T312	2		T313	3
values[21]	249	1			T55	4		T312	2		T313	2
values[22]	229	1			T55	2		T312	2		T313	6
values[23]	279	1			T55	3		T312	2		T313	3
values[24]	270	1			T55	2		T312	2		T313	4
values[25]	265	1			T55	2		T312	2		T313	2
values[26]	238	1			T55	3		T312	2		T313	1
values[27]	230	1			T55	3		T312	2		T313	3
values[28]	256	1			T55	1		T312	2		T313	3
values[29]	252	1			T55	3		T312	2		T313	2
values[30]	238	1			T55	2		T312	2		T313	11
values[31]	249	1			T55	2		T312	2		T313	10
values[32]	275	1			T55	1		T312	2		T313	6
values[33]	258	1			T55	2		T312	3		T313	2
values[34]	201	1			T55	3		T312	2		T313	2
values[35]	230	1			T55	1		T312	2		T313	4
values[36]	233	1			T55	3		T312	2		T313	6
values[37]	228	1			T55	1		T312	2		T313	7
values[38]	232	1			T55	2		T312	2		T313	7
values[39]	274	1			T55	1		T312	2		T313	4
values[40]	235	1			T55	2		T312	2		T313	3
values[41]	257	1			T55	1		T312	2		T313	2
values[42]	254	1			T55	2		T312	2		T313	2
values[43]	316	1			T55	6		T312	2		T58	21
values[44]	223	1			T55	2		T312	2		T58	19
values[45]	216	1			T55	7		T312	2		T58	11
values[46]	208	1			T55	5		T312	2		T58	17
values[47]	240	1			T55	5		T312	2		T58	18
values[48]	253	1			T55	17		T312	2		T58	16
values[49]	236	1			T55	7		T312	2		T58	16
values[50]	231	1			T55	1		T312	2		T58	10
values[51]	242	1			T55	3		T312	2		T58	17
values[52]	230	1			T55	11		T312	2		T58	18
values[53]	194	1			T55	3		T312	2		T58	21
values[54]	216	1			T55	4		T312	2		T58	17
values[55]	213	1			T55	6		T312	2		T58	13
values[56]	199	1			T55	4		T312	2		T58	14
values[57]	190	1			T55	1		T312	2		T58	19
values[58]	196	1			T55	1		T312	2		T58	1
values[59]	187	1			T55	1		T312	2		T228	6
values[60]	173	1			T55	9		T312	2		T228	6
values[61]	205	1			T55	13		T312	2		T228	3
values[62]	172	1			T55	8		T312	2		T228	3
values[63]	159	1			T55	1		T312	2		T228	3
values[64]	153	1			T55	4		T312	2		T228	3
values[65]	126	1			T55	1		T312	2		T228	6
values[66]	116	1			T55	1		T312	2		T228	6
values[67]	112	1			T55	3		T312	2		T228	8
values[68]	91	1			T55	1		T312	2		T228	11
values[69]	102	1			T55	4		T312	4		T228	3
values[70]	86	1			T55	1		T312	2		T228	3
values[71]	94	1			T55	4		T312	2		T228	3
values[72]	106	1			T55	2		T312	2		T228	15
values[73]	74	1			T55	1		T312	2		T228	4
values[74]	75	1			T55	4		T312	2		T228	10
values[75]	47	1			T55	3		T312	2		T228	8
values[76]	58	1			T55	4		T312	2		T228	8
values[77]	41	1			T55	2		T312	2		T228	4
values[78]	40	1			T55	3		T312	2		T228	6
values[79]	43	1			T55	1		T312	2		T228	8
values[80]	42	1			T55	4		T312	2		T228	5
values[81]	56	1			T55	8		T312	2		T228	6
values[82]	48	1			T55	6		T312	2		T228	2
values[83]	54	1			T55	4		T312	2		T228	3
values[84]	67	1			T55	11		T312	2		T228	9
values[85]	58	1			T55	2		T312	2		T228	7
values[86]	51	1			T55	3		T312	2		T228	3
values[87]	48	1			T55	1		T312	2		T228	9
values[88]	65	1			T55	4		T312	2		T228	8
values[89]	66	1			T55	1		T312	2		T228	11
values[90]	74	1			T55	1		T312	2		T228	13
values[91]	61	1			T55	3		T312	2		T228	8
values[92]	57	1			T55	2		T312	2		T228	4
values[93]	78	1			T55	2		T312	2		T228	9
values[94]	82	1			T55	6		T312	2		T228	7
values[95]	79	1			T55	1		T312	2		T228	12
values[96]	94	1			T55	2		T312	3		T228	14
values[97]	84	1			T55	1		T312	3		T228	13
values[98]	81	1			T55	3		T312	5		T228	11
values[99]	98	1			T55	8		T312	6		T228	25
values[100]	90	1			T55	3		T312	3		T228	12
values[101]	70	1			T55	4		T312	3		T228	9
values[102]	66	1			T55	2		T312	2		T228	11
values[103]	87	1			T55	3		T312	3		T228	17
values[104]	84	1			T55	1		T312	2		T228	13
values[105]	69	1			T55	3		T312	2		T228	10
values[106]	68	1			T55	1		T312	5		T228	11
values[107]	65	1			T55	3		T312	2		T228	5
values[108]	65	1			T55	5		T312	9		T228	7
values[109]	62	1			T55	3		T312	5		T228	3
values[110]	66	1			T55	2		T312	2		T228	6
values[111]	66	1			T55	1		T312	5		T228	7
values[112]	71	1			T55	5		T312	4		T228	4
values[113]	81	1			T55	3		T312	3		T228	5
values[114]	54	1			T55	4		T312	2		T228	4
values[115]	89	1			T55	6		T312	3		T228	4
values[116]	79	1			T55	3		T312	2		T228	7
values[117]	59	1			T55	5		T312	3		T228	11
values[118]	80	1			T55	9		T312	2		T228	11
values[119]	57	1			T55	5		T312	2		T228	9
values[120]	57	1			T55	1		T312	2		T228	2
values[121]	66	1			T55	3		T312	2		T228	3
values[122]	54	1			T55	3		T312	2		T228	9
values[123]	62	1			T55	2		T312	2		T228	9
values[124]	68	1			T55	1		T312	4		T228	9
values[125]	79	1			T55	7		T312	5		T228	8
values[126]	147	1			T55	20		T312	7		T228	17
values[127]	927	1			T55	37		T312	63		T228	63
values[128]	7048	1			T55	23		T312	642		T228	36

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	156243	1			T11	183		T12	11		T13	28
values[2]	3347	1			T14	1		T28	2		T79	1
values[3]	1501	1			T80	1		T54	1		T202	1
values[4]	1083	1			T204	1		T82	1		T294	29
values[5]	860	1			T204	1		T82	1		T294	40
values[6]	730	1			T204	7		T82	1		T294	49
values[7]	671	1			T204	9		T82	1		T294	39
values[8]	625	1			T204	16		T82	1		T294	52
values[9]	529	1			T204	15		T82	1		T294	16
values[10]	554	1			T204	23		T82	1		T294	10
values[11]	540	1			T204	38		T82	1		T294	4
values[12]	534	1			T204	41		T82	1		T294	4
values[13]	479	1			T204	22		T82	1		T312	1
values[14]	426	1			T204	12		T82	1		T312	1
values[15]	368	1			T204	14		T82	1		T312	1
values[16]	346	1			T204	37		T82	1		T312	1
values[17]	306	1			T204	31		T82	1		T312	1
values[18]	383	1			T204	50		T82	1		T312	1
values[19]	401	1			T204	56		T82	1		T312	1
values[20]	381	1			T204	31		T82	1		T312	1
values[21]	315	1			T204	21		T82	1		T312	1
values[22]	301	1			T204	24		T82	1		T312	1
values[23]	212	1			T204	17		T82	1		T312	1
values[24]	145	1			T204	11		T82	1		T312	1
values[25]	108	1			T204	14		T82	1		T312	1
values[26]	111	1			T204	4		T82	1		T312	1
values[27]	98	1			T204	14		T82	1		T312	1
values[28]	102	1			T204	18		T82	1		T312	1
values[29]	107	1			T204	13		T82	1		T312	1
values[30]	109	1			T204	7		T82	1		T312	1
values[31]	102	1			T82	1		T312	1		T314	7
values[32]	81	1			T82	1		T312	1		T314	2
values[33]	79	1			T82	1		T312	1		T314	3
values[34]	89	1			T82	1		T312	1		T314	4
values[35]	84	1			T82	1		T312	1		T314	8
values[36]	79	1			T82	1		T312	1		T314	3
values[37]	83	1			T82	1		T312	1		T314	4
values[38]	93	1			T82	1		T312	1		T314	5
values[39]	87	1			T82	1		T312	1		T314	3
values[40]	100	1			T82	1		T312	1		T314	7
values[41]	77	1			T82	1		T312	1		T314	4
values[42]	74	1			T82	1		T312	1		T314	1
values[43]	67	1			T82	1		T312	1		T314	2
values[44]	71	1			T82	1		T312	1		T314	5
values[45]	68	1			T82	1		T312	1		T314	2
values[46]	65	1			T82	1		T312	1		T314	3
values[47]	57	1			T82	1		T312	1		T314	1
values[48]	60	1			T82	1		T312	1		T314	2
values[49]	77	1			T82	1		T312	1		T314	4
values[50]	69	1			T82	1		T312	1		T314	2
values[51]	65	1			T82	1		T312	1		T314	3
values[52]	53	1			T82	1		T312	1		T314	3
values[53]	52	1			T82	1		T312	1		T314	2
values[54]	54	1			T82	1		T312	1		T314	2
values[55]	55	1			T82	1		T312	1		T314	2
values[56]	56	1			T82	1		T312	1		T314	2
values[57]	44	1			T82	1		T312	1		T314	1
values[58]	51	1			T82	1		T312	1		T314	2
values[59]	51	1			T82	1		T312	1		T314	3
values[60]	70	1			T82	1		T312	1		T314	3
values[61]	63	1			T82	1		T312	1		T314	3
values[62]	49	1			T82	1		T312	1		T314	4
values[63]	49	1			T82	1		T312	1		T314	4
values[64]	50	1			T82	1		T312	1		T314	2
values[65]	48	1			T82	1		T312	1		T314	2
values[66]	53	1			T82	1		T312	1		T314	2
values[67]	48	1			T82	1		T312	1		T314	3
values[68]	48	1			T82	1		T312	1		T314	2
values[69]	52	1			T82	1		T312	1		T314	1
values[70]	53	1			T82	2		T312	1		T314	2
values[71]	53	1			T82	1		T312	1		T314	1
values[72]	50	1			T82	1		T312	1		T314	1
values[73]	45	1			T82	1		T312	1		T314	2
values[74]	47	1			T82	1		T312	1		T314	2
values[75]	49	1			T82	1		T312	1		T314	5
values[76]	55	1			T82	1		T312	1		T314	8
values[77]	65	1			T82	1		T312	2		T314	4
values[78]	70	1			T82	1		T312	1		T314	3
values[79]	78	1			T82	1		T312	1		T314	1
values[80]	61	1			T82	1		T312	1		T314	2
values[81]	67	1			T82	1		T312	1		T314	7
values[82]	51	1			T82	1		T312	1		T314	2
values[83]	52	1			T82	1		T312	1		T314	2
values[84]	64	1			T82	1		T312	1		T314	8
values[85]	56	1			T82	1		T312	1		T314	2
values[86]	60	1			T82	1		T312	1		T314	4
values[87]	62	1			T82	1		T312	1		T314	2
values[88]	73	1			T82	1		T312	1		T314	2
values[89]	74	1			T82	1		T312	1		T314	2
values[90]	65	1			T82	1		T312	1		T314	2
values[91]	65	1			T82	1		T312	1		T314	1
values[92]	87	1			T82	2		T312	1		T314	1
values[93]	75	1			T82	2		T312	1		T314	1
values[94]	87	1			T82	1		T312	1		T314	2
values[95]	75	1			T82	4		T312	1		T314	1
values[96]	89	1			T82	3		T312	1		T314	4
values[97]	87	1			T82	2		T312	1		T314	2
values[98]	75	1			T82	1		T312	1		T314	4
values[99]	74	1			T82	1		T312	1		T314	1
values[100]	78	1			T82	1		T312	1		T314	1
values[101]	79	1			T82	1		T312	1		T314	4
values[102]	97	1			T82	3		T312	1		T314	4
values[103]	93	1			T82	1		T312	1		T314	4
values[104]	97	1			T82	2		T312	1		T314	3
values[105]	97	1			T82	6		T312	1		T314	3
values[106]	101	1			T82	3		T312	1		T314	8
values[107]	111	1			T82	7		T312	3		T314	3
values[108]	96	1			T82	6		T312	4		T314	3
values[109]	154	1			T82	4		T312	6		T314	6
values[110]	108	1			T82	3		T312	2		T314	4
values[111]	110	1			T82	1		T312	2		T314	1
values[112]	94	1			T82	1		T312	1		T314	2
values[113]	99	1			T82	1		T312	2		T314	5
values[114]	83	1			T82	1		T312	2		T314	2
values[115]	88	1			T82	1		T312	3		T314	6
values[116]	91	1			T82	1		T312	4		T314	5
values[117]	90	1			T82	1		T312	2		T314	8
values[118]	91	1			T82	1		T312	1		T314	5
values[119]	88	1			T82	2		T312	2		T314	8
values[120]	81	1			T82	1		T312	2		T314	2
values[121]	85	1			T82	1		T312	2		T314	5
values[122]	100	1			T82	2		T312	1		T314	6
values[123]	156	1			T82	2		T312	2		T314	4
values[124]	161	1			T82	4		T312	1		T314	18
values[125]	289	1			T82	4		T312	3		T314	35
values[126]	569	1			T82	6		T312	8		T314	62
values[127]	2600	1			T82	122		T312	90		T314	49
values[128]	4606	1			T82	245		T312	174		T314	5

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143206	1			T11	458		T12	16		T13	16
values[2]	9096	1			T11	100		T28	145		T79	1
values[3]	3421	1			T11	6		T28	27		T53	22
values[4]	2089	1			T28	11		T53	16		T78	8
values[5]	1358	1			T28	1		T53	11		T78	21
values[6]	1003	1			T53	5		T78	4		T84	4
values[7]	735	1			T84	3		T204	2		T82	1
values[8]	493	1			T84	5		T204	3		T82	1
values[9]	450	1			T204	4		T82	1		T55	2
values[10]	397	1			T204	3		T82	1		T55	1
values[11]	326	1			T204	2		T82	1		T55	6
values[12]	337	1			T204	8		T82	1		T55	3
values[13]	298	1			T204	5		T82	1		T55	3
values[14]	280	1			T204	3		T82	1		T55	6
values[15]	336	1			T204	4		T82	1		T55	3
values[16]	310	1			T204	2		T82	1		T55	1
values[17]	288	1			T204	1		T82	1		T55	3
values[18]	304	1			T204	3		T82	1		T55	4
values[19]	282	1			T204	8		T82	1		T55	2
values[20]	304	1			T204	6		T82	1		T55	1
values[21]	292	1			T204	2		T82	1		T55	1
values[22]	314	1			T204	2		T82	1		T55	1
values[23]	318	1			T204	4		T82	1		T55	6
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