Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142400	1			T11	158		T12	13		T13	9
values[2]	9506	1			T14	99		T28	4		T79	1
values[3]	3761	1			T14	4		T78	8		T54	2
values[4]	2193	1			T78	8		T203	6		T63	38
values[5]	1321	1			T78	3		T203	6		T63	33
values[6]	869	1			T78	4		T63	41		T314	2
values[7]	661	1			T78	3		T63	41		T91	1
values[8]	539	1			T78	8		T63	38		T58	16
values[9]	410	1			T78	7		T63	28		T58	4
values[10]	347	1			T78	9		T63	12		T58	9
values[11]	283	1			T78	3		T58	7		T329	2
values[12]	334	1			T78	3		T58	11		T107	7
values[13]	321	1			T78	3		T58	12		T107	7
values[14]	342	1			T78	27		T58	12		T107	12
values[15]	260	1			T78	4		T58	11		T107	6
values[16]	260	1			T78	3		T58	4		T130	1
values[17]	227	1			T78	5		T58	8		T130	1
values[18]	272	1			T78	7		T58	3		T130	1
values[19]	341	1			T78	6		T58	8		T130	1
values[20]	288	1			T78	14		T58	8		T130	1
values[21]	279	1			T78	4		T58	4		T130	1
values[22]	269	1			T78	3		T58	8		T130	1
values[23]	221	1			T78	4		T58	5		T130	1
values[24]	286	1			T78	7		T58	15		T130	1
values[25]	266	1			T78	6		T58	6		T130	1
values[26]	235	1			T78	3		T58	9		T130	1
values[27]	264	1			T78	5		T58	13		T130	1
values[28]	312	1			T78	11		T58	20		T130	1
values[29]	234	1			T78	4		T58	11		T130	1
values[30]	312	1			T78	9		T58	4		T130	1
values[31]	280	1			T78	7		T58	6		T130	1
values[32]	287	1			T78	9		T58	4		T130	1
values[33]	282	1			T78	10		T58	5		T130	1
values[34]	324	1			T78	6		T58	7		T130	1
values[35]	329	1			T78	7		T58	3		T130	1
values[36]	310	1			T78	16		T58	8		T130	1
values[37]	223	1			T78	6		T58	5		T130	1
values[38]	254	1			T78	6		T58	4		T130	1
values[39]	263	1			T78	9		T58	4		T130	1
values[40]	284	1			T78	5		T58	16		T130	1
values[41]	252	1			T78	3		T58	8		T130	1
values[42]	244	1			T78	6		T58	6		T130	1
values[43]	277	1			T78	5		T58	10		T130	1
values[44]	224	1			T78	4		T58	6		T130	1
values[45]	236	1			T78	7		T58	10		T130	1
values[46]	267	1			T78	4		T58	10		T130	1
values[47]	230	1			T78	5		T58	6		T130	1
values[48]	269	1			T78	13		T58	16		T130	1
values[49]	269	1			T78	5		T58	12		T130	1
values[50]	280	1			T78	4		T58	18		T130	1
values[51]	287	1			T78	3		T58	7		T130	1
values[52]	258	1			T78	5		T58	12		T130	1
values[53]	214	1			T58	6		T130	1		T134	3
values[54]	212	1			T58	4		T130	1		T134	3
values[55]	215	1			T58	3		T130	1		T134	4
values[56]	205	1			T58	5		T130	1		T134	14
values[57]	196	1			T58	4		T130	1		T134	3
values[58]	188	1			T58	6		T130	1		T134	8
values[59]	185	1			T58	4		T130	1		T134	11
values[60]	205	1			T58	4		T130	1		T134	4
values[61]	191	1			T58	3		T130	1		T134	15
values[62]	174	1			T58	6		T130	1		T324	1
values[63]	150	1			T58	1		T130	1		T324	1
values[64]	166	1			T130	1		T324	1		T330	4
values[65]	191	1			T130	1		T324	1		T330	2
values[66]	160	1			T130	1		T324	1		T330	1
values[67]	181	1			T130	1		T324	1		T330	7
values[68]	147	1			T130	1		T324	1		T330	3
values[69]	178	1			T130	1		T324	2		T330	3
values[70]	155	1			T130	1		T324	1		T330	4
values[71]	120	1			T130	1		T324	1		T330	1
values[72]	99	1			T130	1		T324	1		T330	1
values[73]	70	1			T130	1		T324	1		T330	3
values[74]	61	1			T130	1		T324	1		T330	2
values[75]	90	1			T130	1		T324	1		T330	3
values[76]	78	1			T130	1		T324	1		T330	3
values[77]	66	1			T130	1		T324	1		T330	4
values[78]	70	1			T130	1		T324	1		T330	5
values[79]	68	1			T130	1		T324	1		T330	6
values[80]	75	1			T130	1		T324	1		T330	3
values[81]	82	1			T130	1		T324	1		T330	2
values[82]	86	1			T130	1		T324	1		T330	1
values[83]	80	1			T130	1		T324	1		T330	2
values[84]	72	1			T130	1		T324	1		T330	1
values[85]	77	1			T130	1		T324	1		T330	4
values[86]	73	1			T130	1		T324	1		T330	3
values[87]	53	1			T130	1		T324	1		T330	1
values[88]	53	1			T130	1		T324	1		T330	2
values[89]	57	1			T130	1		T324	1		T330	2
values[90]	53	1			T130	1		T324	1		T330	1
values[91]	70	1			T130	1		T324	1		T330	3
values[92]	81	1			T130	1		T324	1		T330	4
values[93]	93	1			T130	1		T324	1		T330	20
values[94]	75	1			T130	1		T324	1		T330	14
values[95]	57	1			T130	1		T324	1		T330	4
values[96]	63	1			T130	1		T324	1		T330	1
values[97]	58	1			T130	1		T324	1		T330	4
values[98]	56	1			T130	1		T324	1		T330	1
values[99]	70	1			T130	1		T324	1		T330	2
values[100]	62	1			T130	1		T324	1		T330	3
values[101]	58	1			T130	1		T324	1		T330	5
values[102]	68	1			T130	2		T324	1		T330	5
values[103]	57	1			T130	1		T324	1		T330	4
values[104]	60	1			T130	1		T324	1		T330	5
values[105]	76	1			T130	1		T324	1		T330	1
values[106]	60	1			T130	1		T324	1		T330	3
values[107]	56	1			T130	1		T324	1		T330	3
values[108]	61	1			T130	1		T324	1		T330	4
values[109]	63	1			T130	1		T324	1		T330	5
values[110]	63	1			T130	1		T324	1		T330	5
values[111]	56	1			T130	1		T324	1		T330	6
values[112]	63	1			T130	1		T324	1		T330	3
values[113]	55	1			T130	1		T324	1		T330	2
values[114]	60	1			T130	1		T324	1		T330	2
values[115]	78	1			T130	1		T324	1		T330	7
values[116]	56	1			T130	1		T324	1		T330	4
values[117]	60	1			T130	1		T324	1		T330	2
values[118]	59	1			T130	1		T324	1		T330	3
values[119]	52	1			T130	1		T324	1		T330	3
values[120]	48	1			T130	1		T324	1		T330	5
values[121]	59	1			T130	1		T324	1		T330	4
values[122]	59	1			T130	2		T324	8		T330	4
values[123]	54	1			T130	2		T324	1		T330	4
values[124]	49	1			T130	2		T324	2		T331	5
values[125]	62	1			T130	2		T324	3		T331	5
values[126]	101	1			T130	3		T324	4		T331	2
values[127]	645	1			T130	24		T324	21		T331	63
values[128]	5427	1			T130	270		T324	252		T331	653