Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	161945	1			T11	676		T12	7		T13	13
values[2]	3778	1			T14	1		T28	2		T53	28
values[3]	1763	1			T53	2		T147	1		T63	2
values[4]	1294	1			T63	3		T332	56		T91	46
values[5]	1158	1			T63	2		T332	36		T91	32
values[6]	1014	1			T63	3		T332	49		T91	32
values[7]	871	1			T63	2		T332	28		T91	42
values[8]	666	1			T63	1		T332	19		T91	29
values[9]	621	1			T63	2		T332	15		T91	27
values[10]	664	1			T63	4		T332	16		T91	21
values[11]	662	1			T63	1		T332	16		T91	17
values[12]	608	1			T63	1		T332	7		T91	7
values[13]	546	1			T63	2		T332	9		T91	4
values[14]	491	1			T63	1		T332	1		T91	2
values[15]	406	1			T63	3		T332	4		T98	22
values[16]	359	1			T63	2		T332	3		T98	4
values[17]	369	1			T63	1		T98	2		T316	1
values[18]	282	1			T63	2		T98	1		T316	1
values[19]	252	1			T63	3		T98	3		T316	1
values[20]	262	1			T63	4		T98	6		T316	1
values[21]	230	1			T63	2		T98	16		T316	1
values[22]	258	1			T63	3		T98	28		T316	1
values[23]	263	1			T63	2		T98	34		T316	1
values[24]	263	1			T63	4		T98	41		T316	1
values[25]	233	1			T63	12		T98	24		T316	1
values[26]	189	1			T63	3		T98	18		T316	1
values[27]	185	1			T63	1		T98	20		T316	1
values[28]	198	1			T63	2		T98	22		T316	1
values[29]	176	1			T63	3		T98	6		T316	1
values[30]	178	1			T63	6		T98	8		T316	1
values[31]	169	1			T63	4		T98	9		T316	1
values[32]	194	1			T63	2		T98	16		T316	1
values[33]	202	1			T63	2		T98	6		T316	1
values[34]	172	1			T63	1		T316	1		T321	1
values[35]	148	1			T63	4		T316	1		T321	3
values[36]	155	1			T63	8		T316	1		T321	2
values[37]	167	1			T63	4		T316	1		T321	3
values[38]	141	1			T63	1		T316	2		T321	2
values[39]	120	1			T63	5		T316	1		T321	5
values[40]	125	1			T63	4		T316	1		T321	1
values[41]	108	1			T63	2		T316	1		T321	4
values[42]	96	1			T63	1		T316	1		T321	2
values[43]	99	1			T63	3		T316	1		T321	3
values[44]	74	1			T63	1		T316	2		T321	1
values[45]	81	1			T63	3		T316	1		T321	1
values[46]	68	1			T63	1		T316	1		T321	3
values[47]	67	1			T63	2		T316	1		T321	3
values[48]	68	1			T63	1		T316	1		T321	2
values[49]	65	1			T63	1		T316	1		T321	3
values[50]	75	1			T63	3		T316	1		T321	3
values[51]	67	1			T63	1		T316	1		T321	1
values[52]	71	1			T63	1		T316	1		T321	1
values[53]	94	1			T63	1		T316	1		T321	2
values[54]	96	1			T63	3		T316	1		T321	2
values[55]	98	1			T63	5		T316	1		T321	2
values[56]	91	1			T63	4		T316	1		T321	3
values[57]	56	1			T63	2		T316	1		T321	2
values[58]	50	1			T63	2		T316	1		T321	2
values[59]	58	1			T63	2		T316	1		T321	5
values[60]	60	1			T63	2		T316	1		T321	2
values[61]	67	1			T63	1		T316	1		T321	9
values[62]	54	1			T63	2		T316	1		T321	1
values[63]	59	1			T63	5		T316	1		T321	4
values[64]	56	1			T63	2		T316	1		T321	4
values[65]	54	1			T63	1		T316	1		T321	2
values[66]	64	1			T63	3		T316	1		T321	2
values[67]	52	1			T63	4		T316	1		T321	2
values[68]	57	1			T63	1		T316	1		T321	1
values[69]	65	1			T63	2		T316	1		T321	2
values[70]	61	1			T63	5		T316	1		T321	5
values[71]	53	1			T63	2		T316	1		T321	1
values[72]	52	1			T63	1		T316	1		T321	1
values[73]	57	1			T63	1		T316	1		T321	4
values[74]	61	1			T63	2		T316	1		T321	5
values[75]	56	1			T63	2		T316	1		T321	5
values[76]	58	1			T63	3		T316	1		T321	1
values[77]	58	1			T63	1		T316	1		T321	1
values[78]	55	1			T63	1		T316	1		T321	1
values[79]	71	1			T63	2		T316	1		T321	2
values[80]	61	1			T63	1		T316	1		T321	2
values[81]	70	1			T63	1		T316	1		T321	2
values[82]	72	1			T63	2		T316	1		T321	9
values[83]	71	1			T63	1		T316	1		T321	1
values[84]	68	1			T63	1		T316	1		T321	4
values[85]	89	1			T63	2		T316	1		T321	5
values[86]	75	1			T63	1		T316	1		T321	3
values[87]	66	1			T63	3		T316	1		T321	3
values[88]	75	1			T63	3		T316	1		T321	2
values[89]	66	1			T63	2		T316	1		T321	2
values[90]	68	1			T63	2		T316	1		T321	2
values[91]	79	1			T63	3		T316	1		T321	1
values[92]	79	1			T63	4		T316	1		T321	3
values[93]	83	1			T63	1		T316	1		T321	4
values[94]	81	1			T63	2		T316	1		T321	4
values[95]	92	1			T63	3		T316	1		T321	8
values[96]	87	1			T63	1		T316	1		T321	4
values[97]	76	1			T63	3		T316	1		T321	2
values[98]	86	1			T63	4		T316	1		T321	3
values[99]	97	1			T63	3		T316	1		T321	9
values[100]	86	1			T63	9		T316	1		T321	5
values[101]	94	1			T63	5		T316	1		T321	2
values[102]	112	1			T63	7		T316	1		T321	3
values[103]	109	1			T63	1		T316	1		T321	1
values[104]	89	1			T63	1		T316	1		T321	1
values[105]	96	1			T63	1		T316	1		T321	3
values[106]	94	1			T63	2		T316	1		T321	3
values[107]	95	1			T63	3		T316	1		T321	2
values[108]	77	1			T63	1		T316	1		T321	1
values[109]	93	1			T63	7		T316	1		T321	3
values[110]	103	1			T63	4		T316	1		T321	1
values[111]	102	1			T63	6		T316	1		T321	3
values[112]	108	1			T63	3		T316	1		T321	1
values[113]	104	1			T63	4		T316	1		T321	5
values[114]	102	1			T63	2		T316	1		T321	5
values[115]	89	1			T63	1		T316	1		T321	6
values[116]	101	1			T63	4		T316	1		T321	4
values[117]	110	1			T63	6		T316	1		T321	7
values[118]	126	1			T63	12		T316	1		T321	11
values[119]	122	1			T63	8		T316	1		T321	2
values[120]	100	1			T63	5		T316	1		T321	2
values[121]	98	1			T63	2		T316	1		T321	5
values[122]	96	1			T63	5		T316	1		T321	5
values[123]	128	1			T63	5		T316	2		T321	7
values[124]	197	1			T63	4		T316	2		T321	12
values[125]	428	1			T63	14		T316	3		T321	38
values[126]	927	1			T63	24		T316	12		T321	28
values[127]	3429	1			T63	11		T316	112		T321	11
values[128]	6270	1			T316	283		T321	1		T130	203