Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	159980	1			T11	198		T12	16		T13	21
values[2]	4410	1			T53	2		T81	5		T80	4
values[3]	2073	1			T64	1		T322	1		T294	1
values[4]	1545	1			T64	1		T322	1		T314	32
values[5]	1270	1			T64	3		T322	1		T314	23
values[6]	1001	1			T64	2		T322	1		T314	18
values[7]	806	1			T64	1		T322	1		T314	14
values[8]	815	1			T64	3		T322	1		T314	15
values[9]	733	1			T64	1		T322	1		T314	33
values[10]	623	1			T64	1		T322	1		T314	25
values[11]	518	1			T64	2		T322	1		T314	30
values[12]	512	1			T64	2		T322	1		T314	27
values[13]	485	1			T64	1		T322	1		T314	22
values[14]	466	1			T64	2		T322	1		T314	45
values[15]	383	1			T64	5		T322	1		T314	32
values[16]	348	1			T64	4		T322	1		T314	54
values[17]	328	1			T64	7		T322	1		T314	43
values[18]	328	1			T64	3		T322	1		T314	37
values[19]	275	1			T64	2		T322	1		T314	12
values[20]	275	1			T64	6		T322	1		T314	17
values[21]	231	1			T64	1		T322	1		T314	3
values[22]	263	1			T64	2		T322	1		T91	3
values[23]	206	1			T64	3		T322	1		T91	5
values[24]	178	1			T64	2		T322	1		T91	6
values[25]	164	1			T64	1		T322	1		T91	9
values[26]	182	1			T64	2		T322	1		T91	12
values[27]	147	1			T64	2		T322	1		T91	10
values[28]	138	1			T64	5		T322	1		T91	6
values[29]	155	1			T64	9		T322	1		T91	3
values[30]	200	1			T64	8		T322	1		T91	4
values[31]	189	1			T64	4		T322	1		T91	8
values[32]	210	1			T64	4		T322	1		T91	6
values[33]	180	1			T64	1		T322	1		T91	9
values[34]	151	1			T64	3		T322	1		T91	10
values[35]	142	1			T64	2		T322	1		T91	3
values[36]	135	1			T64	7		T322	1		T91	2
values[37]	141	1			T64	7		T322	1		T91	2
values[38]	118	1			T64	3		T322	1		T91	6
values[39]	124	1			T64	2		T322	1		T91	6
values[40]	123	1			T64	5		T322	1		T91	5
values[41]	101	1			T64	2		T322	1		T91	4
values[42]	101	1			T64	2		T322	1		T91	5
values[43]	94	1			T64	1		T322	1		T91	6
values[44]	97	1			T64	1		T322	1		T91	7
values[45]	86	1			T64	4		T322	1		T91	5
values[46]	69	1			T64	4		T322	1		T91	4
values[47]	69	1			T64	3		T322	1		T91	4
values[48]	71	1			T64	3		T322	1		T91	5
values[49]	70	1			T64	1		T322	1		T91	6
values[50]	62	1			T64	2		T322	1		T91	5
values[51]	76	1			T64	2		T322	1		T91	9
values[52]	63	1			T64	1		T322	1		T91	2
values[53]	57	1			T64	6		T322	1		T91	2
values[54]	54	1			T64	2		T322	1		T91	3
values[55]	58	1			T64	2		T322	1		T91	6
values[56]	73	1			T64	5		T322	1		T91	7
values[57]	64	1			T64	1		T322	1		T91	11
values[58]	69	1			T64	2		T322	1		T91	6
values[59]	70	1			T64	3		T322	1		T91	10
values[60]	60	1			T64	1		T322	1		T91	4
values[61]	71	1			T64	4		T322	1		T91	4
values[62]	63	1			T64	6		T322	1		T91	3
values[63]	69	1			T64	2		T322	1		T91	2
values[64]	56	1			T64	1		T322	1		T91	4
values[65]	66	1			T64	4		T322	1		T91	5
values[66]	60	1			T64	3		T322	1		T91	4
values[67]	65	1			T64	2		T322	1		T91	2
values[68]	62	1			T64	3		T322	1		T91	6
values[69]	70	1			T64	1		T322	1		T91	5
values[70]	70	1			T64	3		T322	1		T91	7
values[71]	73	1			T64	5		T322	1		T91	5
values[72]	92	1			T64	3		T322	1		T91	7
values[73]	79	1			T64	1		T322	1		T91	6
values[74]	62	1			T64	1		T322	1		T91	6
values[75]	63	1			T64	3		T322	1		T91	2
values[76]	82	1			T64	1		T322	1		T91	3
values[77]	84	1			T64	4		T322	1		T91	3
values[78]	88	1			T64	2		T322	1		T91	2
values[79]	81	1			T64	2		T322	2		T91	5
values[80]	87	1			T64	2		T322	2		T91	3
values[81]	93	1			T64	1		T322	1		T91	5
values[82]	97	1			T64	1		T322	7		T91	3
values[83]	108	1			T64	2		T322	7		T91	3
values[84]	85	1			T64	1		T322	6		T91	4
values[85]	79	1			T64	1		T322	1		T91	8
values[86]	91	1			T64	6		T322	1		T91	4
values[87]	95	1			T64	3		T322	1		T91	5
values[88]	100	1			T64	4		T322	2		T91	5
values[89]	119	1			T64	4		T322	1		T91	8
values[90]	97	1			T64	3		T322	1		T91	11
values[91]	92	1			T64	2		T322	3		T91	11
values[92]	114	1			T64	4		T322	4		T91	11
values[93]	106	1			T64	3		T322	3		T91	12
values[94]	115	1			T64	1		T322	14		T91	8
values[95]	117	1			T64	2		T322	5		T91	8
values[96]	118	1			T64	1		T322	2		T91	5
values[97]	116	1			T64	1		T322	3		T91	10
values[98]	103	1			T64	2		T322	4		T91	3
values[99]	108	1			T64	3		T322	3		T91	5
values[100]	110	1			T64	1		T322	2		T91	5
values[101]	109	1			T64	2		T322	1		T91	6
values[102]	111	1			T64	4		T322	5		T91	12
values[103]	104	1			T64	3		T322	4		T91	6
values[104]	103	1			T64	3		T322	2		T91	5
values[105]	124	1			T64	4		T322	4		T91	10
values[106]	115	1			T64	1		T322	5		T91	9
values[107]	103	1			T64	1		T322	1		T91	5
values[108]	102	1			T64	2		T322	1		T91	3
values[109]	109	1			T64	4		T322	4		T91	3
values[110]	128	1			T64	3		T322	3		T91	4
values[111]	133	1			T64	9		T322	4		T91	6
values[112]	118	1			T64	3		T322	4		T91	5
values[113]	96	1			T64	2		T322	1		T91	2
values[114]	107	1			T322	5		T91	6		T228	5
values[115]	110	1			T322	3		T91	5		T228	6
values[116]	122	1			T322	2		T91	18		T228	6
values[117]	128	1			T322	1		T91	16		T228	8
values[118]	119	1			T322	1		T91	20		T228	9
values[119]	114	1			T322	3		T91	5		T228	5
values[120]	115	1			T322	5		T91	9		T228	6
values[121]	90	1			T322	2		T91	13		T228	5
values[122]	130	1			T322	1		T91	14		T228	6
values[123]	154	1			T322	1		T91	11		T228	7
values[124]	212	1			T322	3		T91	22		T228	10
values[125]	392	1			T322	3		T91	40		T228	26
values[126]	833	1			T322	9		T91	87		T228	35
values[127]	3141	1			T322	88		T91	39		T228	10
values[128]	5743	1			T322	182		T91	2		T228	3