Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	158560	1			T11	193		T12	16		T13	15
values[2]	3678	1			T28	7		T79	1		T53	117
values[3]	1784	1			T28	9		T53	98		T200	6
values[4]	1261	1			T28	21		T53	55		T200	13
values[5]	979	1			T28	20		T53	42		T200	9
values[6]	806	1			T28	16		T53	43		T200	16
values[7]	660	1			T28	8		T53	30		T200	41
values[8]	529	1			T28	8		T53	21		T200	41
values[9]	422	1			T28	4		T53	29		T200	19
values[10]	381	1			T28	3		T53	46		T200	12
values[11]	421	1			T28	1		T53	21		T200	13
values[12]	402	1			T28	6		T53	48		T200	6
values[13]	393	1			T28	2		T53	29		T200	9
values[14]	319	1			T28	2		T53	14		T200	12
values[15]	229	1			T28	4		T200	14		T82	1
values[16]	200	1			T28	1		T200	23		T82	1
values[17]	170	1			T28	10		T200	8		T82	1
values[18]	197	1			T28	26		T200	6		T82	1
values[19]	198	1			T28	13		T200	9		T82	1
values[20]	240	1			T28	19		T200	21		T82	1
values[21]	236	1			T28	11		T200	8		T82	1
values[22]	174	1			T28	8		T200	6		T82	1
values[23]	154	1			T28	4		T200	9		T82	1
values[24]	143	1			T28	5		T200	8		T82	1
values[25]	129	1			T28	11		T200	3		T82	1
values[26]	145	1			T28	4		T200	3		T82	1
values[27]	118	1			T28	2		T200	3		T82	1
values[28]	136	1			T28	7		T200	6		T82	1
values[29]	136	1			T28	11		T200	12		T82	1
values[30]	101	1			T28	11		T200	9		T82	1
values[31]	106	1			T28	11		T200	3		T82	1
values[32]	116	1			T28	11		T200	13		T82	1
values[33]	110	1			T28	6		T200	17		T82	1
values[34]	118	1			T28	7		T200	13		T82	1
values[35]	149	1			T28	2		T200	15		T82	1
values[36]	150	1			T28	2		T200	32		T82	1
values[37]	135	1			T28	3		T200	14		T82	1
values[38]	105	1			T28	5		T200	2		T82	1
values[39]	78	1			T28	1		T82	1		T91	1
values[40]	85	1			T28	4		T82	1		T91	1
values[41]	85	1			T28	7		T82	1		T91	5
values[42]	83	1			T28	8		T82	1		T91	3
values[43]	78	1			T28	12		T82	1		T91	5
values[44]	72	1			T28	6		T82	1		T91	3
values[45]	71	1			T28	8		T82	1		T91	3
values[46]	73	1			T28	9		T82	1		T91	1
values[47]	70	1			T28	7		T82	1		T91	1
values[48]	77	1			T28	15		T82	1		T91	2
values[49]	74	1			T28	19		T82	1		T91	2
values[50]	79	1			T28	26		T82	1		T91	4
values[51]	92	1			T28	22		T82	1		T91	5
values[52]	71	1			T28	9		T82	1		T91	1
values[53]	63	1			T28	4		T82	1		T91	1
values[54]	56	1			T82	1		T91	4		T325	1
values[55]	51	1			T82	1		T91	1		T325	1
values[56]	62	1			T82	1		T91	1		T325	1
values[57]	61	1			T82	1		T91	7		T325	1
values[58]	59	1			T82	1		T91	6		T325	1
values[59]	51	1			T82	1		T91	4		T325	1
values[60]	53	1			T82	1		T91	1		T325	1
values[61]	52	1			T82	1		T91	1		T325	1
values[62]	58	1			T82	1		T91	1		T325	1
values[63]	68	1			T82	1		T91	5		T325	1
values[64]	50	1			T82	1		T91	1		T325	1
values[65]	55	1			T82	1		T91	1		T325	1
values[66]	51	1			T82	1		T91	3		T325	1
values[67]	66	1			T82	1		T91	3		T325	1
values[68]	68	1			T82	1		T91	1		T325	1
values[69]	61	1			T82	1		T91	3		T325	1
values[70]	59	1			T82	1		T91	4		T325	1
values[71]	67	1			T82	1		T91	3		T325	1
values[72]	48	1			T82	1		T91	2		T325	1
values[73]	52	1			T82	1		T91	5		T325	1
values[74]	69	1			T82	1		T91	4		T325	1
values[75]	60	1			T82	1		T91	10		T325	1
values[76]	73	1			T82	1		T91	3		T325	1
values[77]	76	1			T82	1		T91	2		T325	1
values[78]	83	1			T82	1		T91	2		T325	1
values[79]	76	1			T82	1		T91	4		T325	1
values[80]	66	1			T82	1		T91	1		T325	1
values[81]	67	1			T82	1		T91	2		T325	1
values[82]	68	1			T82	1		T91	1		T325	1
values[83]	69	1			T82	1		T91	2		T325	1
values[84]	62	1			T82	1		T91	4		T325	1
values[85]	78	1			T82	1		T91	2		T325	1
values[86]	72	1			T82	1		T91	3		T325	1
values[87]	64	1			T82	1		T91	2		T325	1
values[88]	75	1			T82	1		T91	4		T325	1
values[89]	74	1			T82	1		T91	3		T325	1
values[90]	62	1			T82	1		T91	5		T325	1
values[91]	80	1			T82	1		T91	2		T325	1
values[92]	80	1			T82	1		T91	4		T325	1
values[93]	69	1			T82	1		T91	5		T325	1
values[94]	69	1			T82	1		T91	3		T325	1
values[95]	77	1			T82	1		T91	5		T325	1
values[96]	79	1			T82	1		T91	10		T325	1
values[97]	73	1			T82	1		T91	4		T325	1
values[98]	86	1			T82	1		T91	2		T325	1
values[99]	82	1			T82	1		T91	3		T325	1
values[100]	77	1			T82	1		T91	1		T325	1
values[101]	88	1			T82	1		T91	3		T325	1
values[102]	112	1			T82	1		T91	10		T325	1
values[103]	91	1			T82	1		T91	1		T325	1
values[104]	76	1			T82	1		T91	1		T325	1
values[105]	87	1			T82	1		T91	3		T325	1
values[106]	76	1			T82	1		T91	2		T325	1
values[107]	109	1			T82	1		T91	1		T325	1
values[108]	99	1			T82	1		T91	3		T325	1
values[109]	84	1			T82	1		T91	1		T325	1
values[110]	83	1			T82	1		T91	4		T325	1
values[111]	101	1			T82	1		T91	6		T325	1
values[112]	120	1			T82	1		T91	2		T325	1
values[113]	100	1			T82	1		T91	2		T325	1
values[114]	104	1			T82	1		T91	3		T325	1
values[115]	121	1			T82	1		T91	5		T325	1
values[116]	139	1			T82	1		T91	6		T325	1
values[117]	117	1			T82	1		T91	9		T325	1
values[118]	108	1			T82	1		T91	12		T325	1
values[119]	128	1			T82	2		T91	5		T325	1
values[120]	108	1			T82	2		T91	12		T325	1
values[121]	104	1			T82	1		T91	12		T325	1
values[122]	102	1			T82	2		T91	6		T325	1
values[123]	123	1			T82	5		T91	11		T325	1
values[124]	183	1			T82	1		T91	9		T325	2
values[125]	355	1			T82	3		T91	20		T325	1
values[126]	776	1			T82	8		T91	49		T325	12
values[127]	2981	1			T82	103		T91	41		T325	104
values[128]	5484	1			T82	230		T91	4		T325	199