Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	464	1			T53	4		T78	3		T64	3
all_values[1]	458	1			T28	2		T53	3		T200	1
all_values[2]	461	1			T28	1		T200	1		T78	1
all_values[3]	465	1			T14	1		T28	2		T53	2
all_values[4]	427	1			T78	3		T64	4		T68	1
all_values[5]	452	1			T14	4		T28	1		T53	1
all_values[6]	472	1			T11	1		T14	1		T28	2
all_values[7]	458	1			T11	1		T53	5		T78	6
all_values[8]	456	1			T28	1		T53	2		T78	5
all_values[9]	455	1			T28	2		T53	6		T200	1
all_values[10]	469	1			T14	3		T28	2		T53	3
all_values[11]	430	1			T14	1		T28	2		T53	6
all_values[12]	450	1			T53	2		T78	5		T64	7
all_values[13]	462	1			T28	3		T78	4		T64	2
all_values[14]	462	1			T53	3		T64	1		T84	1
all_values[15]	464	1			T28	3		T53	2		T78	1
all_values[16]	462	1			T28	3		T53	4		T200	1
all_values[17]	438	1			T11	1		T14	2		T53	3
all_values[18]	445	1			T14	1		T28	1		T53	3
all_values[19]	482	1			T11	1		T28	1		T53	2
all_values[20]	467	1			T11	1		T53	6		T78	4
all_values[21]	453	1			T28	2		T53	2		T78	1
all_values[22]	431	1			T14	1		T28	1		T53	1
all_values[23]	468	1			T11	1		T14	1		T28	1
all_values[24]	476	1			T28	1		T53	3		T78	4
all_values[25]	442	1			T53	1		T78	3		T64	2
all_values[26]	480	1			T14	1		T28	1		T53	2
all_values[27]	472	1			T28	2		T53	3		T200	1
all_values[28]	479	1			T14	3		T28	1		T53	1
all_values[29]	447	1			T14	2		T78	3		T64	1
all_values[30]	505	1			T11	1		T14	1		T28	3
all_values[31]	418	1			T11	2		T78	1		T64	4
all_values[32]	472	1			T14	2		T28	4		T53	5
all_values[33]	473	1			T14	1		T53	2		T78	3
all_values[34]	441	1			T11	1		T14	1		T28	1
all_values[35]	441	1			T14	1		T28	1		T53	2
all_values[36]	416	1			T11	1		T14	2		T28	2
all_values[37]	494	1			T14	2		T28	3		T53	2
all_values[38]	439	1			T28	1		T53	4		T78	3
all_values[39]	453	1			T14	1		T28	1		T53	4
all_values[40]	455	1			T14	2		T53	4		T64	4
all_values[41]	420	1			T14	3		T28	4		T53	1
all_values[42]	479	1			T53	2		T78	1		T64	5
all_values[43]	495	1			T11	1		T28	2		T53	4
all_values[44]	471	1			T14	1		T53	2		T78	3
all_values[45]	441	1			T14	2		T28	1		T53	6
all_values[46]	447	1			T28	1		T53	1		T78	5
all_values[47]	454	1			T28	4		T53	6		T78	2
all_values[48]	464	1			T28	2		T53	3		T78	4
all_values[49]	459	1			T11	1		T14	1		T28	3