Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3662	1			T11	2		T14	10		T28	24
all_values[1]	3615	1			T11	7		T14	16		T28	9
all_values[2]	3645	1			T11	6		T14	19		T28	10
all_values[3]	3657	1			T11	11		T14	12		T28	14
all_values[4]	3702	1			T11	9		T14	18		T28	14
all_values[5]	3623	1			T11	5		T14	11		T28	13
all_values[6]	3666	1			T11	12		T14	12		T28	15
all_values[7]	3654	1			T11	4		T14	14		T28	12
all_values[8]	3665	1			T11	5		T14	13		T28	12
all_values[9]	3598	1			T11	5		T14	15		T28	13
all_values[10]	3543	1			T11	1		T14	28		T28	12
all_values[11]	3676	1			T11	3		T14	17		T28	23
all_values[12]	3641	1			T11	6		T14	16		T28	15
all_values[13]	3659	1			T11	4		T14	12		T28	19
all_values[14]	3803	1			T11	4		T14	20		T28	11
all_values[15]	3750	1			T11	9		T14	13		T28	11
all_values[16]	3703	1			T11	4		T14	20		T28	12
all_values[17]	3503	1			T11	5		T14	16		T28	13
all_values[18]	3699	1			T11	3		T14	14		T28	17
all_values[19]	3616	1			T11	4		T14	17		T28	17
all_values[20]	3758	1			T11	5		T14	12		T28	16
all_values[21]	3618	1			T11	7		T14	14		T28	22
all_values[22]	3661	1			T11	5		T14	20		T28	12
all_values[23]	3667	1			T11	2		T14	14		T28	16
all_values[24]	3684	1			T11	2		T14	15		T28	13
all_values[25]	3545	1			T11	4		T14	17		T28	7
all_values[26]	3657	1			T11	9		T14	18		T28	14
all_values[27]	3507	1			T11	4		T14	21		T28	10
all_values[28]	3539	1			T11	11		T14	14		T28	12
all_values[29]	3661	1			T11	3		T14	11		T28	10
all_values[30]	3689	1			T11	8		T14	25		T28	19
all_values[31]	3705	1			T11	6		T14	18		T28	12
all_values[32]	3626	1			T11	7		T14	14		T28	11
all_values[33]	3615	1			T11	5		T14	14		T28	12
all_values[34]	3629	1			T11	11		T14	10		T28	12
all_values[35]	3610	1			T11	7		T14	18		T28	9
all_values[36]	3728	1			T11	4		T14	13		T28	9
all_values[37]	3730	1			T11	6		T14	18		T28	15
all_values[38]	3631	1			T11	5		T14	13		T28	16
all_values[39]	3837	1			T11	4		T14	23		T28	22
all_values[40]	3662	1			T11	6		T14	12		T28	9
all_values[41]	3633	1			T11	8		T14	14		T28	12
all_values[42]	3652	1			T11	4		T14	13		T28	18
all_values[43]	3600	1			T11	2		T14	13		T28	10
all_values[44]	3732	1			T11	4		T14	23		T28	17
all_values[45]	3561	1			T11	5		T14	12		T28	12
all_values[46]	3593	1			T11	9		T14	18		T28	8
all_values[47]	3648	1			T11	3		T14	24		T28	9
all_values[48]	3715	1			T11	8		T14	15		T28	12
all_values[49]	3638	1			T11	11		T14	17		T28	11
all_values[50]	3574	1			T11	2		T14	19		T28	11
all_values[51]	3763	1			T11	4		T14	16		T28	16
all_values[52]	3744	1			T11	10		T14	14		T28	12
all_values[53]	3593	1			T11	6		T14	15		T28	14
all_values[54]	3736	1			T11	4		T14	25		T28	12
all_values[55]	3692	1			T11	5		T14	19		T28	12
all_values[56]	3641	1			T11	1		T14	30		T28	15
all_values[57]	3722	1			T11	7		T14	21		T28	12
all_values[58]	3662	1			T11	1		T14	16		T28	18
all_values[59]	3705	1			T11	6		T14	16		T28	12
all_values[60]	3687	1			T11	3		T14	18		T28	17
all_values[61]	3627	1			T11	7		T14	17		T28	18
all_values[62]	3628	1			T11	8		T14	17		T28	13
all_values[63]	3629	1			T11	4		T14	23		T28	19