Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	137046	1			T5	35		T6	91		T7	48
values[2]	9095	1			T5	15		T6	1		T7	2
values[3]	3347	1			T5	7		T249	1		T147	1
values[4]	1978	1			T5	3		T249	1		T147	1
values[5]	1230	1			T5	3		T249	1		T251	44
values[6]	905	1			T5	1		T249	1		T251	36
values[7]	693	1			T249	1		T251	15		T296	7
values[8]	489	1			T249	1		T251	2		T296	7
values[9]	420	1			T249	1		T296	3		T339	1
values[10]	349	1			T249	1		T296	2		T339	1
values[11]	294	1			T249	1		T339	1		T72	1
values[12]	287	1			T249	1		T339	1		T72	1
values[13]	288	1			T249	1		T339	1		T72	1
values[14]	300	1			T249	1		T339	1		T72	1
values[15]	269	1			T249	1		T339	1		T72	1
values[16]	247	1			T249	1		T339	1		T72	1
values[17]	261	1			T249	1		T339	1		T72	1
values[18]	266	1			T249	1		T339	1		T72	1
values[19]	303	1			T249	1		T339	1		T72	1
values[20]	244	1			T249	1		T339	1		T72	1
values[21]	225	1			T249	1		T339	1		T72	1
values[22]	270	1			T249	1		T339	1		T72	1
values[23]	229	1			T249	1		T339	1		T72	1
values[24]	226	1			T249	1		T339	1		T72	1
values[25]	259	1			T249	1		T339	1		T72	1
values[26]	255	1			T249	1		T339	1		T72	1
values[27]	318	1			T249	1		T339	1		T72	1
values[28]	276	1			T249	1		T339	1		T72	1
values[29]	232	1			T249	1		T339	1		T72	1
values[30]	258	1			T249	1		T339	1		T72	1
values[31]	252	1			T249	1		T339	1		T72	1
values[32]	252	1			T249	1		T339	1		T72	1
values[33]	243	1			T249	1		T339	1		T72	1
values[34]	255	1			T249	1		T339	1		T72	1
values[35]	237	1			T249	1		T339	1		T72	1
values[36]	236	1			T249	1		T339	1		T72	1
values[37]	236	1			T249	1		T339	1		T72	1
values[38]	203	1			T249	1		T339	1		T72	1
values[39]	213	1			T249	1		T339	1		T72	1
values[40]	224	1			T249	1		T339	1		T72	1
values[41]	234	1			T249	1		T339	1		T72	1
values[42]	227	1			T249	1		T339	1		T72	1
values[43]	223	1			T249	1		T339	1		T72	1
values[44]	276	1			T249	1		T339	1		T72	1
values[45]	223	1			T249	1		T339	1		T72	1
values[46]	283	1			T249	1		T339	1		T72	1
values[47]	203	1			T249	1		T339	1		T72	1
values[48]	217	1			T249	1		T339	1		T72	1
values[49]	198	1			T249	1		T339	1		T72	1
values[50]	191	1			T249	1		T339	1		T72	1
values[51]	185	1			T249	1		T339	1		T72	1
values[52]	212	1			T249	1		T339	1		T72	1
values[53]	232	1			T249	1		T339	1		T72	1
values[54]	200	1			T249	1		T339	1		T72	1
values[55]	261	1			T249	1		T339	1		T72	1
values[56]	207	1			T249	1		T339	1		T72	1
values[57]	176	1			T249	1		T339	1		T72	1
values[58]	199	1			T249	1		T339	1		T72	1
values[59]	169	1			T249	1		T339	1		T72	1
values[60]	185	1			T249	1		T339	1		T72	1
values[61]	167	1			T249	1		T339	1		T72	1
values[62]	155	1			T249	1		T339	1		T72	1
values[63]	157	1			T249	1		T339	1		T72	1
values[64]	177	1			T249	1		T339	1		T72	1
values[65]	158	1			T249	1		T339	1		T72	1
values[66]	165	1			T249	1		T339	1		T72	1
values[67]	120	1			T249	1		T339	1		T72	1
values[68]	94	1			T249	1		T339	1		T72	1
values[69]	68	1			T249	1		T339	1		T72	1
values[70]	97	1			T249	1		T339	1		T72	1
values[71]	73	1			T249	1		T339	1		T72	1
values[72]	65	1			T249	1		T339	1		T72	1
values[73]	75	1			T249	1		T339	1		T72	1
values[74]	75	1			T249	1		T339	1		T72	1
values[75]	96	1			T249	1		T339	1		T72	1
values[76]	88	1			T249	1		T339	1		T72	1
values[77]	94	1			T249	1		T339	1		T72	1
values[78]	79	1			T249	1		T339	1		T72	1
values[79]	83	1			T249	1		T339	1		T72	1
values[80]	81	1			T249	1		T339	1		T72	1
values[81]	66	1			T249	1		T339	1		T72	1
values[82]	59	1			T249	2		T339	1		T72	1
values[83]	71	1			T249	9		T339	1		T72	1
values[84]	85	1			T249	4		T339	1		T72	1
values[85]	80	1			T249	14		T339	1		T72	1
values[86]	78	1			T249	4		T339	1		T72	1
values[87]	75	1			T249	7		T339	1		T72	1
values[88]	76	1			T249	2		T339	1		T72	1
values[89]	65	1			T249	1		T339	1		T72	1
values[90]	75	1			T249	2		T339	1		T72	1
values[91]	77	1			T249	8		T339	1		T72	1
values[92]	64	1			T249	1		T339	1		T72	1
values[93]	73	1			T249	2		T339	1		T72	1
values[94]	66	1			T249	1		T339	1		T72	1
values[95]	70	1			T249	2		T339	1		T72	1
values[96]	62	1			T249	2		T339	1		T72	1
values[97]	53	1			T249	2		T339	1		T72	1
values[98]	76	1			T249	2		T339	1		T72	1
values[99]	63	1			T249	7		T339	1		T72	1
values[100]	65	1			T249	1		T339	1		T72	1
values[101]	74	1			T249	3		T339	2		T72	1
values[102]	56	1			T249	2		T339	1		T72	1
values[103]	64	1			T249	2		T339	1		T72	1
values[104]	64	1			T249	3		T339	1		T72	1
values[105]	63	1			T249	3		T339	1		T72	2
values[106]	55	1			T249	2		T339	1		T72	1
values[107]	51	1			T249	1		T339	1		T72	1
values[108]	79	1			T249	1		T339	1		T72	1
values[109]	55	1			T249	3		T339	1		T72	1
values[110]	59	1			T249	6		T339	1		T72	1
values[111]	64	1			T249	2		T339	1		T72	1
values[112]	78	1			T249	6		T339	1		T72	1
values[113]	70	1			T249	4		T339	1		T72	1
values[114]	68	1			T249	2		T339	1		T72	1
values[115]	75	1			T249	8		T339	1		T72	1
values[116]	80	1			T249	2		T339	1		T72	1
values[117]	62	1			T249	1		T339	1		T72	2
values[118]	61	1			T249	3		T339	1		T72	3
values[119]	67	1			T249	2		T339	1		T72	3
values[120]	77	1			T249	1		T339	1		T72	3
values[121]	84	1			T249	1		T339	1		T72	2
values[122]	46	1			T249	1		T339	1		T72	2
values[123]	54	1			T249	2		T339	1		T72	5
values[124]	69	1			T249	2		T339	1		T72	3
values[125]	61	1			T249	3		T339	1		T72	2
values[126]	86	1			T249	1		T339	1		T72	4
values[127]	811	1			T249	21		T339	35		T72	24
values[128]	7078	1			T249	228		T339	418		T72	312