Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	135375	1			T5	15		T6	71		T7	51
values[2]	7088	1			T6	4		T7	3		T18	1
values[3]	3203	1			T125	1		T336	1		T243	1
values[4]	2081	1			T336	1		T243	1		T339	1
values[5]	1422	1			T336	1		T243	1		T339	1
values[6]	995	1			T336	1		T243	1		T339	1
values[7]	863	1			T336	1		T243	1		T339	1
values[8]	681	1			T336	1		T243	1		T339	1
values[9]	629	1			T336	1		T243	1		T339	1
values[10]	535	1			T336	1		T243	1		T339	1
values[11]	494	1			T336	1		T243	1		T339	1
values[12]	487	1			T336	1		T243	1		T339	1
values[13]	558	1			T336	1		T243	1		T339	1
values[14]	490	1			T336	1		T243	1		T339	1
values[15]	431	1			T336	1		T243	2		T339	1
values[16]	415	1			T336	1		T243	1		T339	1
values[17]	433	1			T336	1		T243	1		T339	1
values[18]	468	1			T336	1		T243	1		T339	1
values[19]	426	1			T336	1		T243	1		T339	1
values[20]	457	1			T336	1		T243	1		T339	1
values[21]	387	1			T336	1		T243	1		T339	1
values[22]	386	1			T336	1		T243	1		T339	1
values[23]	392	1			T336	1		T243	1		T339	1
values[24]	478	1			T336	1		T243	1		T339	1
values[25]	355	1			T336	1		T243	1		T339	1
values[26]	364	1			T336	1		T243	1		T339	1
values[27]	403	1			T336	1		T243	1		T339	1
values[28]	417	1			T336	1		T243	1		T339	1
values[29]	436	1			T336	1		T243	1		T339	1
values[30]	367	1			T336	1		T243	1		T339	1
values[31]	368	1			T336	1		T243	1		T339	1
values[32]	356	1			T336	1		T243	1		T339	1
values[33]	363	1			T336	1		T243	1		T339	1
values[34]	299	1			T336	1		T243	1		T339	1
values[35]	404	1			T336	1		T243	1		T339	1
values[36]	351	1			T336	1		T243	1		T339	1
values[37]	338	1			T336	1		T243	1		T339	1
values[38]	339	1			T336	1		T243	1		T339	1
values[39]	321	1			T336	1		T243	1		T339	1
values[40]	368	1			T336	1		T243	1		T339	1
values[41]	307	1			T336	1		T243	1		T339	1
values[42]	329	1			T336	1		T243	1		T339	1
values[43]	311	1			T336	1		T243	1		T339	1
values[44]	241	1			T336	1		T243	1		T339	1
values[45]	240	1			T336	2		T243	1		T339	1
values[46]	180	1			T336	1		T243	1		T339	1
values[47]	225	1			T336	1		T243	1		T339	1
values[48]	227	1			T336	1		T243	1		T339	1
values[49]	184	1			T336	1		T243	1		T339	1
values[50]	195	1			T336	1		T243	1		T339	1
values[51]	120	1			T336	1		T243	1		T339	1
values[52]	129	1			T336	1		T243	1		T339	1
values[53]	113	1			T336	1		T243	1		T339	1
values[54]	131	1			T336	1		T243	1		T339	1
values[55]	132	1			T336	1		T243	1		T339	1
values[56]	84	1			T336	1		T243	1		T339	1
values[57]	82	1			T336	1		T243	1		T339	1
values[58]	63	1			T336	1		T243	1		T339	1
values[59]	70	1			T336	1		T243	1		T339	1
values[60]	61	1			T336	1		T243	1		T339	1
values[61]	64	1			T336	1		T243	1		T339	1
values[62]	71	1			T336	1		T243	1		T339	1
values[63]	53	1			T336	1		T243	1		T339	1
values[64]	68	1			T336	1		T243	1		T339	1
values[65]	86	1			T336	1		T243	1		T339	1
values[66]	110	1			T336	1		T243	1		T339	1
values[67]	104	1			T336	1		T243	1		T339	1
values[68]	89	1			T336	1		T243	1		T339	1
values[69]	103	1			T336	1		T243	1		T339	1
values[70]	88	1			T336	1		T243	1		T339	1
values[71]	70	1			T336	1		T243	1		T339	1
values[72]	72	1			T336	1		T243	1		T339	1
values[73]	82	1			T336	1		T243	1		T339	1
values[74]	92	1			T336	1		T243	1		T339	1
values[75]	106	1			T336	1		T243	1		T339	1
values[76]	115	1			T336	1		T243	1		T339	1
values[77]	94	1			T336	1		T243	1		T339	1
values[78]	113	1			T336	1		T243	1		T339	1
values[79]	92	1			T336	1		T243	1		T339	1
values[80]	91	1			T336	1		T243	1		T339	1
values[81]	79	1			T336	1		T243	1		T339	1
values[82]	86	1			T336	1		T243	1		T339	1
values[83]	87	1			T336	1		T243	1		T339	1
values[84]	86	1			T336	1		T243	1		T339	1
values[85]	85	1			T336	1		T243	1		T339	1
values[86]	76	1			T336	1		T243	1		T339	1
values[87]	57	1			T336	1		T243	1		T339	1
values[88]	60	1			T336	1		T243	1		T339	1
values[89]	50	1			T336	1		T243	1		T339	1
values[90]	40	1			T336	1		T243	1		T339	1
values[91]	46	1			T336	3		T243	1		T339	1
values[92]	49	1			T336	5		T243	1		T339	1
values[93]	51	1			T336	3		T243	1		T339	1
values[94]	43	1			T336	2		T243	1		T339	1
values[95]	61	1			T336	1		T243	1		T339	1
values[96]	53	1			T336	2		T243	1		T339	1
values[97]	53	1			T336	1		T243	1		T339	2
values[98]	50	1			T336	5		T243	1		T339	1
values[99]	55	1			T336	1		T243	1		T339	1
values[100]	49	1			T336	3		T243	1		T339	1
values[101]	41	1			T336	1		T243	1		T339	1
values[102]	52	1			T336	6		T243	1		T339	1
values[103]	51	1			T336	1		T243	1		T339	1
values[104]	52	1			T336	4		T243	1		T339	1
values[105]	45	1			T336	2		T243	1		T339	1
values[106]	65	1			T336	3		T243	1		T339	1
values[107]	77	1			T336	1		T243	2		T339	1
values[108]	66	1			T336	4		T243	7		T339	1
values[109]	53	1			T336	2		T243	1		T339	1
values[110]	64	1			T336	1		T243	3		T339	1
values[111]	50	1			T336	3		T243	2		T339	2
values[112]	48	1			T336	2		T243	2		T339	1
values[113]	54	1			T336	2		T243	3		T339	1
values[114]	52	1			T336	4		T243	4		T339	1
values[115]	40	1			T336	2		T243	2		T339	1
values[116]	46	1			T336	3		T243	1		T339	1
values[117]	61	1			T336	6		T243	1		T339	1
values[118]	53	1			T336	1		T243	2		T339	1
values[119]	53	1			T336	3		T243	4		T339	2
values[120]	45	1			T336	2		T243	2		T339	1
values[121]	40	1			T336	1		T243	1		T339	4
values[122]	47	1			T336	2		T243	3		T339	8
values[123]	48	1			T336	3		T243	1		T339	5
values[124]	45	1			T336	1		T243	2		T339	2
values[125]	49	1			T336	1		T243	1		T339	9
values[126]	96	1			T336	3		T243	5		T339	9
values[127]	1365	1			T336	59		T243	63		T339	61
values[128]	6728	1			T336	260		T243	351		T339	312