Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
121779 |
1 |
|
|
T5 |
12 |
|
T6 |
49 |
|
T7 |
13 |
auto[1] |
65504 |
1 |
|
|
T5 |
4 |
|
T6 |
27 |
|
T7 |
32 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
47311 |
1 |
|
|
T5 |
6 |
|
T6 |
33 |
|
T7 |
3 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
131619 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
55664 |
1 |
|
|
T5 |
9 |
|
T6 |
28 |
|
T7 |
11 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
14640 |
1 |
|
|
T5 |
4 |
|
T6 |
15 |
|
T18 |
30 |