Summary for Variable cp_error
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_error
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
953547 |
1 |
|
|
T5 |
214 |
|
T6 |
472 |
|
T7 |
310 |
auto[1] |
495572 |
1 |
|
|
T5 |
109 |
|
T6 |
69 |
|
T7 |
31 |
Summary for Variable cp_opcode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_opcode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
369802 |
1 |
|
|
T5 |
117 |
|
T6 |
203 |
|
T7 |
41 |
Summary for Variable cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_size
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
1008095 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
biggest_size |
441024 |
1 |
|
|
T5 |
111 |
|
T6 |
166 |
|
T7 |
88 |
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
cp_opcode | cp_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x1] |
biggest_size |
117635 |
1 |
|
|
T5 |
44 |
|
T6 |
52 |
|
T7 |
12 |