Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	486	1			T5	1		T18	1		T156	2
all_values[1]	495	1			T5	1		T156	3		T244	1
all_values[2]	500	1			T5	4		T156	4		T337	1
all_values[3]	465	1			T5	3		T18	1		T156	4
all_values[4]	462	1			T5	3		T18	1		T156	7
all_values[5]	495	1			T5	1		T18	1		T156	4
all_values[6]	456	1			T5	2		T336	1		T156	4
all_values[7]	522	1			T5	3		T18	1		T156	4
all_values[8]	484	1			T5	3		T156	4		T249	1
all_values[9]	486	1			T5	1		T336	1		T156	2
all_values[10]	472	1			T5	3		T156	6		T155	2
all_values[11]	445	1			T5	1		T18	1		T156	3
all_values[12]	498	1			T5	2		T336	1		T156	2
all_values[13]	503	1			T5	2		T18	2		T156	2
all_values[14]	467	1			T5	3		T156	5		T244	1
all_values[15]	504	1			T5	2		T156	3		T249	1
all_values[16]	467	1			T5	2		T336	1		T156	2
all_values[17]	522	1			T5	2		T156	5		T246	1
all_values[18]	495	1			T5	2		T18	3		T156	7
all_values[19]	455	1			T5	3		T156	2		T145	6
all_values[20]	473	1			T5	2		T18	1		T156	3
all_values[21]	457	1			T5	1		T156	2		T243	2
all_values[22]	469	1			T5	2		T156	5		T244	1
all_values[23]	480	1			T18	4		T156	3		T57	1
all_values[24]	514	1			T5	2		T156	7		T57	1
all_values[25]	467	1			T5	1		T156	4		T244	1
all_values[26]	462	1			T5	1		T18	1		T156	3
all_values[27]	414	1			T5	2		T156	1		T145	5
all_values[28]	475	1			T5	1		T156	7		T249	1
all_values[29]	490	1			T5	1		T18	1		T156	2
all_values[30]	485	1			T5	2		T18	2		T156	3
all_values[31]	462	1			T5	3		T156	4		T249	1
all_values[32]	491	1			T5	1		T156	1		T249	1
all_values[33]	498	1			T156	4		T244	1		T57	2
all_values[34]	450	1			T5	3		T156	2		T155	1
all_values[35]	481	1			T5	3		T156	2		T244	1
all_values[36]	473	1			T5	1		T18	1		T156	4
all_values[37]	432	1			T5	1		T156	4		T249	1
all_values[38]	486	1			T5	2		T156	8		T244	1
all_values[39]	457	1			T5	1		T156	5		T243	1
all_values[40]	489	1			T5	2		T156	6		T244	1
all_values[41]	487	1			T18	2		T156	3		T244	1
all_values[42]	433	1			T156	3		T155	1		T246	1
all_values[43]	480	1			T5	1		T18	1		T156	5
all_values[44]	495	1			T18	2		T156	4		T155	1
all_values[45]	482	1			T5	3		T156	2		T243	1
all_values[46]	468	1			T5	3		T156	6		T244	1
all_values[47]	423	1			T5	4		T156	3		T244	1
all_values[48]	494	1			T5	1		T156	1		T337	1
all_values[49]	456	1			T5	2		T156	2		T249	1