Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3432	1			T5	9		T18	3		T52	1
all_values[1]	3512	1			T5	14		T18	8		T52	2
all_values[2]	3442	1			T5	17		T18	10		T52	3
all_values[3]	3506	1			T5	14		T18	6		T52	2
all_values[4]	3452	1			T5	16		T18	8		T52	1
all_values[5]	3503	1			T5	15		T18	3		T52	4
all_values[6]	3388	1			T5	10		T18	6		T52	2
all_values[7]	3540	1			T5	13		T18	10		T52	1
all_values[8]	3451	1			T5	17		T18	2		T52	1
all_values[9]	3487	1			T5	15		T18	6		T52	1
all_values[10]	3513	1			T5	9		T18	7		T52	1
all_values[11]	3474	1			T5	17		T18	4		T52	1
all_values[12]	3370	1			T5	19		T18	3		T52	1
all_values[13]	3450	1			T5	15		T18	10		T52	2
all_values[14]	3402	1			T5	14		T18	8		T52	1
all_values[15]	3427	1			T5	12		T18	3		T156	20
all_values[16]	3559	1			T5	10		T18	6		T52	4
all_values[17]	3473	1			T5	14		T18	8		T52	2
all_values[18]	3493	1			T5	13		T18	6		T52	2
all_values[19]	3459	1			T5	8		T18	3		T156	25
all_values[20]	3502	1			T5	12		T18	10		T156	28
all_values[21]	3436	1			T5	10		T18	2		T52	1
all_values[22]	3468	1			T5	10		T18	13		T52	2
all_values[23]	3481	1			T5	14		T18	3		T52	2
all_values[24]	3407	1			T5	14		T18	6		T156	26
all_values[25]	3444	1			T5	10		T18	7		T52	1
all_values[26]	3410	1			T5	18		T18	8		T156	27
all_values[27]	3370	1			T5	16		T18	5		T52	3
all_values[28]	3461	1			T5	14		T18	6		T52	2
all_values[29]	3546	1			T5	15		T18	9		T52	3
all_values[30]	3466	1			T5	16		T18	7		T52	1
all_values[31]	3457	1			T5	11		T18	5		T52	2
all_values[32]	3425	1			T5	17		T18	10		T52	3
all_values[33]	3421	1			T5	14		T18	5		T52	2
all_values[34]	3481	1			T5	11		T18	1		T52	1
all_values[35]	3352	1			T5	19		T18	4		T52	5
all_values[36]	3513	1			T5	17		T18	11		T52	2
all_values[37]	3461	1			T5	13		T18	9		T52	4
all_values[38]	3421	1			T5	14		T18	6		T156	25
all_values[39]	3438	1			T5	10		T18	4		T156	27
all_values[40]	3448	1			T5	12		T18	6		T156	20
all_values[41]	3469	1			T5	10		T18	6		T52	3
all_values[42]	3375	1			T5	8		T18	11		T52	4
all_values[43]	3617	1			T5	8		T18	3		T52	1
all_values[44]	3465	1			T5	13		T18	7		T52	2
all_values[45]	3401	1			T5	10		T18	9		T52	1
all_values[46]	3442	1			T5	16		T18	10		T52	4
all_values[47]	3533	1			T5	12		T18	5		T52	1
all_values[48]	3404	1			T5	8		T18	2		T52	2
all_values[49]	3624	1			T5	18		T18	6		T156	21
all_values[50]	3400	1			T5	8		T18	5		T52	3
all_values[51]	3550	1			T5	13		T18	7		T52	3
all_values[52]	3383	1			T5	13		T18	5		T52	1
all_values[53]	3456	1			T5	8		T18	6		T156	24
all_values[54]	3405	1			T5	10		T18	5		T52	4
all_values[55]	3553	1			T5	16		T18	3		T52	4
all_values[56]	3418	1			T5	13		T18	7		T52	1
all_values[57]	3462	1			T5	25		T18	5		T52	2
all_values[58]	3451	1			T5	9		T18	9		T52	1
all_values[59]	3481	1			T5	11		T18	6		T52	1
all_values[60]	3510	1			T5	7		T18	5		T52	1
all_values[61]	3556	1			T5	19		T18	6		T156	21
all_values[62]	3461	1			T5	11		T18	10		T52	2
all_values[63]	3341	1			T5	20		T18	4		T52	2