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 LINE       20370
 EXPRESSION (dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T230,T111,T231

 LINE       20523
 EXPRESSION (dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T72,T66,T98

 LINE       20676
 EXPRESSION (dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T97,T213,T177

 LINE       20829
 EXPRESSION (dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T84,T174,T232

 LINE       20982
 EXPRESSION (dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T233,T234,T235

 LINE       21135
 EXPRESSION (dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T236,T123,T237

 LINE       21288
 EXPRESSION (dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T97,T140,T238

 LINE       21441
 EXPRESSION (dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T91,T87,T103

 LINE       21594
 EXPRESSION (dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T80,T239,T137

 LINE       21747
 EXPRESSION (dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T184,T240,T241

 LINE       24535
 EXPRESSION (mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T13,T49
1	1	Covered	T22,T16,T57

 LINE       24567
 EXPRESSION (mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T11,T21
1	1	Covered	T22,T8,T9

 LINE       24599
 EXPRESSION (mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T36,T20
1	1	Covered	T22,T16,T8

 LINE       24631
 EXPRESSION (mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T21,T13
1	1	Covered	T22,T16,T8

 LINE       24663
 EXPRESSION (mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T11,T36
1	1	Covered	T22,T16,T8

 LINE       24695
 EXPRESSION (mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T49
1	1	Covered	T22,T16,T8

 LINE       24727
 EXPRESSION (mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T10
1	1	Covered	T22,T16,T65

 LINE       24759
 EXPRESSION (mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T10
1	1	Covered	T22,T16,T8

 LINE       24791
 EXPRESSION (mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T10,T36
1	1	Covered	T22,T16,T8

 LINE       24823
 EXPRESSION (mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T11
1	1	Covered	T22,T16,T56

 LINE       24855
 EXPRESSION (mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T11
1	1	Covered	T22,T56,T8

 LINE       24887
 EXPRESSION (mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T9
1	1	Covered	T22,T8,T11

 LINE       24919
 EXPRESSION (mio_pad_sleep_en_12_we & mio_pad_sleep_regwen_12_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T10,T11
1	1	Covered	T22,T16,T8

 LINE       24951
 EXPRESSION (mio_pad_sleep_en_13_we & mio_pad_sleep_regwen_13_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T11
1	1	Covered	T22,T16,T8

 LINE       24983
 EXPRESSION (mio_pad_sleep_en_14_we & mio_pad_sleep_regwen_14_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T10,T11
1	1	Covered	T22,T16,T8

 LINE       25015
 EXPRESSION (mio_pad_sleep_en_15_we & mio_pad_sleep_regwen_15_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T10,T41
1	1	Covered	T22,T16,T8

 LINE       25047
 EXPRESSION (mio_pad_sleep_en_16_we & mio_pad_sleep_regwen_16_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T38
1	1	Covered	T22,T75,T8

 LINE       25079
 EXPRESSION (mio_pad_sleep_en_17_we & mio_pad_sleep_regwen_17_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T11
1	1	Covered	T22,T16,T8

 LINE       25111
 EXPRESSION (mio_pad_sleep_en_18_we & mio_pad_sleep_regwen_18_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T41,T49
1	1	Covered	T22,T8,T9

 LINE       25143
 EXPRESSION (mio_pad_sleep_en_19_we & mio_pad_sleep_regwen_19_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T11
1	1	Covered	T22,T16,T146

 LINE       25175
 EXPRESSION (mio_pad_sleep_en_20_we & mio_pad_sleep_regwen_20_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T11
1	1	Covered	T22,T16,T8

 LINE       25207
 EXPRESSION (mio_pad_sleep_en_21_we & mio_pad_sleep_regwen_21_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T10,T11
1	1	Covered	T22,T16,T8

 LINE       25239
 EXPRESSION (mio_pad_sleep_en_22_we & mio_pad_sleep_regwen_22_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T10
1	1	Covered	T22,T8,T63

 LINE       25271
 EXPRESSION (mio_pad_sleep_en_23_we & mio_pad_sleep_regwen_23_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T10
1	1	Covered	T22,T9,T10

 LINE       25303
 EXPRESSION (mio_pad_sleep_en_24_we & mio_pad_sleep_regwen_24_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T9
1	1	Covered	T22,T16,T8

 LINE       25335
 EXPRESSION (mio_pad_sleep_en_25_we & mio_pad_sleep_regwen_25_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T36
1	1	Covered	T22,T16,T8

 LINE       25367
 EXPRESSION (mio_pad_sleep_en_26_we & mio_pad_sleep_regwen_26_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T36,T21
1	1	Covered	T22,T52,T16

 LINE       25399
 EXPRESSION (mio_pad_sleep_en_27_we & mio_pad_sleep_regwen_27_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T8
1	1	Covered	T22,T8,T10

 LINE       25431
 EXPRESSION (mio_pad_sleep_en_28_we & mio_pad_sleep_regwen_28_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T10
1	1	Covered	T22,T16,T8

 LINE       25463
 EXPRESSION (mio_pad_sleep_en_29_we & mio_pad_sleep_regwen_29_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T9
1	1	Covered	T22,T8,T10

 LINE       25495
 EXPRESSION (mio_pad_sleep_en_30_we & mio_pad_sleep_regwen_30_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T36,T20
1	1	Covered	T22,T8,T9

 LINE       25527
 EXPRESSION (mio_pad_sleep_en_31_we & mio_pad_sleep_regwen_31_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T9
1	1	Covered	T8,T63,T10

 LINE       25559
 EXPRESSION (mio_pad_sleep_en_32_we & mio_pad_sleep_regwen_32_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T11,T36
1	1	Covered	T22,T16,T147

 LINE       25591
 EXPRESSION (mio_pad_sleep_en_33_we & mio_pad_sleep_regwen_33_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T36
1	1	Covered	T22,T16,T8

 LINE       25623
 EXPRESSION (mio_pad_sleep_en_34_we & mio_pad_sleep_regwen_34_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T8
1	1	Covered	T22,T8,T9

 LINE       25655
 EXPRESSION (mio_pad_sleep_en_35_we & mio_pad_sleep_regwen_35_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T10,T36
1	1	Covered	T16,T8,T9

 LINE       25687
 EXPRESSION (mio_pad_sleep_en_36_we & mio_pad_sleep_regwen_36_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T10
1	1	Covered	T22,T16,T56

 LINE       25719
 EXPRESSION (mio_pad_sleep_en_37_we & mio_pad_sleep_regwen_37_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T36,T20
1	1	Covered	T22,T52,T16

 LINE       25751
 EXPRESSION (mio_pad_sleep_en_38_we & mio_pad_sleep_regwen_38_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T11
1	1	Covered	T22,T52,T9

 LINE       25783
 EXPRESSION (mio_pad_sleep_en_39_we & mio_pad_sleep_regwen_39_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T9,T10
1	1	Covered	T16,T8,T63

 LINE       25815
 EXPRESSION (mio_pad_sleep_en_40_we & mio_pad_sleep_regwen_40_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T8
1	1	Covered	T22,T16,T8

 LINE       25847
 EXPRESSION (mio_pad_sleep_en_41_we & mio_pad_sleep_regwen_41_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T9,T11
1	1	Covered	T16,T8,T10

 LINE       25879
 EXPRESSION (mio_pad_sleep_en_42_we & mio_pad_sleep_regwen_42_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T36
1	1	Covered	T22,T16,T8

 LINE       25911
 EXPRESSION (mio_pad_sleep_en_43_we & mio_pad_sleep_regwen_43_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T9
1	1	Covered	T22,T8,T63

 LINE       25943
 EXPRESSION (mio_pad_sleep_en_44_we & mio_pad_sleep_regwen_44_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T10
1	1	Covered	T8,T9,T10

 LINE       25975
 EXPRESSION (mio_pad_sleep_en_45_we & mio_pad_sleep_regwen_45_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T9
1	1	Covered	T22,T142,T16

 LINE       26007
 EXPRESSION (mio_pad_sleep_en_46_we & mio_pad_sleep_regwen_46_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T10,T11
1	1	Covered	T22,T16,T8

 LINE       26039
 EXPRESSION (mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T11,T48
1	1	Covered	T22,T16,T8

 LINE       26071
 EXPRESSION (mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T11
1	1	Covered	T22,T16,T8

 LINE       26103
 EXPRESSION (mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T21,T49
1	1	Covered	T22,T16,T8

 LINE       26135
 EXPRESSION (mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T36,T20
1	1	Covered	T22,T16,T8

 LINE       26167
 EXPRESSION (mio_pad_sleep_mode_4_we & mio_pad_sleep_regwen_4_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T11
1	1	Covered	T22,T52,T16

 LINE       26199
 EXPRESSION (mio_pad_sleep_mode_5_we & mio_pad_sleep_regwen_5_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T10,T36
1	1	Covered	T22,T8,T9

 LINE       26231
 EXPRESSION (mio_pad_sleep_mode_6_we & mio_pad_sleep_regwen_6_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T9
1	1	Covered	T22,T16,T8

 LINE       26263
 EXPRESSION (mio_pad_sleep_mode_7_we & mio_pad_sleep_regwen_7_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T36
1	1	Covered	T22,T16,T8

 LINE       26295
 EXPRESSION (mio_pad_sleep_mode_8_we & mio_pad_sleep_regwen_8_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T10,T36
1	1	Covered	T22,T16,T8

 LINE       26327
 EXPRESSION (mio_pad_sleep_mode_9_we & mio_pad_sleep_regwen_9_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T11
1	1	Covered	T22,T16,T57

 LINE       26359
 EXPRESSION (mio_pad_sleep_mode_10_we & mio_pad_sleep_regwen_10_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T11
1	1	Covered	T22,T6,T16

 LINE       26391
 EXPRESSION (mio_pad_sleep_mode_11_we & mio_pad_sleep_regwen_11_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T10,T36
1	1	Covered	T22,T8,T9

 LINE       26423
 EXPRESSION (mio_pad_sleep_mode_12_we & mio_pad_sleep_regwen_12_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T36
1	1	Covered	T22,T16,T57

 LINE       26455
 EXPRESSION (mio_pad_sleep_mode_13_we & mio_pad_sleep_regwen_13_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T11,T36
1	1	Covered	T22,T16,T8

 LINE       26487
 EXPRESSION (mio_pad_sleep_mode_14_we & mio_pad_sleep_regwen_14_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T11
1	1	Covered	T22,T16,T8

 LINE       26519
 EXPRESSION (mio_pad_sleep_mode_15_we & mio_pad_sleep_regwen_15_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T10,T36
1	1	Covered	T22,T16,T8

 LINE       26551
 EXPRESSION (mio_pad_sleep_mode_16_we & mio_pad_sleep_regwen_16_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T11
1	1	Covered	T22,T16,T8

 LINE       26583
 EXPRESSION (mio_pad_sleep_mode_17_we & mio_pad_sleep_regwen_17_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T10
1	1	Covered	T22,T16,T8

 LINE       26615
 EXPRESSION (mio_pad_sleep_mode_18_we & mio_pad_sleep_regwen_18_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T31
1	1	Covered	T22,T8,T10

 LINE       26647
 EXPRESSION (mio_pad_sleep_mode_19_we & mio_pad_sleep_regwen_19_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T11
1	1	Covered	T22,T8,T10

 LINE       26679
 EXPRESSION (mio_pad_sleep_mode_20_we & mio_pad_sleep_regwen_20_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T11
1	1	Covered	T22,T16,T8

 LINE       26711
 EXPRESSION (mio_pad_sleep_mode_21_we & mio_pad_sleep_regwen_21_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T10,T11
1	1	Covered	T22,T16,T8

 LINE       26743
 EXPRESSION (mio_pad_sleep_mode_22_we & mio_pad_sleep_regwen_22_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T10
1	1	Covered	T22,T8,T10

 LINE       26775
 EXPRESSION (mio_pad_sleep_mode_23_we & mio_pad_sleep_regwen_23_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T10
1	1	Covered	T22,T8,T9

 LINE       26807
 EXPRESSION (mio_pad_sleep_mode_24_we & mio_pad_sleep_regwen_24_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T9
1	1	Covered	T22,T8,T10

 LINE       26839
 EXPRESSION (mio_pad_sleep_mode_25_we & mio_pad_sleep_regwen_25_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T36
1	1	Covered	T22,T16,T8

 LINE       26871
 EXPRESSION (mio_pad_sleep_mode_26_we & mio_pad_sleep_regwen_26_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T36,T21
1	1	Covered	T22,T16,T8

 LINE       26903
 EXPRESSION (mio_pad_sleep_mode_27_we & mio_pad_sleep_regwen_27_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T8
1	1	Covered	T5,T8,T10

 LINE       26935
 EXPRESSION (mio_pad_sleep_mode_28_we & mio_pad_sleep_regwen_28_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T21,T49
1	1	Covered	T22,T16,T8

 LINE       26967
 EXPRESSION (mio_pad_sleep_mode_29_we & mio_pad_sleep_regwen_29_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T11
1	1	Covered	T22,T8,T10

 LINE       26999
 EXPRESSION (mio_pad_sleep_mode_30_we & mio_pad_sleep_regwen_30_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T36
1	1	Covered	T22,T8,T9

 LINE       27031
 EXPRESSION (mio_pad_sleep_mode_31_we & mio_pad_sleep_regwen_31_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T11
1	1	Covered	T22,T16,T8

 LINE       27063
 EXPRESSION (mio_pad_sleep_mode_32_we & mio_pad_sleep_regwen_32_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T11,T36
1	1	Covered	T22,T16,T8

 LINE       27095
 EXPRESSION (mio_pad_sleep_mode_33_we & mio_pad_sleep_regwen_33_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T10,T36
1	1	Covered	T22,T16,T8

 LINE       27127
 EXPRESSION (mio_pad_sleep_mode_34_we & mio_pad_sleep_regwen_34_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T11
1	1	Covered	T22,T8,T9

 LINE       27159
 EXPRESSION (mio_pad_sleep_mode_35_we & mio_pad_sleep_regwen_35_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T10,T36
1	1	Covered	T22,T16,T8

 LINE       27191
 EXPRESSION (mio_pad_sleep_mode_36_we & mio_pad_sleep_regwen_36_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T10,T11
1	1	Covered	T16,T8,T9

 LINE       27223
 EXPRESSION (mio_pad_sleep_mode_37_we & mio_pad_sleep_regwen_37_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T36
1	1	Covered	T22,T16,T8

 LINE       27255
 EXPRESSION (mio_pad_sleep_mode_38_we & mio_pad_sleep_regwen_38_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T11
1	1	Covered	T22,T9,T10

 LINE       27287
 EXPRESSION (mio_pad_sleep_mode_39_we & mio_pad_sleep_regwen_39_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T9,T10
1	1	Covered	T22,T16,T8

 LINE       27319
 EXPRESSION (mio_pad_sleep_mode_40_we & mio_pad_sleep_regwen_40_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T8
1	1	Covered	T22,T9,T10

 LINE       27351
 EXPRESSION (mio_pad_sleep_mode_41_we & mio_pad_sleep_regwen_41_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T9,T10
1	1	Covered	T16,T8,T10

 LINE       27383
 EXPRESSION (mio_pad_sleep_mode_42_we & mio_pad_sleep_regwen_42_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T36
1	1	Covered	T22,T16,T8

 LINE       27415
 EXPRESSION (mio_pad_sleep_mode_43_we & mio_pad_sleep_regwen_43_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T9
1	1	Covered	T22,T16,T10

 LINE       27447
 EXPRESSION (mio_pad_sleep_mode_44_we & mio_pad_sleep_regwen_44_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T10
1	1	Covered	T8,T9,T115

 LINE       27479
 EXPRESSION (mio_pad_sleep_mode_45_we & mio_pad_sleep_regwen_45_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T9
1	1	Covered	T22,T16,T146

 LINE       27511
 EXPRESSION (mio_pad_sleep_mode_46_we & mio_pad_sleep_regwen_46_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T10,T11
1	1	Covered	T22,T16,T8

 LINE       28442
 EXPRESSION (dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T20,T242
1	1	Covered	T22,T16,T8

 LINE       28474
 EXPRESSION (dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T9
1	1	Covered	T22,T16,T8

 LINE       28506
 EXPRESSION (dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T10
1	1	Covered	T22,T16,T8

 LINE       28538
 EXPRESSION (dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T9
1	1	Covered	T22,T8,T121

 LINE       28570
 EXPRESSION (dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T8
1	1	Covered	T10,T81,T36

 LINE       28602
 EXPRESSION (dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T9,T48
1	1	Covered	T16,T8,T115

 LINE       28634
 EXPRESSION (dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T10
1	1	Covered	T22,T8,T9

 LINE       28666
 EXPRESSION (dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T11,T13
1	1	Covered	T22,T146,T8

 LINE       28698
 EXPRESSION (dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T36,T41
1	1	Covered	T22,T16,T8

 LINE       28730
 EXPRESSION (dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T9
1	1	Covered	T22,T8,T10

 LINE       28762
 EXPRESSION (dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T11
1	1	Covered	T22,T16,T8

 LINE       28794
 EXPRESSION (dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T10,T36
1	1	Covered	T22,T150,T8

 LINE       28826
 EXPRESSION (dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T11
1	1	Covered	T22,T8,T10

 LINE       28858
 EXPRESSION (dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T8,T9
1	1	Covered	T22,T16,T74

 LINE       28890
 EXPRESSION (dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T8
1	1	Covered	T16,T8,T10

 LINE       28922
 EXPRESSION (dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T8
1	1	Covered	T8,T10,T11

 LINE       28954
 EXPRESSION (dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T20,T242
1	1	Covered	T22,T16,T8

 LINE       28986
 EXPRESSION (dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T9
1	1	Covered	T22,T16,T8

 LINE       29018
 EXPRESSION (dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T10
1	1	Covered	T22,T8,T9

 LINE       29050
 EXPRESSION (dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T11
1	1	Covered	T22,T8,T67

 LINE       29082
 EXPRESSION (dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T8
1	1	Covered	T9,T10,T66

 LINE       29114
 EXPRESSION (dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T9,T48
1	1	Covered	T16,T8,T10

 LINE       29146
 EXPRESSION (dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T10
1	1	Covered	T22,T8,T9

 LINE       29178
 EXPRESSION (dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T11
1	1	Covered	T22,T16,T8

 LINE       29210
 EXPRESSION (dio_pad_sleep_mode_8_we & dio_pad_sleep_regwen_8_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T10
1	1	Covered	T22,T16,T8

 LINE       29242
 EXPRESSION (dio_pad_sleep_mode_9_we & dio_pad_sleep_regwen_9_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T11,T20
1	1	Covered	T22,T8,T63

 LINE       29274
 EXPRESSION (dio_pad_sleep_mode_10_we & dio_pad_sleep_regwen_10_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T8,T10
1	1	Covered	T22,T16,T8

 LINE       29306
 EXPRESSION (dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T8
1	1	Covered	T22,T8,T10

 LINE       29338
 EXPRESSION (dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T9,T11
1	1	Covered	T22,T16,T8

 LINE       29370
 EXPRESSION (dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T9,T11
1	1	Covered	T16,T8,T10

 LINE       29402
 EXPRESSION (dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T8,T21
1	1	Covered	T16,T8,T9

 LINE       29434
 EXPRESSION (dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T16,T9
1	1	Covered	T8,T10,T110

 LINE       29698
 EXPRESSION (aon_wkup_detector_en_0_we & aon_wkup_detector_en_0_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T9,T13
1	1	Covered	T22,T16,T8

 LINE       29731
 EXPRESSION (aon_wkup_detector_en_1_we & aon_wkup_detector_en_1_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T22,T16,T8
1	1	Covered	T8,T9,T10

 LINE       29764
 EXPRESSION (aon_wkup_detector_en_2_we & aon_wkup_detector_en_2_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T10,T36
1	1	Covered	T22,T16,T8

 LINE       29797
 EXPRESSION (aon_wkup_detector_en_3_we & aon_wkup_detector_en_3_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T22,T16,T9
1	1	Covered	T22,T16,T8

 LINE       29830
 EXPRESSION (aon_wkup_detector_en_4_we & aon_wkup_detector_en_4_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T8,T9
1	1	Covered	T22,T8,T10

 LINE       29863
 EXPRESSION (aon_wkup_detector_en_5_we & aon_wkup_detector_en_5_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T22,T16,T8
1	1	Covered	T16,T8,T10

 LINE       29896
 EXPRESSION (aon_wkup_detector_en_6_we & aon_wkup_detector_en_6_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T11
1	1	Covered	T22,T16,T8

 LINE       29929
 EXPRESSION (aon_wkup_detector_en_7_we & aon_wkup_detector_en_7_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T22,T16,T8
1	1	Covered	T16,T9,T10