Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}
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Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 50 0 50 100.00


Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 50 0 50 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 50 0 50 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 442 1 T423 2 T416 2 T507 7
all_values[1] 467 1 T417 1 T507 2 T452 3
all_values[2] 465 1 T710 1 T423 1 T416 4
all_values[3] 447 1 T710 1 T416 3 T452 2
all_values[4] 496 1 T423 1 T416 1 T417 2
all_values[5] 461 1 T423 1 T507 2 T452 3
all_values[6] 463 1 T416 4 T417 2 T507 5
all_values[7] 455 1 T423 1 T416 1 T507 1
all_values[8] 468 1 T416 1 T507 3 T452 2
all_values[9] 468 1 T710 1 T416 1 T417 1
all_values[10] 441 1 T710 1 T417 1 T507 6
all_values[11] 476 1 T423 2 T417 1 T507 3
all_values[12] 425 1 T416 1 T507 3 T452 1
all_values[13] 458 1 T423 1 T416 2 T507 1
all_values[14] 417 1 T507 1 T452 5 T681 5
all_values[15] 475 1 T416 2 T417 1 T507 2
all_values[16] 496 1 T710 2 T417 1 T507 5
all_values[17] 483 1 T416 3 T507 2 T452 4
all_values[18] 448 1 T507 3 T452 3 T681 5
all_values[19] 484 1 T417 1 T507 6 T452 4
all_values[20] 454 1 T423 1 T507 3 T452 2
all_values[21] 457 1 T416 3 T417 3 T507 3
all_values[22] 456 1 T710 1 T507 4 T452 3
all_values[23] 458 1 T507 3 T452 1 T681 1
all_values[24] 443 1 T416 2 T417 1 T507 1
all_values[25] 438 1 T423 1 T417 2 T507 1
all_values[26] 478 1 T423 1 T416 1 T507 4
all_values[27] 413 1 T416 2 T417 1 T507 5
all_values[28] 471 1 T710 1 T417 1 T507 1
all_values[29] 426 1 T423 1 T416 2 T417 1
all_values[30] 454 1 T507 4 T452 1 T426 1
all_values[31] 461 1 T423 1 T416 1 T507 6
all_values[32] 432 1 T416 2 T417 1 T507 3
all_values[33] 459 1 T423 1 T416 2 T417 1
all_values[34] 480 1 T423 1 T416 1 T417 2
all_values[35] 494 1 T423 1 T507 2 T452 3
all_values[36] 450 1 T423 1 T417 1 T507 4
all_values[37] 438 1 T423 1 T417 1 T507 2
all_values[38] 474 1 T416 1 T417 1 T507 4
all_values[39] 465 1 T416 1 T507 3 T452 3
all_values[40] 436 1 T416 1 T417 1 T507 4
all_values[41] 470 1 T423 1 T417 1 T507 5
all_values[42] 451 1 T416 2 T507 2 T452 6
all_values[43] 436 1 T507 8 T452 1 T681 2
all_values[44] 432 1 T416 1 T417 1 T507 5
all_values[45] 439 1 T416 1 T507 6 T452 4
all_values[46] 469 1 T416 1 T507 2 T452 1
all_values[47] 431 1 T416 1 T417 2 T507 3
all_values[48] 434 1 T710 1 T423 1 T416 4
all_values[49] 457 1 T416 1 T507 3 T452 3

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