Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3507	1			T432	2		T226	2		T423	4
all_values[1]	3466	1			T226	3		T423	5		T416	12
all_values[2]	3381	1			T432	3		T226	3		T423	5
all_values[3]	3556	1			T432	3		T226	2		T423	6
all_values[4]	3451	1			T432	3		T226	2		T423	6
all_values[5]	3407	1			T432	2		T226	1		T423	4
all_values[6]	3402	1			T432	1		T226	2		T423	9
all_values[7]	3424	1			T432	5		T226	2		T423	5
all_values[8]	3492	1			T432	1		T226	2		T423	7
all_values[9]	3383	1			T432	1		T226	2		T423	13
all_values[10]	3383	1			T432	2		T226	5		T423	9
all_values[11]	3431	1			T432	8		T226	2		T423	4
all_values[12]	3536	1			T226	1		T423	3		T416	7
all_values[13]	3499	1			T432	3		T226	3		T423	5
all_values[14]	3472	1			T432	5		T226	6		T423	5
all_values[15]	3452	1			T432	5		T226	2		T423	8
all_values[16]	3466	1			T432	3		T226	2		T423	6
all_values[17]	3337	1			T432	5		T226	3		T423	7
all_values[18]	3523	1			T432	1		T226	3		T423	7
all_values[19]	3504	1			T432	1		T423	9		T416	9
all_values[20]	3412	1			T226	2		T423	5		T416	11
all_values[21]	3410	1			T432	2		T226	1		T423	5
all_values[22]	3481	1			T432	1		T226	4		T423	6
all_values[23]	3473	1			T432	2		T226	1		T423	1
all_values[24]	3634	1			T432	6		T226	5		T423	6
all_values[25]	3402	1			T432	4		T226	2		T423	6
all_values[26]	3344	1			T432	3		T226	4		T423	5
all_values[27]	3381	1			T432	1		T226	6		T423	8
all_values[28]	3480	1			T432	2		T226	3		T423	6
all_values[29]	3418	1			T432	3		T226	1		T423	6
all_values[30]	3257	1			T432	3		T226	4		T423	7
all_values[31]	3450	1			T432	2		T226	4		T423	12
all_values[32]	3355	1			T432	2		T226	1		T423	7
all_values[33]	3487	1			T432	3		T423	4		T416	10
all_values[34]	3497	1			T432	4		T226	3		T423	14
all_values[35]	3434	1			T226	4		T423	6		T416	7
all_values[36]	3524	1			T432	2		T226	2		T423	9
all_values[37]	3406	1			T432	1		T423	7		T416	5
all_values[38]	3454	1			T432	2		T226	2		T423	4
all_values[39]	3388	1			T432	3		T226	2		T423	7
all_values[40]	3464	1			T432	3		T226	2		T423	9
all_values[41]	3479	1			T226	4		T423	8		T416	5
all_values[42]	3376	1			T432	3		T423	6		T416	12
all_values[43]	3350	1			T432	2		T423	6		T416	12
all_values[44]	3476	1			T432	4		T226	1		T423	6
all_values[45]	3359	1			T432	2		T226	4		T423	13
all_values[46]	3399	1			T432	4		T226	5		T423	10
all_values[47]	3420	1			T432	3		T226	1		T423	6
all_values[48]	3456	1			T432	2		T226	3		T423	5
all_values[49]	3454	1			T432	2		T423	3		T416	6
all_values[50]	3528	1			T432	2		T226	1		T423	5
all_values[51]	3414	1			T226	4		T423	7		T416	6
all_values[52]	3487	1			T432	4		T226	3		T423	6
all_values[53]	3416	1			T432	2		T226	2		T423	6
all_values[54]	3427	1			T432	4		T423	6		T416	6
all_values[55]	3492	1			T432	5		T226	3		T423	8
all_values[56]	3369	1			T432	3		T423	9		T416	8
all_values[57]	3514	1			T432	1		T226	4		T423	5
all_values[58]	3330	1			T432	3		T226	1		T423	10
all_values[59]	3385	1			T432	1		T226	2		T423	2
all_values[60]	3591	1			T432	2		T423	13		T416	5
all_values[61]	3480	1			T226	3		T423	11		T416	7
all_values[62]	3473	1			T432	5		T226	1		T423	7
all_values[63]	3529	1			T432	1		T226	2		T423	5