Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139893	1			T88	45		T89	58		T91	75
values[2]	9087	1			T91	1		T249	1		T250	3
values[3]	3310	1			T249	1		T500	7		T502	126
values[4]	1882	1			T500	5		T502	46		T393	22
values[5]	1283	1			T500	14		T502	52		T393	24
values[6]	916	1			T500	2		T502	22		T393	24
values[7]	761	1			T500	8		T502	6		T393	36
values[8]	524	1			T500	12		T502	1		T393	19
values[9]	431	1			T500	3		T393	5		T564	12
values[10]	421	1			T500	6		T564	6		T456	10
values[11]	342	1			T500	13		T564	3		T456	5
values[12]	343	1			T500	15		T564	4		T456	5
values[13]	307	1			T500	6		T564	3		T456	19
values[14]	307	1			T500	5		T564	4		T456	2
values[15]	335	1			T500	15		T564	14		T456	7
values[16]	317	1			T500	10		T564	7		T456	7
values[17]	317	1			T500	4		T564	4		T456	6
values[18]	320	1			T500	7		T564	24		T456	5
values[19]	297	1			T500	15		T564	7		T456	3
values[20]	320	1			T500	5		T564	7		T456	6
values[21]	272	1			T500	5		T564	4		T456	3
values[22]	314	1			T500	3		T564	3		T456	15
values[23]	319	1			T500	4		T564	3		T456	5
values[24]	335	1			T500	5		T564	8		T456	3
values[25]	306	1			T500	6		T564	7		T456	4
values[26]	291	1			T500	11		T564	5		T456	3
values[27]	301	1			T500	7		T564	6		T456	6
values[28]	331	1			T500	9		T564	6		T456	11
values[29]	335	1			T500	14		T564	6		T456	12
values[30]	289	1			T500	11		T564	11		T456	11
values[31]	288	1			T500	5		T564	6		T456	9
values[32]	259	1			T500	4		T564	3		T456	4
values[33]	286	1			T500	4		T564	16		T456	3
values[34]	320	1			T500	4		T564	5		T456	9
values[35]	278	1			T500	6		T564	5		T456	4
values[36]	292	1			T500	4		T564	12		T456	7
values[37]	290	1			T500	5		T564	12		T456	10
values[38]	337	1			T500	16		T564	7		T456	3
values[39]	355	1			T500	14		T564	13		T456	9
values[40]	355	1			T500	10		T564	5		T456	8
values[41]	290	1			T500	6		T564	3		T456	4
values[42]	318	1			T500	8		T564	6		T456	7
values[43]	289	1			T500	5		T564	4		T456	19
values[44]	316	1			T500	14		T564	3		T456	10
values[45]	300	1			T500	20		T564	15		T456	3
values[46]	337	1			T500	14		T564	8		T456	11
values[47]	307	1			T500	4		T564	6		T456	7
values[48]	241	1			T500	5		T564	5		T456	4
values[49]	274	1			T500	3		T564	19		T456	9
values[50]	268	1			T500	5		T564	11		T456	7
values[51]	262	1			T500	11		T564	4		T456	3
values[52]	259	1			T500	1		T564	5		T456	16
values[53]	247	1			T564	4		T456	5		T513	2
values[54]	249	1			T564	11		T456	4		T513	1
values[55]	244	1			T564	8		T456	4		T513	2
values[56]	223	1			T564	4		T456	11		T513	2
values[57]	220	1			T564	5		T456	10		T513	4
values[58]	201	1			T564	5		T456	4		T513	7
values[59]	226	1			T564	9		T456	6		T513	2
values[60]	218	1			T564	17		T456	8		T513	1
values[61]	244	1			T564	6		T456	14		T513	1
values[62]	203	1			T564	3		T456	16		T513	4
values[63]	158	1			T564	11		T456	4		T513	4
values[64]	148	1			T564	4		T456	5		T513	3
values[65]	171	1			T564	14		T456	4		T513	3
values[66]	153	1			T564	3		T456	15		T513	6
values[67]	114	1			T564	6		T456	3		T513	3
values[68]	134	1			T564	9		T456	13		T513	2
values[69]	88	1			T564	1		T456	8		T513	2
values[70]	97	1			T456	3		T513	2		T549	10
values[71]	91	1			T456	5		T513	4		T549	7
values[72]	76	1			T513	1		T549	10		T792	1
values[73]	67	1			T513	1		T549	19		T792	1
values[74]	70	1			T513	4		T549	21		T792	1
values[75]	67	1			T513	1		T549	7		T792	1
values[76]	58	1			T513	2		T549	3		T792	1
values[77]	60	1			T513	5		T549	7		T792	1
values[78]	63	1			T513	4		T549	8		T792	1
values[79]	54	1			T513	3		T549	2		T792	1
values[80]	61	1			T513	1		T549	5		T792	1
values[81]	52	1			T513	1		T549	8		T792	1
values[82]	43	1			T513	1		T549	5		T792	1
values[83]	54	1			T513	3		T549	2		T792	1
values[84]	50	1			T513	1		T549	2		T792	1
values[85]	57	1			T513	3		T549	4		T792	1
values[86]	54	1			T513	3		T549	5		T792	1
values[87]	60	1			T513	3		T549	9		T792	1
values[88]	70	1			T513	1		T549	8		T792	1
values[89]	50	1			T513	2		T549	7		T792	1
values[90]	48	1			T513	1		T549	4		T792	1
values[91]	57	1			T513	3		T549	9		T792	1
values[92]	52	1			T513	1		T549	9		T792	1
values[93]	52	1			T513	1		T549	6		T792	1
values[94]	64	1			T513	5		T549	3		T792	1
values[95]	58	1			T513	5		T549	7		T792	1
values[96]	68	1			T513	5		T549	5		T792	1
values[97]	58	1			T513	5		T549	7		T792	1
values[98]	58	1			T513	4		T549	3		T792	1
values[99]	54	1			T513	4		T549	1		T792	1
values[100]	54	1			T513	3		T549	5		T792	1
values[101]	59	1			T513	6		T549	5		T792	1
values[102]	49	1			T513	4		T549	7		T792	1
values[103]	55	1			T513	9		T549	14		T792	1
values[104]	54	1			T513	8		T792	1		T796	1
values[105]	61	1			T513	7		T792	1		T796	1
values[106]	57	1			T513	8		T792	1		T796	1
values[107]	57	1			T513	2		T792	1		T796	1
values[108]	51	1			T513	4		T792	1		T796	1
values[109]	68	1			T513	5		T792	1		T796	1
values[110]	55	1			T513	1		T792	3		T796	1
values[111]	54	1			T513	4		T792	2		T796	1
values[112]	58	1			T513	9		T792	4		T796	1
values[113]	46	1			T513	8		T792	1		T796	1
values[114]	44	1			T513	3		T792	3		T796	1
values[115]	52	1			T513	1		T792	5		T796	1
values[116]	46	1			T513	2		T792	6		T796	1
values[117]	57	1			T513	1		T792	1		T796	1
values[118]	46	1			T513	3		T792	3		T796	1
values[119]	51	1			T513	1		T792	3		T796	1
values[120]	51	1			T513	5		T792	1		T796	1
values[121]	48	1			T513	2		T792	1		T796	1
values[122]	49	1			T513	5		T792	2		T796	1
values[123]	35	1			T513	4		T792	3		T796	2
values[124]	54	1			T513	4		T792	4		T796	2
values[125]	73	1			T513	18		T792	1		T796	6
values[126]	105	1			T513	31		T792	1		T796	7
values[127]	715	1			T513	63		T792	43		T796	43
values[128]	5731	1			T513	39		T792	381		T796	356