Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
big_delay 500 1 T91 1 T249 1 T507 1
small_delay 671 1 T88 1 T250 1 T427 1
zero 629 1 T89 1 T500 1 T426 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
big_delay 200 1 T91 1 T504 1 T492 1
small_delay 971 1 T88 1 T249 1 T250 1
zero 629 1 T89 1 T500 1 T426 1