Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	440	1			T477	1		T501	1		T415	2
all_values[1]	468	1			T477	3		T415	2		T503	4
all_values[2]	472	1			T500	1		T477	2		T501	1
all_values[3]	456	1			T415	2		T420	4		T393	7
all_values[4]	423	1			T477	1		T501	3		T415	3
all_values[5]	482	1			T477	1		T501	1		T415	2
all_values[6]	445	1			T477	1		T501	2		T415	2
all_values[7]	449	1			T500	1		T426	1		T477	2
all_values[8]	428	1			T500	1		T426	1		T477	3
all_values[9]	440	1			T477	1		T415	7		T503	1
all_values[10]	468	1			T477	3		T415	2		T503	5
all_values[11]	436	1			T477	1		T501	1		T415	2
all_values[12]	468	1			T426	1		T477	2		T501	3
all_values[13]	456	1			T500	1		T415	2		T503	2
all_values[14]	465	1			T500	1		T426	1		T415	5
all_values[15]	387	1			T477	2		T501	2		T415	1
all_values[16]	452	1			T426	1		T477	1		T501	2
all_values[17]	492	1			T477	2		T501	1		T415	2
all_values[18]	460	1			T501	1		T415	4		T503	3
all_values[19]	427	1			T477	3		T501	1		T415	4
all_values[20]	472	1			T500	1		T477	1		T501	1
all_values[21]	466	1			T500	1		T477	3		T501	4
all_values[22]	462	1			T477	4		T501	3		T415	4
all_values[23]	490	1			T501	3		T415	4		T503	4
all_values[24]	459	1			T500	1		T477	4		T501	2
all_values[25]	445	1			T426	1		T415	2		T505	1
all_values[26]	438	1			T426	1		T477	2		T501	3
all_values[27]	425	1			T426	1		T477	1		T501	1
all_values[28]	440	1			T501	1		T415	1		T503	1
all_values[29]	428	1			T477	1		T415	3		T503	5
all_values[30]	446	1			T501	2		T415	5		T503	3
all_values[31]	521	1			T477	1		T415	6		T503	1
all_values[32]	467	1			T500	1		T477	2		T501	1
all_values[33]	466	1			T500	1		T477	2		T501	2
all_values[34]	435	1			T500	1		T426	1		T477	1
all_values[35]	476	1			T500	1		T426	1		T477	2
all_values[36]	490	1			T477	3		T501	2		T415	12
all_values[37]	463	1			T500	1		T426	1		T477	3
all_values[38]	448	1			T477	3		T501	2		T415	5
all_values[39]	436	1			T500	1		T477	3		T415	2
all_values[40]	493	1			T500	1		T477	5		T501	3
all_values[41]	463	1			T477	1		T501	2		T415	8
all_values[42]	483	1			T500	1		T426	1		T477	1
all_values[43]	463	1			T500	1		T477	4		T415	3
all_values[44]	471	1			T426	2		T477	3		T415	3
all_values[45]	446	1			T500	1		T426	1		T477	3
all_values[46]	483	1			T500	1		T477	1		T501	3
all_values[47]	456	1			T477	4		T501	1		T415	4
all_values[48]	450	1			T500	1		T477	7		T501	1
all_values[49]	509	1			T477	3		T501	1		T415	3