Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3549	1			T89	2		T427	1		T477	14
all_values[1]	3542	1			T89	4		T477	10		T501	18
all_values[2]	3603	1			T426	2		T477	17		T501	14
all_values[3]	3449	1			T89	2		T426	2		T477	10
all_values[4]	3537	1			T89	4		T426	3		T477	14
all_values[5]	3601	1			T89	1		T426	1		T477	13
all_values[6]	3607	1			T89	2		T426	3		T477	20
all_values[7]	3545	1			T426	1		T477	10		T501	17
all_values[8]	3589	1			T89	2		T427	1		T426	2
all_values[9]	3578	1			T89	2		T426	3		T477	22
all_values[10]	3630	1			T89	3		T426	2		T477	9
all_values[11]	3427	1			T89	2		T426	3		T477	17
all_values[12]	3515	1			T89	4		T426	1		T477	13
all_values[13]	3563	1			T89	4		T427	2		T426	2
all_values[14]	3489	1			T89	1		T426	1		T477	14
all_values[15]	3548	1			T89	1		T427	1		T426	2
all_values[16]	3587	1			T427	1		T426	2		T477	12
all_values[17]	3557	1			T89	2		T426	1		T477	19
all_values[18]	3450	1			T89	2		T426	1		T477	19
all_values[19]	3565	1			T89	2		T427	2		T477	17
all_values[20]	3444	1			T89	2		T477	13		T501	14
all_values[21]	3565	1			T89	1		T426	2		T477	20
all_values[22]	3600	1			T89	6		T427	1		T426	5
all_values[23]	3480	1			T89	1		T426	4		T477	10
all_values[24]	3526	1			T427	1		T426	3		T477	19
all_values[25]	3597	1			T89	2		T427	1		T426	1
all_values[26]	3623	1			T427	1		T426	1		T477	18
all_values[27]	3459	1			T89	1		T426	3		T477	18
all_values[28]	3549	1			T89	2		T426	4		T477	24
all_values[29]	3639	1			T89	2		T426	3		T477	10
all_values[30]	3524	1			T89	2		T426	2		T477	20
all_values[31]	3578	1			T89	7		T427	1		T477	19
all_values[32]	3561	1			T426	2		T477	17		T501	11
all_values[33]	3606	1			T89	3		T426	2		T477	15
all_values[34]	3573	1			T89	2		T426	4		T477	17
all_values[35]	3586	1			T89	2		T427	2		T426	1
all_values[36]	3508	1			T89	3		T426	5		T477	16
all_values[37]	3532	1			T89	1		T426	2		T477	19
all_values[38]	3493	1			T89	3		T426	2		T477	11
all_values[39]	3497	1			T89	1		T426	1		T477	10
all_values[40]	3488	1			T89	3		T426	2		T477	17
all_values[41]	3543	1			T89	3		T427	1		T426	7
all_values[42]	3495	1			T89	1		T426	1		T477	30
all_values[43]	3639	1			T89	3		T426	5		T477	21
all_values[44]	3590	1			T89	4		T426	4		T477	19
all_values[45]	3533	1			T427	1		T426	3		T477	9
all_values[46]	3587	1			T89	2		T426	2		T477	20
all_values[47]	3533	1			T89	4		T427	1		T426	2
all_values[48]	3607	1			T89	2		T426	3		T477	17
all_values[49]	3614	1			T89	1		T426	7		T477	19
all_values[50]	3486	1			T89	2		T426	2		T477	15
all_values[51]	3496	1			T89	1		T427	2		T426	1
all_values[52]	3526	1			T89	1		T427	1		T426	5
all_values[53]	3511	1			T89	1		T426	1		T477	14
all_values[54]	3493	1			T89	2		T477	13		T501	14
all_values[55]	3645	1			T426	2		T477	13		T501	12
all_values[56]	3459	1			T89	3		T426	3		T477	21
all_values[57]	3487	1			T89	2		T427	1		T426	1
all_values[58]	3567	1			T89	2		T427	1		T426	2
all_values[59]	3681	1			T89	2		T426	3		T477	10
all_values[60]	3566	1			T426	3		T477	13		T501	11
all_values[61]	3518	1			T89	2		T427	1		T426	1
all_values[62]	3535	1			T89	3		T427	1		T426	5
all_values[63]	3504	1			T89	1		T426	2		T477	17