Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	153011	1			T83	7		T84	118		T85	11
values[2]	5218	1			T84	1		T85	1		T136	1
values[3]	2931	1			T543	1		T540	30		T584	1
values[4]	2394	1			T540	24		T922	1		T923	32
values[5]	1825	1			T540	13		T922	1		T923	39
values[6]	1427	1			T540	7		T922	1		T923	44
values[7]	1283	1			T540	14		T922	1		T923	69
values[8]	1054	1			T540	20		T922	1		T923	88
values[9]	826	1			T540	7		T922	1		T923	121
values[10]	744	1			T540	7		T922	1		T923	85
values[11]	606	1			T922	1		T923	67		T569	1
values[12]	582	1			T922	1		T923	59		T569	3
values[13]	512	1			T922	1		T923	45		T569	2
values[14]	521	1			T922	1		T923	36		T569	3
values[15]	427	1			T922	1		T923	22		T569	1
values[16]	410	1			T922	1		T923	13		T569	5
values[17]	403	1			T922	1		T923	12		T569	7
values[18]	432	1			T922	1		T923	15		T569	7
values[19]	403	1			T922	1		T923	16		T569	12
values[20]	355	1			T922	1		T923	7		T569	19
values[21]	305	1			T922	1		T923	3		T569	28
values[22]	295	1			T922	1		T923	4		T569	19
values[23]	203	1			T922	1		T923	7		T569	2
values[24]	216	1			T922	1		T923	1		T569	3
values[25]	254	1			T922	1		T569	18		T896	1
values[26]	295	1			T922	1		T569	12		T896	1
values[27]	277	1			T922	1		T569	34		T896	1
values[28]	231	1			T922	1		T569	25		T896	1
values[29]	232	1			T922	1		T569	24		T896	1
values[30]	202	1			T922	1		T569	28		T896	1
values[31]	146	1			T922	1		T569	13		T896	1
values[32]	169	1			T922	1		T569	11		T896	1
values[33]	145	1			T922	1		T569	2		T896	1
values[34]	83	1			T922	1		T896	1		T522	2
values[35]	80	1			T922	1		T896	1		T522	2
values[36]	68	1			T922	1		T896	1		T522	2
values[37]	79	1			T922	1		T896	1		T522	2
values[38]	76	1			T922	1		T896	1		T522	2
values[39]	80	1			T922	1		T896	1		T522	2
values[40]	74	1			T922	1		T896	1		T522	2
values[41]	68	1			T922	1		T896	1		T522	2
values[42]	55	1			T922	1		T896	1		T522	2
values[43]	57	1			T922	1		T896	1		T522	2
values[44]	61	1			T922	1		T896	1		T522	2
values[45]	56	1			T922	1		T896	1		T522	2
values[46]	67	1			T922	1		T896	1		T522	2
values[47]	60	1			T922	1		T896	1		T522	2
values[48]	56	1			T922	1		T896	1		T522	2
values[49]	51	1			T922	1		T896	1		T522	2
values[50]	52	1			T922	1		T896	1		T522	2
values[51]	58	1			T922	1		T896	1		T522	2
values[52]	53	1			T922	1		T896	1		T522	2
values[53]	47	1			T922	1		T896	1		T522	2
values[54]	53	1			T922	1		T896	1		T522	2
values[55]	53	1			T922	1		T896	1		T522	2
values[56]	58	1			T922	1		T896	1		T522	2
values[57]	49	1			T922	1		T896	1		T522	2
values[58]	58	1			T922	1		T896	1		T522	2
values[59]	64	1			T922	1		T896	1		T522	2
values[60]	59	1			T922	1		T896	1		T522	2
values[61]	70	1			T922	1		T896	1		T522	2
values[62]	68	1			T922	1		T896	1		T522	2
values[63]	60	1			T922	1		T896	1		T522	2
values[64]	65	1			T922	1		T896	1		T522	2
values[65]	61	1			T922	1		T896	1		T522	2
values[66]	62	1			T922	1		T896	1		T522	2
values[67]	55	1			T922	1		T896	1		T522	2
values[68]	58	1			T922	1		T896	1		T522	2
values[69]	57	1			T922	1		T896	1		T522	2
values[70]	55	1			T922	1		T896	1		T522	2
values[71]	60	1			T922	1		T896	1		T522	2
values[72]	58	1			T922	1		T896	1		T522	2
values[73]	52	1			T922	1		T896	1		T522	2
values[74]	60	1			T922	1		T896	1		T522	2
values[75]	56	1			T922	1		T896	1		T522	2
values[76]	58	1			T922	1		T896	1		T522	2
values[77]	62	1			T922	1		T896	1		T522	2
values[78]	53	1			T922	1		T896	1		T522	2
values[79]	62	1			T922	1		T896	1		T522	2
values[80]	59	1			T922	1		T896	1		T522	2
values[81]	67	1			T922	1		T896	1		T522	2
values[82]	79	1			T922	1		T896	1		T522	2
values[83]	74	1			T922	1		T896	1		T522	2
values[84]	60	1			T922	1		T896	1		T522	2
values[85]	75	1			T922	1		T896	1		T522	2
values[86]	69	1			T922	1		T896	1		T522	2
values[87]	73	1			T922	1		T896	1		T522	2
values[88]	85	1			T922	1		T896	1		T522	3
values[89]	71	1			T922	1		T896	1		T522	2
values[90]	75	1			T922	1		T896	1		T522	2
values[91]	85	1			T922	1		T896	1		T522	2
values[92]	65	1			T922	1		T896	1		T522	2
values[93]	64	1			T922	1		T896	1		T522	2
values[94]	75	1			T922	1		T896	1		T522	2
values[95]	55	1			T922	1		T896	1		T522	2
values[96]	57	1			T922	1		T896	1		T522	2
values[97]	64	1			T922	1		T896	1		T522	2
values[98]	64	1			T922	2		T896	1		T522	2
values[99]	74	1			T922	6		T896	1		T522	2
values[100]	69	1			T922	3		T896	1		T522	2
values[101]	82	1			T922	6		T896	1		T522	2
values[102]	81	1			T922	10		T896	1		T522	2
values[103]	82	1			T922	5		T896	1		T522	2
values[104]	89	1			T922	3		T896	1		T522	2
values[105]	81	1			T922	4		T896	1		T522	2
values[106]	83	1			T922	4		T896	1		T522	2
values[107]	75	1			T922	1		T896	1		T522	2
values[108]	90	1			T922	5		T896	1		T522	2
values[109]	89	1			T922	5		T896	1		T522	2
values[110]	78	1			T922	3		T896	1		T522	2
values[111]	98	1			T922	2		T896	1		T522	2
values[112]	104	1			T922	1		T896	1		T522	2
values[113]	83	1			T922	1		T896	1		T522	3
values[114]	106	1			T922	3		T896	1		T522	7
values[115]	82	1			T922	1		T896	4		T522	2
values[116]	81	1			T922	1		T896	2		T522	2
values[117]	83	1			T922	1		T896	1		T522	3
values[118]	110	1			T922	5		T896	2		T522	3
values[119]	92	1			T922	2		T896	1		T522	3
values[120]	107	1			T922	1		T896	2		T522	4
values[121]	105	1			T922	4		T896	1		T522	3
values[122]	105	1			T922	2		T896	1		T522	4
values[123]	108	1			T922	3		T896	1		T522	4
values[124]	176	1			T922	3		T896	2		T522	6
values[125]	273	1			T922	3		T896	1		T522	5
values[126]	848	1			T922	9		T896	21		T522	46
values[127]	4202	1			T922	83		T896	132		T522	304
values[128]	7303	1			T922	183		T896	155		T522	411