Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	455	1			T84	1		T261	2		T494	1
all_values[1]	509	1			T84	1		T261	1		T494	2
all_values[2]	476	1			T84	1		T87	1		T494	2
all_values[3]	506	1			T261	1		T494	2		T540	1
all_values[4]	454	1			T84	1		T494	5		T540	1
all_values[5]	474	1			T84	1		T494	3		T454	2
all_values[6]	460	1			T84	1		T87	1		T494	3
all_values[7]	449	1			T261	1		T540	1		T505	3
all_values[8]	452	1			T84	2		T87	1		T494	1
all_values[9]	453	1			T84	1		T494	2		T454	2
all_values[10]	432	1			T261	1		T539	1		T492	1
all_values[11]	479	1			T84	2		T87	1		T549	2
all_values[12]	466	1			T84	4		T87	1		T539	1
all_values[13]	493	1			T84	1		T539	1		T494	3
all_values[14]	453	1			T84	1		T261	1		T494	1
all_values[15]	443	1			T87	1		T494	1		T505	1
all_values[16]	477	1			T505	1		T752	1		T741	2
all_values[17]	464	1			T84	1		T494	2		T454	1
all_values[18]	482	1			T84	1		T87	1		T492	1
all_values[19]	453	1			T261	1		T492	1		T494	2
all_values[20]	427	1			T84	1		T87	1		T261	1
all_values[21]	438	1			T84	1		T87	1		T540	1
all_values[22]	484	1			T84	2		T261	1		T539	1
all_values[23]	481	1			T84	2		T494	1		T454	4
all_values[24]	522	1			T84	1		T87	1		T494	4
all_values[25]	455	1			T84	2		T261	1		T494	3
all_values[26]	447	1			T84	2		T494	2		T505	1
all_values[27]	490	1			T492	1		T494	1		T454	1
all_values[28]	457	1			T84	1		T494	1		T752	1
all_values[29]	434	1			T84	1		T87	2		T261	1
all_values[30]	448	1			T84	2		T494	2		T549	1
all_values[31]	455	1			T84	1		T494	4		T549	1
all_values[32]	457	1			T84	3		T87	2		T261	1
all_values[33]	451	1			T261	2		T539	2		T494	3
all_values[34]	520	1			T84	1		T261	1		T539	1
all_values[35]	500	1			T539	1		T494	5		T549	2
all_values[36]	512	1			T84	2		T505	1		T454	1
all_values[37]	474	1			T84	1		T87	1		T494	2
all_values[38]	460	1			T87	2		T261	1		T494	5
all_values[39]	468	1			T84	1		T539	1		T494	1
all_values[40]	458	1			T84	2		T494	2		T454	5
all_values[41]	436	1			T494	2		T454	5		T619	2
all_values[42]	452	1			T84	1		T87	1		T492	1
all_values[43]	479	1			T84	3		T261	2		T494	1
all_values[44]	483	1			T84	1		T492	3		T494	2
all_values[45]	482	1			T494	1		T549	1		T505	1
all_values[46]	479	1			T84	4		T494	1		T540	1
all_values[47]	484	1			T87	1		T492	2		T494	3
all_values[48]	474	1			T84	1		T492	1		T494	2
all_values[49]	465	1			T84	2		T539	2		T494	2