Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3624	1			T84	22		T261	5		T494	10
all_values[1]	3594	1			T84	23		T261	6		T494	7
all_values[2]	3700	1			T84	15		T261	7		T494	11
all_values[3]	3618	1			T84	12		T261	6		T494	9
all_values[4]	3596	1			T84	25		T261	8		T494	9
all_values[5]	3645	1			T84	19		T261	6		T494	15
all_values[6]	3612	1			T84	15		T261	8		T494	11
all_values[7]	3506	1			T84	12		T261	10		T494	8
all_values[8]	3590	1			T84	18		T261	5		T494	7
all_values[9]	3540	1			T84	12		T261	6		T494	11
all_values[10]	3589	1			T84	20		T261	2		T494	13
all_values[11]	3610	1			T84	13		T261	5		T494	11
all_values[12]	3610	1			T84	15		T261	6		T494	12
all_values[13]	3536	1			T84	22		T261	2		T494	12
all_values[14]	3615	1			T84	12		T261	7		T494	6
all_values[15]	3624	1			T84	15		T494	8		T540	1
all_values[16]	3657	1			T84	17		T261	6		T494	9
all_values[17]	3565	1			T84	16		T261	7		T494	14
all_values[18]	3538	1			T84	14		T261	3		T494	2
all_values[19]	3582	1			T84	22		T261	6		T494	9
all_values[20]	3604	1			T84	14		T261	7		T494	10
all_values[21]	3651	1			T84	19		T261	3		T494	8
all_values[22]	3648	1			T84	17		T261	5		T494	8
all_values[23]	3761	1			T84	20		T261	5		T494	16
all_values[24]	3603	1			T84	22		T261	5		T494	8
all_values[25]	3502	1			T84	20		T261	6		T494	13
all_values[26]	3522	1			T84	18		T261	6		T494	15
all_values[27]	3674	1			T84	22		T261	3		T494	9
all_values[28]	3648	1			T84	13		T261	6		T494	12
all_values[29]	3625	1			T84	16		T261	6		T494	6
all_values[30]	3553	1			T84	21		T261	9		T494	10
all_values[31]	3568	1			T84	13		T261	4		T494	10
all_values[32]	3544	1			T84	19		T261	7		T494	11
all_values[33]	3584	1			T84	14		T261	7		T494	12
all_values[34]	3548	1			T84	15		T261	5		T494	13
all_values[35]	3632	1			T84	16		T261	4		T494	8
all_values[36]	3618	1			T84	16		T261	5		T494	11
all_values[37]	3642	1			T84	22		T261	7		T494	9
all_values[38]	3634	1			T84	13		T261	5		T494	10
all_values[39]	3517	1			T84	20		T261	5		T494	19
all_values[40]	3650	1			T84	18		T261	2		T494	10
all_values[41]	3679	1			T84	18		T261	5		T494	9
all_values[42]	3498	1			T84	15		T261	6		T494	6
all_values[43]	3635	1			T84	12		T261	9		T494	10
all_values[44]	3662	1			T84	19		T261	2		T494	13
all_values[45]	3543	1			T84	21		T261	6		T494	13
all_values[46]	3613	1			T84	16		T261	5		T494	11
all_values[47]	3614	1			T84	20		T261	6		T494	12
all_values[48]	3520	1			T84	16		T261	3		T494	15
all_values[49]	3580	1			T84	19		T261	3		T494	8
all_values[50]	3640	1			T84	18		T261	3		T494	12
all_values[51]	3554	1			T84	28		T261	3		T494	11
all_values[52]	3558	1			T84	23		T261	3		T494	6
all_values[53]	3553	1			T84	17		T261	10		T494	8
all_values[54]	3655	1			T84	22		T261	1		T494	14
all_values[55]	3659	1			T84	19		T261	6		T494	9
all_values[56]	3589	1			T84	17		T261	4		T494	14
all_values[57]	3691	1			T84	26		T261	4		T494	12
all_values[58]	3715	1			T84	18		T261	3		T494	5
all_values[59]	3482	1			T84	29		T261	7		T494	18
all_values[60]	3596	1			T84	11		T261	6		T494	8
all_values[61]	3612	1			T84	16		T261	4		T494	12
all_values[62]	3509	1			T84	22		T261	9		T494	11
all_values[63]	3495	1			T84	21		T261	4		T494	12