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LINE 133
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T9 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T61,T62,T63 |
LINE 420
EXPRESSION (sleep_en_i & ((~sleep_en_q)))
-----1---- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[0].q ? mio_out_retreg_q[0] : periph_data_mux[reg2hw.mio_outsel[0].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[1].q ? mio_out_retreg_q[1] : periph_data_mux[reg2hw.mio_outsel[1].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[2].q ? mio_out_retreg_q[2] : periph_data_mux[reg2hw.mio_outsel[2].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[3].q ? mio_out_retreg_q[3] : periph_data_mux[reg2hw.mio_outsel[3].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[4].q ? mio_out_retreg_q[4] : periph_data_mux[reg2hw.mio_outsel[4].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[5].q ? mio_out_retreg_q[5] : periph_data_mux[reg2hw.mio_outsel[5].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[6].q ? mio_out_retreg_q[6] : periph_data_mux[reg2hw.mio_outsel[6].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[7].q ? mio_out_retreg_q[7] : periph_data_mux[reg2hw.mio_outsel[7].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[8].q ? mio_out_retreg_q[8] : periph_data_mux[reg2hw.mio_outsel[8].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[9].q ? mio_out_retreg_q[9] : periph_data_mux[reg2hw.mio_outsel[9].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[10].q ? mio_out_retreg_q[10] : periph_data_mux[reg2hw.mio_outsel[10].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[11].q ? mio_out_retreg_q[11] : periph_data_mux[reg2hw.mio_outsel[11].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[12].q ? mio_out_retreg_q[12] : periph_data_mux[reg2hw.mio_outsel[12].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[13].q ? mio_out_retreg_q[13] : periph_data_mux[reg2hw.mio_outsel[13].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[14].q ? mio_out_retreg_q[14] : periph_data_mux[reg2hw.mio_outsel[14].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[15].q ? mio_out_retreg_q[15] : periph_data_mux[reg2hw.mio_outsel[15].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[16].q ? mio_out_retreg_q[16] : periph_data_mux[reg2hw.mio_outsel[16].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[17].q ? mio_out_retreg_q[17] : periph_data_mux[reg2hw.mio_outsel[17].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[18].q ? mio_out_retreg_q[18] : periph_data_mux[reg2hw.mio_outsel[18].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[19].q ? mio_out_retreg_q[19] : periph_data_mux[reg2hw.mio_outsel[19].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[20].q ? mio_out_retreg_q[20] : periph_data_mux[reg2hw.mio_outsel[20].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[21].q ? mio_out_retreg_q[21] : periph_data_mux[reg2hw.mio_outsel[21].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[22].q ? mio_out_retreg_q[22] : periph_data_mux[reg2hw.mio_outsel[22].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[23].q ? mio_out_retreg_q[23] : periph_data_mux[reg2hw.mio_outsel[23].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[24].q ? mio_out_retreg_q[24] : periph_data_mux[reg2hw.mio_outsel[24].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[25].q ? mio_out_retreg_q[25] : periph_data_mux[reg2hw.mio_outsel[25].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[26].q ? mio_out_retreg_q[26] : periph_data_mux[reg2hw.mio_outsel[26].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[27].q ? mio_out_retreg_q[27] : periph_data_mux[reg2hw.mio_outsel[27].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[28].q ? mio_out_retreg_q[28] : periph_data_mux[reg2hw.mio_outsel[28].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[29].q ? mio_out_retreg_q[29] : periph_data_mux[reg2hw.mio_outsel[29].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[30].q ? mio_out_retreg_q[30] : periph_data_mux[reg2hw.mio_outsel[30].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[31].q ? mio_out_retreg_q[31] : periph_data_mux[reg2hw.mio_outsel[31].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[32].q ? mio_out_retreg_q[32] : periph_data_mux[reg2hw.mio_outsel[32].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[33].q ? mio_out_retreg_q[33] : periph_data_mux[reg2hw.mio_outsel[33].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[34].q ? mio_out_retreg_q[34] : periph_data_mux[reg2hw.mio_outsel[34].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[35].q ? mio_out_retreg_q[35] : periph_data_mux[reg2hw.mio_outsel[35].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[36].q ? mio_out_retreg_q[36] : periph_data_mux[reg2hw.mio_outsel[36].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[37].q ? mio_out_retreg_q[37] : periph_data_mux[reg2hw.mio_outsel[37].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[38].q ? mio_out_retreg_q[38] : periph_data_mux[reg2hw.mio_outsel[38].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[39].q ? mio_out_retreg_q[39] : periph_data_mux[reg2hw.mio_outsel[39].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[40].q ? mio_out_retreg_q[40] : periph_data_mux[reg2hw.mio_outsel[40].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[41].q ? mio_out_retreg_q[41] : periph_data_mux[reg2hw.mio_outsel[41].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[42].q ? mio_out_retreg_q[42] : periph_data_mux[reg2hw.mio_outsel[42].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[43].q ? mio_out_retreg_q[43] : periph_data_mux[reg2hw.mio_outsel[43].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[44].q ? mio_out_retreg_q[44] : periph_data_mux[reg2hw.mio_outsel[44].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[45].q ? mio_out_retreg_q[45] : periph_data_mux[reg2hw.mio_outsel[45].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 479
EXPRESSION (reg2hw.mio_pad_sleep_status[46].q ? mio_out_retreg_q[46] : periph_data_mux[reg2hw.mio_outsel[46].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[0].q ? mio_oe_retreg_q[0] : periph_oe_mux[reg2hw.mio_outsel[0].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[1].q ? mio_oe_retreg_q[1] : periph_oe_mux[reg2hw.mio_outsel[1].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[2].q ? mio_oe_retreg_q[2] : periph_oe_mux[reg2hw.mio_outsel[2].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[3].q ? mio_oe_retreg_q[3] : periph_oe_mux[reg2hw.mio_outsel[3].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[4].q ? mio_oe_retreg_q[4] : periph_oe_mux[reg2hw.mio_outsel[4].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[5].q ? mio_oe_retreg_q[5] : periph_oe_mux[reg2hw.mio_outsel[5].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[6].q ? mio_oe_retreg_q[6] : periph_oe_mux[reg2hw.mio_outsel[6].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[7].q ? mio_oe_retreg_q[7] : periph_oe_mux[reg2hw.mio_outsel[7].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[8].q ? mio_oe_retreg_q[8] : periph_oe_mux[reg2hw.mio_outsel[8].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[9].q ? mio_oe_retreg_q[9] : periph_oe_mux[reg2hw.mio_outsel[9].q])
----------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[10].q ? mio_oe_retreg_q[10] : periph_oe_mux[reg2hw.mio_outsel[10].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[11].q ? mio_oe_retreg_q[11] : periph_oe_mux[reg2hw.mio_outsel[11].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[12].q ? mio_oe_retreg_q[12] : periph_oe_mux[reg2hw.mio_outsel[12].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[13].q ? mio_oe_retreg_q[13] : periph_oe_mux[reg2hw.mio_outsel[13].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[14].q ? mio_oe_retreg_q[14] : periph_oe_mux[reg2hw.mio_outsel[14].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[15].q ? mio_oe_retreg_q[15] : periph_oe_mux[reg2hw.mio_outsel[15].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[16].q ? mio_oe_retreg_q[16] : periph_oe_mux[reg2hw.mio_outsel[16].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[17].q ? mio_oe_retreg_q[17] : periph_oe_mux[reg2hw.mio_outsel[17].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[18].q ? mio_oe_retreg_q[18] : periph_oe_mux[reg2hw.mio_outsel[18].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[19].q ? mio_oe_retreg_q[19] : periph_oe_mux[reg2hw.mio_outsel[19].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[20].q ? mio_oe_retreg_q[20] : periph_oe_mux[reg2hw.mio_outsel[20].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[21].q ? mio_oe_retreg_q[21] : periph_oe_mux[reg2hw.mio_outsel[21].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[22].q ? mio_oe_retreg_q[22] : periph_oe_mux[reg2hw.mio_outsel[22].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[23].q ? mio_oe_retreg_q[23] : periph_oe_mux[reg2hw.mio_outsel[23].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[24].q ? mio_oe_retreg_q[24] : periph_oe_mux[reg2hw.mio_outsel[24].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[25].q ? mio_oe_retreg_q[25] : periph_oe_mux[reg2hw.mio_outsel[25].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[26].q ? mio_oe_retreg_q[26] : periph_oe_mux[reg2hw.mio_outsel[26].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[27].q ? mio_oe_retreg_q[27] : periph_oe_mux[reg2hw.mio_outsel[27].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[28].q ? mio_oe_retreg_q[28] : periph_oe_mux[reg2hw.mio_outsel[28].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[29].q ? mio_oe_retreg_q[29] : periph_oe_mux[reg2hw.mio_outsel[29].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[30].q ? mio_oe_retreg_q[30] : periph_oe_mux[reg2hw.mio_outsel[30].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[31].q ? mio_oe_retreg_q[31] : periph_oe_mux[reg2hw.mio_outsel[31].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[32].q ? mio_oe_retreg_q[32] : periph_oe_mux[reg2hw.mio_outsel[32].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[33].q ? mio_oe_retreg_q[33] : periph_oe_mux[reg2hw.mio_outsel[33].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[34].q ? mio_oe_retreg_q[34] : periph_oe_mux[reg2hw.mio_outsel[34].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[35].q ? mio_oe_retreg_q[35] : periph_oe_mux[reg2hw.mio_outsel[35].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[36].q ? mio_oe_retreg_q[36] : periph_oe_mux[reg2hw.mio_outsel[36].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[37].q ? mio_oe_retreg_q[37] : periph_oe_mux[reg2hw.mio_outsel[37].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[38].q ? mio_oe_retreg_q[38] : periph_oe_mux[reg2hw.mio_outsel[38].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[39].q ? mio_oe_retreg_q[39] : periph_oe_mux[reg2hw.mio_outsel[39].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[40].q ? mio_oe_retreg_q[40] : periph_oe_mux[reg2hw.mio_outsel[40].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[41].q ? mio_oe_retreg_q[41] : periph_oe_mux[reg2hw.mio_outsel[41].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[42].q ? mio_oe_retreg_q[42] : periph_oe_mux[reg2hw.mio_outsel[42].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[43].q ? mio_oe_retreg_q[43] : periph_oe_mux[reg2hw.mio_outsel[43].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[44].q ? mio_oe_retreg_q[44] : periph_oe_mux[reg2hw.mio_outsel[44].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[45].q ? mio_oe_retreg_q[45] : periph_oe_mux[reg2hw.mio_outsel[45].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 483
EXPRESSION (reg2hw.mio_pad_sleep_status[46].q ? mio_oe_retreg_q[46] : periph_oe_mux[reg2hw.mio_outsel[46].q])
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[0].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[0].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[0].q == 2'h2) ? 1'b0 : mio_out[0])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T13 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[0].q == 2'b0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T13 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[0].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[0].q == 2'h2) ? 1'b0 : mio_out[0]))
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T20 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[0].q == 2'b1)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T20 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[0].q == 2'h2) ? 1'b0 : mio_out[0])
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T9 |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[0].q == 2'h2)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T9 |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[1].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[1].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[1].q == 2'h2) ? 1'b0 : mio_out[1])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T8,T11 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[1].q == 2'b0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T8,T11 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[1].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[1].q == 2'h2) ? 1'b0 : mio_out[1]))
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T9 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[1].q == 2'b1)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T9 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[1].q == 2'h2) ? 1'b0 : mio_out[1])
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[1].q == 2'h2)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[2].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[2].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[2].q == 2'h2) ? 1'b0 : mio_out[2])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T8,T11,T12 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[2].q == 2'b0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T8,T11,T12 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[2].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[2].q == 2'h2) ? 1'b0 : mio_out[2]))
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T13 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[2].q == 2'b1)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T13 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[2].q == 2'h2) ? 1'b0 : mio_out[2])
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[2].q == 2'h2)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[3].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[3].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[3].q == 2'h2) ? 1'b0 : mio_out[3])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T8,T11,T12 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[3].q == 2'b0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T8,T11,T12 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[3].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[3].q == 2'h2) ? 1'b0 : mio_out[3]))
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[3].q == 2'b1)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[3].q == 2'h2) ? 1'b0 : mio_out[3])
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[3].q == 2'h2)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[4].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[4].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[4].q == 2'h2) ? 1'b0 : mio_out[4])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T9 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[4].q == 2'b0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T9 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[4].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[4].q == 2'h2) ? 1'b0 : mio_out[4]))
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[4].q == 2'b1)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[4].q == 2'h2) ? 1'b0 : mio_out[4])
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[4].q == 2'h2)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[5].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[5].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[5].q == 2'h2) ? 1'b0 : mio_out[5])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[5].q == 2'b0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[5].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[5].q == 2'h2) ? 1'b0 : mio_out[5]))
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T9 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[5].q == 2'b1)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T9 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[5].q == 2'h2) ? 1'b0 : mio_out[5])
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[5].q == 2'h2)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[6].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[6].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[6].q == 2'h2) ? 1'b0 : mio_out[6])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T8,T11,T12 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[6].q == 2'b0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T8,T11,T12 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[6].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[6].q == 2'h2) ? 1'b0 : mio_out[6]))
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T20 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[6].q == 2'b1)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T20 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[6].q == 2'h2) ? 1'b0 : mio_out[6])
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[6].q == 2'h2)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[7].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[7].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[7].q == 2'h2) ? 1'b0 : mio_out[7])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T9 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[7].q == 2'b0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T12,T9 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[7].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[7].q == 2'h2) ? 1'b0 : mio_out[7]))
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[7].q == 2'b1)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T11,T12 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[7].q == 2'h2) ? 1'b0 : mio_out[7])
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[7].q == 2'h2)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[8].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[8].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[8].q == 2'h2) ? 1'b0 : mio_out[8])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T21 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[8].q == 2'b0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T21 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[8].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[8].q == 2'h2) ? 1'b0 : mio_out[8]))
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T8,T9,T20 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[8].q == 2'b1)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T8,T9,T20 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[8].q == 2'h2) ? 1'b0 : mio_out[8])
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[8].q == 2'h2)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[9].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[9].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[9].q == 2'h2) ? 1'b0 : mio_out[9])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T9 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[9].q == 2'b0)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T9 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[9].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[9].q == 2'h2) ? 1'b0 : mio_out[9]))
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[9].q == 2'b1)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[9].q == 2'h2) ? 1'b0 : mio_out[9])
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T8 |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[9].q == 2'h2)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T8 |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[10].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[10].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[10].q == 2'h2) ? 1'b0 : mio_out[10])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T20,T21 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[10].q == 2'b0)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T20,T21 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[10].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[10].q == 2'h2) ? 1'b0 : mio_out[10]))
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[10].q == 2'b1)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[10].q == 2'h2) ? 1'b0 : mio_out[10])
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T9 |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[10].q == 2'h2)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T9 |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[11].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[11].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[11].q == 2'h2) ? 1'b0 : mio_out[11])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T21 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[11].q == 2'b0)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T21 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[11].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[11].q == 2'h2) ? 1'b0 : mio_out[11]))
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[11].q == 2'b1)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[11].q == 2'h2) ? 1'b0 : mio_out[11])
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[11].q == 2'h2)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[12].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[12].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[12].q == 2'h2) ? 1'b0 : mio_out[12])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[12].q == 2'b0)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20,T21 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[12].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[12].q == 2'h2) ? 1'b0 : mio_out[12]))
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Not Covered | |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[12].q == 2'b1)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Not Covered | |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[12].q == 2'h2) ? 1'b0 : mio_out[12])
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[12].q == 2'h2)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[13].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[13].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[13].q == 2'h2) ? 1'b0 : mio_out[13])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[13].q == 2'b0)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T20 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[13].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[13].q == 2'h2) ? 1'b0 : mio_out[13]))
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Not Covered | |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[13].q == 2'b1)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Not Covered | |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[13].q == 2'h2) ? 1'b0 : mio_out[13])
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[13].q == 2'h2)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
EXPRESSION
Number Term
1 (reg2hw.mio_pad_sleep_mode[14].q == 2'b0) ? 1'b0 : ((reg2hw.mio_pad_sleep_mode[14].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[14].q == 2'h2) ? 1'b0 : mio_out[14])))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T20,T21 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[14].q == 2'b0)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T20,T21 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[14].q == 2'b1) ? 1'b1 : ((reg2hw.mio_pad_sleep_mode[14].q == 2'h2) ? 1'b0 : mio_out[14]))
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T8 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[14].q == 2'b1)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T8 |
LINE 492
SUB-EXPRESSION ((reg2hw.mio_pad_sleep_mode[14].q == 2'h2) ? 1'b0 : mio_out[14])
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |
LINE 492
SUB-EXPRESSION (reg2hw.mio_pad_sleep_mode[14].q == 2'h2)
--------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Covered | T4,T5,T6 |