Unified Coverage Report :: Cond split page

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 LINE       32819
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_30_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T65,T56,T336

 LINE       32820
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_31_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T65,T336,T324

 LINE       32821
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_32_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T65,T336,T324

 LINE       32822
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_33_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T65,T336,T324

 LINE       32823
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_34_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T65,T336,T324

 LINE       32824
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_35_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T65,T336,T324

 LINE       32825
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_36_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T65,T336,T324

 LINE       32826
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_37_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T65,T336,T324

 LINE       32827
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_38_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T123,T65,T68

 LINE       32828
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_39_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T123,T65,T68

 LINE       32829
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_40_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T530,T125,T531

 LINE       32830
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_41_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T530,T125,T532

 LINE       32831
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_42_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T125,T87,T136

 LINE       32832
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_43_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T123,T65,T68

 LINE       32833
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_44_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T123,T65,T68

 LINE       32834
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_45_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T123,T65,T68

 LINE       32835
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_46_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T123,T65,T68

 LINE       32836
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T44

 LINE       32837
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T44

 LINE       32838
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T69,T56,T18

 LINE       32839
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T125,T23

 LINE       32840
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T68,T69,T325

 LINE       32841
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T123,T65,T56

 LINE       32842
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T123,T65,T56

 LINE       32843
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T125,T9,T84

 LINE       32844
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T125,T9,T85

 LINE       32845
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T125,T9,T84

 LINE       32846
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T123,T65,T56

 LINE       32847
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T123,T65,T56

 LINE       32848
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T123,T65,T336

 LINE       32849
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T123,T65,T56

 LINE       32850
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T56,T18,T108

 LINE       32851
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T56,T18,T108

 LINE       32852
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_0_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T44

 LINE       32853
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_1_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T44

 LINE       32854
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_2_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T108,T235,T533

 LINE       32855
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_3_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T56,T111,T410

 LINE       32856
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_4_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T56,T18,T111

 LINE       32857
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_5_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T294,T23

 LINE       32858
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_6_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T294,T84,T85

 LINE       32859
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_7_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T294,T84,T261

 LINE       32860
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_8_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T56,T18,T111

 LINE       32861
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_9_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T56,T18,T111

 LINE       32862
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_10_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T111,T255,T366

 LINE       32863
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_11_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T56,T18,T111

 LINE       32864
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_12_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T56,T18,T111

 LINE       32865
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_13_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T56,T18,T111

 LINE       32866
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_14_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T56,T18,T111

 LINE       32867
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_15_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T294,T24,T46

 LINE       32868
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T111,T255,T366

 LINE       32869
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T56,T358

 LINE       32870
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T56,T18

 LINE       32871
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T294,T11

 LINE       32872
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T294,T11

 LINE       32873
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T294,T11

 LINE       32874
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T56,T18

 LINE       32875
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T56,T18

 LINE       32876
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T358,T534

 LINE       32877
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T56,T18

 LINE       32878
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T56,T18

 LINE       32879
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T56,T18

 LINE       32880
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T56,T18

 LINE       32881
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32882
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T358,T534

 LINE       32883
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32884
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32885
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32886
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32887
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32888
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32889
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32890
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32891
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32892
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32893
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32894
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32895
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32896
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32897
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32898
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32899
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32900
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32901
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32902
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32903
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32904
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32905
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32906
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32907
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32908
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32909
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32910
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32911
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32912
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32913
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32914
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32915
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32916
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32917
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32918
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32919
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32920
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32921
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32922
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32923
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32924
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32925
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32926
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32927
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32928
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32929
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32930
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32931
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32932
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32933
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32934
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32935
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32936
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32937
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32938
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32939
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32940
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32941
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32942
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32943
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32944
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32945
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32946
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32947
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32948
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T193,T8

 LINE       32949
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32950
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32951
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32952
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32953
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32954
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32955
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32956
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32957
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32958
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32959
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32960
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32961
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32962
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32963
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32964
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T11

 LINE       32965
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T11

 LINE       32966
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T11

 LINE       32967
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T11

 LINE       32968
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T11

 LINE       32969
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T11

 LINE       32970
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T11

 LINE       32971
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T11

 LINE       32972
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32973
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32974
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32975
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32976
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32977
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32978
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32979
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32980
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32981
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32982
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32983
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32984
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32985
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32986
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32987
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32988
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32989
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32990
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32991
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9

 LINE       32992
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T19,T8,T9