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 LINE       33107
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT83,T84,T85
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       33107
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT84,T85,T134

 LINE       33107
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT83,T84,T85

 LINE       33107
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT87,T136,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT84,T87,T541

 LINE       33107
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT84,T87,T135

 LINE       33107
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT84,T87,T136

 LINE       33107
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT84,T87,T136

 LINE       33107
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT85,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT85,T87,T136

 LINE       33107
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT83,T84,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T6,T44
11CoveredT84,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T6,T44
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T161
11CoveredT83,T84,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T25
11CoveredT84,T87,T136

 LINE       33107
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T136

 LINE       33107
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T186,T68
11CoveredT85,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T541

 LINE       33107
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT123,T65,T166
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT123,T65,T166
11CoveredT84,T87,T136

 LINE       33107
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T134,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T136

 LINE       33107
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT83,T84,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[61] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T136

 LINE       33107
 SUB-EXPRESSION (addr_hit[62] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T136

 LINE       33107
 SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[64] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT261,T537,T538

 LINE       33107
 SUB-EXPRESSION (addr_hit[65] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT261,T537,T516

 LINE       33107
 SUB-EXPRESSION (addr_hit[66] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T261,T537

 LINE       33107
 SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT261,T537,T539

 LINE       33107
 SUB-EXPRESSION (addr_hit[68] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[69] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T85,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT87,T261,T537

 LINE       33107
 SUB-EXPRESSION (addr_hit[71] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[72] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[73] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T69,T56
11CoveredT87,T136,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[74] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT136,T261,T536

 LINE       33107
 SUB-EXPRESSION (addr_hit[75] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T261,T536

 LINE       33107
 SUB-EXPRESSION (addr_hit[76] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T261,T537

 LINE       33107
 SUB-EXPRESSION (addr_hit[77] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT261,T536,T538

 LINE       33107
 SUB-EXPRESSION (addr_hit[78] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[79] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[80] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT136,T261,T538

 LINE       33107
 SUB-EXPRESSION (addr_hit[81] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT134,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[82] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT84,T261,T538

 LINE       33107
 SUB-EXPRESSION (addr_hit[83] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T177
11CoveredT85,T261,T537

 LINE       33107
 SUB-EXPRESSION (addr_hit[84] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T85,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[85] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[86] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT134,T261,T538

 LINE       33107
 SUB-EXPRESSION (addr_hit[87] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T541

 LINE       33107
 SUB-EXPRESSION (addr_hit[88] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT261,T537,T536

 LINE       33107
 SUB-EXPRESSION (addr_hit[89] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT134,T261,T537

 LINE       33107
 SUB-EXPRESSION (addr_hit[90] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT261,T537,T544

 LINE       33107
 SUB-EXPRESSION (addr_hit[91] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[92] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[93] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T68,T56
11CoveredT84,T136,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[94] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[95] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T65,T56
11CoveredT84,T261,T537

 LINE       33107
 SUB-EXPRESSION (addr_hit[96] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T136

 LINE       33107
 SUB-EXPRESSION (addr_hit[97] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T261,T537

 LINE       33107
 SUB-EXPRESSION (addr_hit[98] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T134,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[99] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT87,T261,T537

 LINE       33107
 SUB-EXPRESSION (addr_hit[100] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT261,T537,T538

 LINE       33107
 SUB-EXPRESSION (addr_hit[101] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T6,T44
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[102] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T161
11CoveredT84,T261,T537

 LINE       33107
 SUB-EXPRESSION (addr_hit[103] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T25
11CoveredT84,T87,T136

 LINE       33107
 SUB-EXPRESSION (addr_hit[104] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[105] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T261,T536

 LINE       33107
 SUB-EXPRESSION (addr_hit[106] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T261,T538

 LINE       33107
 SUB-EXPRESSION (addr_hit[107] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT261,T536,T539

 LINE       33107
 SUB-EXPRESSION (addr_hit[108] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[109] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T186,T68
11CoveredT261,T538,T539

 LINE       33107
 SUB-EXPRESSION (addr_hit[110] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T261,T537

 LINE       33107
 SUB-EXPRESSION (addr_hit[111] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[112] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T85,T135

 LINE       33107
 SUB-EXPRESSION (addr_hit[113] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T261,T539

 LINE       33107
 SUB-EXPRESSION (addr_hit[114] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T85,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[115] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT87,T261,T537

 LINE       33107
 SUB-EXPRESSION (addr_hit[116] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T25
11CoveredT84,T261,T537

 LINE       33107
 SUB-EXPRESSION (addr_hit[117] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T134,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[118] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT87,T261,T538

 LINE       33107
 SUB-EXPRESSION (addr_hit[119] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[120] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T161
11CoveredT83,T84,T87

 LINE       33107
 SUB-EXPRESSION (addr_hit[121] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T136,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[122] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T136,T261

 LINE       33107
 SUB-EXPRESSION (addr_hit[123] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT261,T537,T539

 LINE       33107
 SUB-EXPRESSION (addr_hit[124] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT65,T56,T336
11CoveredT84,T87,T541
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%