Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139497	1			T75	206		T76	58		T77	465
values[2]	7814	1			T75	1		T76	1		T77	4
values[3]	2659	1			T428	3		T463	34		T466	1
values[4]	1620	1			T428	2		T463	23		T466	1
values[5]	1260	1			T428	2		T463	9		T466	1
values[6]	921	1			T428	2		T466	1		T837	5
values[7]	752	1			T428	1		T466	1		T837	7
values[8]	637	1			T428	4		T466	1		T837	5
values[9]	553	1			T428	3		T466	1		T837	1
values[10]	509	1			T428	3		T466	1		T837	2
values[11]	470	1			T428	3		T466	1		T837	4
values[12]	427	1			T428	5		T466	1		T837	2
values[13]	437	1			T428	6		T466	1		T837	5
values[14]	395	1			T428	6		T466	1		T837	1
values[15]	387	1			T428	5		T466	1		T837	4
values[16]	408	1			T428	2		T466	1		T837	1
values[17]	393	1			T428	2		T466	1		T837	1
values[18]	345	1			T428	5		T466	1		T837	1
values[19]	359	1			T428	5		T466	1		T837	2
values[20]	389	1			T428	9		T466	1		T837	2
values[21]	400	1			T428	9		T466	1		T837	1
values[22]	420	1			T428	7		T466	1		T837	7
values[23]	383	1			T428	1		T466	1		T837	3
values[24]	367	1			T428	2		T466	1		T837	2
values[25]	371	1			T428	4		T466	1		T837	1
values[26]	365	1			T428	5		T466	1		T837	3
values[27]	384	1			T428	5		T466	1		T837	6
values[28]	347	1			T428	2		T466	1		T837	4
values[29]	396	1			T428	1		T466	1		T837	7
values[30]	383	1			T428	3		T466	1		T837	12
values[31]	408	1			T428	5		T466	1		T837	10
values[32]	352	1			T428	3		T466	1		T837	1
values[33]	343	1			T428	1		T466	1		T837	2
values[34]	319	1			T428	2		T466	1		T837	1
values[35]	366	1			T428	2		T466	1		T837	4
values[36]	354	1			T428	2		T466	1		T837	1
values[37]	362	1			T428	1		T466	1		T837	3
values[38]	357	1			T428	1		T466	1		T837	4
values[39]	364	1			T428	3		T466	1		T837	4
values[40]	332	1			T428	3		T466	1		T837	1
values[41]	357	1			T428	3		T466	1		T837	1
values[42]	316	1			T428	5		T466	1		T837	6
values[43]	323	1			T428	2		T466	1		T837	4
values[44]	325	1			T428	2		T466	1		T837	4
values[45]	310	1			T428	2		T466	1		T837	5
values[46]	310	1			T428	1		T466	1		T837	2
values[47]	302	1			T428	4		T466	1		T837	4
values[48]	283	1			T428	7		T466	1		T837	3
values[49]	306	1			T428	4		T466	1		T837	1
values[50]	306	1			T428	6		T466	1		T837	6
values[51]	264	1			T428	4		T466	1		T837	3
values[52]	292	1			T428	1		T466	1		T837	5
values[53]	311	1			T428	5		T466	2		T837	6
values[54]	257	1			T428	3		T466	1		T837	7
values[55]	309	1			T428	3		T466	1		T837	4
values[56]	234	1			T428	2		T466	1		T837	1
values[57]	285	1			T428	1		T466	1		T837	7
values[58]	280	1			T428	1		T466	1		T837	5
values[59]	253	1			T428	2		T466	1		T837	9
values[60]	280	1			T428	4		T466	1		T837	13
values[61]	267	1			T428	1		T466	1		T837	1
values[62]	249	1			T428	1		T466	1		T837	5
values[63]	242	1			T428	4		T466	1		T837	3
values[64]	268	1			T428	3		T466	1		T837	3
values[65]	187	1			T428	6		T466	1		T837	3
values[66]	177	1			T428	9		T466	1		T837	1
values[67]	237	1			T428	4		T466	1		T837	5
values[68]	230	1			T428	4		T466	1		T837	1
values[69]	174	1			T428	1		T466	1		T837	2
values[70]	138	1			T428	7		T466	1		T837	2
values[71]	147	1			T428	5		T466	1		T837	2
values[72]	167	1			T428	2		T466	1		T837	3
values[73]	170	1			T428	2		T466	1		T837	6
values[74]	157	1			T428	4		T466	1		T837	7
values[75]	113	1			T428	2		T466	1		T837	23
values[76]	119	1			T428	1		T466	1		T837	19
values[77]	90	1			T428	2		T466	1		T837	10
values[78]	79	1			T428	3		T466	1		T837	4
values[79]	80	1			T428	3		T466	1		T837	3
values[80]	89	1			T428	1		T466	1		T837	2
values[81]	92	1			T428	3		T466	1		T837	7
values[82]	120	1			T428	5		T466	1		T837	9
values[83]	142	1			T428	1		T466	1		T837	2
values[84]	117	1			T428	2		T466	1		T837	5
values[85]	105	1			T428	1		T466	1		T837	3
values[86]	87	1			T428	2		T466	1		T837	1
values[87]	81	1			T428	1		T466	1		T837	2
values[88]	96	1			T428	1		T466	1		T837	2
values[89]	125	1			T428	3		T466	1		T837	1
values[90]	102	1			T428	3		T466	1		T837	4
values[91]	92	1			T428	3		T466	1		T837	1
values[92]	88	1			T428	4		T466	1		T837	2
values[93]	99	1			T428	8		T466	1		T837	1
values[94]	96	1			T428	3		T466	1		T837	2
values[95]	119	1			T428	2		T466	1		T837	3
values[96]	112	1			T428	5		T466	1		T837	1
values[97]	97	1			T428	5		T466	2		T837	3
values[98]	110	1			T428	2		T466	1		T837	5
values[99]	102	1			T428	1		T466	1		T837	2
values[100]	102	1			T428	3		T466	1		T837	2
values[101]	103	1			T428	2		T466	1		T837	5
values[102]	88	1			T428	4		T466	1		T837	2
values[103]	97	1			T428	2		T466	1		T837	4
values[104]	91	1			T428	4		T466	1		T837	5
values[105]	108	1			T428	5		T466	1		T837	6
values[106]	93	1			T428	3		T466	1		T837	2
values[107]	96	1			T428	3		T466	1		T837	7
values[108]	93	1			T428	3		T466	1		T837	1
values[109]	87	1			T428	3		T466	1		T837	1
values[110]	85	1			T428	5		T466	1		T837	3
values[111]	102	1			T428	2		T466	1		T837	2
values[112]	107	1			T428	4		T466	1		T837	5
values[113]	87	1			T428	3		T466	1		T837	12
values[114]	92	1			T428	8		T466	1		T837	8
values[115]	89	1			T428	9		T466	1		T837	5
values[116]	79	1			T428	4		T466	1		T837	4
values[117]	96	1			T428	1		T466	1		T837	5
values[118]	77	1			T428	2		T466	1		T837	13
values[119]	91	1			T428	3		T466	1		T837	5
values[120]	79	1			T428	2		T466	1		T837	3
values[121]	74	1			T428	3		T466	1		T837	1
values[122]	92	1			T428	3		T466	1		T837	5
values[123]	88	1			T428	2		T466	1		T837	3
values[124]	96	1			T428	7		T466	1		T837	3
values[125]	114	1			T428	13		T466	1		T837	11
values[126]	209	1			T428	19		T466	4		T837	13
values[127]	1059	1			T428	30		T466	33		T837	19
values[128]	8319	1			T428	20		T466	273		T837	9

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	161198	1			T75	229		T76	41		T77	470
values[2]	4146	1			T428	2		T537	1		T438	4
values[3]	1906	1			T428	2		T438	1		T710	9
values[4]	1312	1			T428	1		T710	7		T463	25
values[5]	1159	1			T428	2		T710	19		T463	4
values[6]	1014	1			T428	4		T710	31		T463	4
values[7]	813	1			T428	5		T710	41		T463	5
values[8]	763	1			T428	4		T710	36		T672	11
values[9]	717	1			T428	3		T710	31		T672	7
values[10]	563	1			T428	3		T710	11		T672	5
values[11]	491	1			T428	4		T672	1		T656	7
values[12]	497	1			T428	3		T672	1		T838	10
values[13]	390	1			T428	2		T838	1		T839	1
values[14]	331	1			T428	4		T839	1		T840	1
values[15]	248	1			T428	1		T839	1		T840	1
values[16]	239	1			T428	3		T839	1		T840	1
values[17]	206	1			T428	2		T839	1		T840	1
values[18]	233	1			T428	2		T839	1		T840	1
values[19]	202	1			T428	2		T839	1		T840	1
values[20]	172	1			T428	3		T839	1		T840	1
values[21]	152	1			T428	5		T839	1		T840	1
values[22]	125	1			T428	6		T839	1		T840	1
values[23]	102	1			T428	8		T839	1		T840	1
values[24]	109	1			T428	4		T839	1		T840	1
values[25]	111	1			T428	4		T839	1		T840	1
values[26]	101	1			T428	2		T839	1		T840	1
values[27]	95	1			T428	2		T839	1		T840	1
values[28]	77	1			T428	8		T839	1		T840	1
values[29]	81	1			T428	3		T839	1		T840	1
values[30]	100	1			T428	2		T839	1		T840	1
values[31]	109	1			T428	2		T839	1		T840	1
values[32]	104	1			T428	1		T839	1		T840	1
values[33]	87	1			T428	5		T839	1		T840	1
values[34]	65	1			T428	1		T839	1		T840	1
values[35]	80	1			T428	3		T839	1		T840	1
values[36]	95	1			T428	2		T839	1		T840	1
values[37]	113	1			T428	4		T839	1		T840	1
values[38]	87	1			T428	1		T839	1		T840	1
values[39]	74	1			T428	9		T839	1		T840	1
values[40]	62	1			T428	2		T839	1		T840	1
values[41]	73	1			T428	2		T839	1		T840	1
values[42]	101	1			T428	5		T839	1		T840	1
values[43]	65	1			T428	2		T839	1		T840	1
values[44]	61	1			T428	2		T839	1		T840	1
values[45]	54	1			T428	7		T839	1		T840	1
values[46]	50	1			T428	2		T839	1		T840	1
values[47]	58	1			T428	3		T839	1		T840	1
values[48]	58	1			T428	5		T839	1		T840	1
values[49]	57	1			T428	1		T839	1		T840	1
values[50]	59	1			T428	2		T839	1		T840	1
values[51]	48	1			T428	1		T839	1		T840	1
values[52]	59	1			T428	3		T839	1		T840	1
values[53]	49	1			T428	1		T839	1		T840	1
values[54]	56	1			T428	2		T839	1		T840	1
values[55]	70	1			T428	2		T839	1		T840	1
values[56]	54	1			T428	3		T839	1		T840	1
values[57]	64	1			T428	2		T839	1		T840	1
values[58]	55	1			T428	1		T839	1		T840	1
values[59]	56	1			T428	2		T839	1		T840	1
values[60]	51	1			T428	1		T839	1		T840	1
values[61]	53	1			T428	1		T839	1		T840	1
values[62]	63	1			T428	5		T839	1		T840	1
values[63]	46	1			T428	1		T839	1		T840	1
values[64]	51	1			T428	2		T839	1		T840	1
values[65]	47	1			T428	3		T839	1		T840	1
values[66]	49	1			T428	3		T839	1		T840	1
values[67]	58	1			T428	2		T839	1		T840	1
values[68]	48	1			T428	1		T839	1		T840	1
values[69]	60	1			T428	3		T839	1		T840	1
values[70]	67	1			T428	4		T839	1		T840	1
values[71]	55	1			T428	1		T839	1		T840	1
values[72]	54	1			T428	4		T839	1		T840	1
values[73]	58	1			T428	6		T839	1		T840	1
values[74]	73	1			T428	2		T839	1		T840	1
values[75]	68	1			T428	3		T839	1		T840	1
values[76]	58	1			T428	1		T839	1		T840	1
values[77]	59	1			T428	2		T839	1		T840	1
values[78]	81	1			T428	4		T839	1		T840	1
values[79]	62	1			T428	2		T839	1		T840	1
values[80]	69	1			T428	1		T839	1		T840	1
values[81]	65	1			T428	4		T839	1		T840	2
values[82]	61	1			T428	4		T839	1		T840	1
values[83]	69	1			T428	3		T839	1		T840	1
values[84]	59	1			T428	1		T839	1		T840	1
values[85]	66	1			T428	1		T839	1		T840	2
values[86]	58	1			T428	2		T839	1		T840	1
values[87]	70	1			T428	1		T839	1		T840	1
values[88]	65	1			T428	1		T839	1		T840	1
values[89]	66	1			T428	4		T839	1		T840	1
values[90]	72	1			T428	1		T839	1		T840	1
values[91]	60	1			T428	2		T839	1		T840	1
values[92]	77	1			T428	2		T839	1		T840	1
values[93]	81	1			T428	4		T839	1		T840	1
values[94]	74	1			T428	1		T839	1		T840	1
values[95]	68	1			T428	4		T839	1		T840	1
values[96]	75	1			T428	6		T839	1		T840	1
values[97]	79	1			T428	4		T839	1		T840	1
values[98]	76	1			T428	3		T839	2		T840	1
values[99]	87	1			T428	2		T839	1		T840	1
values[100]	89	1			T428	1		T839	1		T840	1
values[101]	68	1			T428	1		T839	1		T840	1
values[102]	72	1			T428	3		T839	1		T840	2
values[103]	84	1			T428	3		T839	1		T840	4
values[104]	79	1			T428	3		T839	1		T840	1
values[105]	82	1			T428	3		T839	1		T840	1
values[106]	84	1			T428	3		T839	1		T840	1
values[107]	74	1			T428	2		T839	1		T840	2
values[108]	65	1			T428	1		T839	1		T840	4
values[109]	96	1			T428	1		T839	1		T840	7
values[110]	88	1			T428	4		T839	1		T840	5
values[111]	105	1			T428	8		T839	1		T840	3
values[112]	87	1			T428	2		T839	1		T840	2
values[113]	89	1			T428	4		T839	1		T840	4
values[114]	84	1			T428	7		T839	1		T840	3
values[115]	89	1			T428	1		T839	1		T840	3
values[116]	91	1			T428	4		T839	1		T840	2
values[117]	97	1			T428	4		T839	1		T840	1
values[118]	94	1			T428	2		T839	2		T840	3
values[119]	89	1			T428	2		T839	1		T840	1
values[120]	103	1			T428	5		T839	1		T840	1
values[121]	97	1			T428	5		T839	1		T840	1
values[122]	101	1			T428	4		T839	1		T840	3
values[123]	131	1			T428	13		T839	1		T840	8
values[124]	235	1			T428	18		T839	1		T840	1
values[125]	376	1			T428	53		T839	1		T840	3
values[126]	663	1			T428	63		T839	23		T840	6
values[127]	2527	1			T428	47		T839	130		T840	79
values[128]	4518	1			T428	1		T839	226		T840	204

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141392	1			T75	205		T76	49		T77	457
values[2]	10460	1			T75	1		T77	4		T456	1
values[3]	4484	1			T539	18		T501	21		T708	18
values[4]	2666	1			T539	18		T501	21		T708	23
values[5]	1676	1			T539	16		T501	18		T708	23
values[6]	1180	1			T539	16		T501	8		T708	26
values[7]	893	1			T539	10		T501	7		T708	15
values[8]	595	1			T539	11		T708	29		T841	1
values[9]	490	1			T539	7		T708	13		T841	5
values[10]	437	1			T539	6		T708	26		T841	3
values[11]	422	1			T539	3		T708	29		T841	2
values[12]	356	1			T539	5		T708	17		T841	7
values[13]	350	1			T539	5		T708	37		T841	8
values[14]	317	1			T539	4		T708	26		T841	7
values[15]	281	1			T539	9		T708	19		T841	6
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