Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143713	1			T75	197		T76	61		T77	463
values[2]	8974	1			T537	1		T438	1		T539	7
values[3]	4564	1			T544	2		T672	85		T685	2
values[4]	2670	1			T544	2		T672	52		T852	9
values[5]	1585	1			T544	9		T672	37		T852	16
values[6]	1234	1			T544	11		T672	38		T852	13
values[7]	999	1			T544	14		T672	15		T852	17
values[8]	812	1			T544	4		T672	7		T852	6
values[9]	735	1			T544	10		T852	14		T528	1
values[10]	692	1			T544	6		T852	15		T528	1
values[11]	639	1			T544	1		T852	9		T528	1
values[12]	603	1			T544	1		T852	7		T528	1
values[13]	521	1			T544	2		T852	16		T528	1
values[14]	647	1			T544	2		T852	13		T528	1
values[15]	637	1			T544	1		T852	10		T528	1
values[16]	542	1			T544	2		T852	10		T528	1
values[17]	654	1			T544	2		T852	6		T528	1
values[18]	579	1			T544	3		T852	7		T528	1
values[19]	517	1			T544	2		T852	14		T528	1
values[20]	506	1			T544	2		T852	9		T528	1
values[21]	526	1			T544	1		T852	10		T528	1
values[22]	515	1			T544	5		T852	10		T528	1
values[23]	524	1			T544	6		T852	15		T528	1
values[24]	488	1			T544	7		T852	11		T528	1
values[25]	473	1			T544	5		T852	12		T528	1
values[26]	508	1			T544	2		T852	12		T528	1
values[27]	561	1			T544	1		T852	7		T528	1
values[28]	504	1			T544	3		T852	4		T528	1
values[29]	457	1			T544	10		T852	5		T528	1
values[30]	446	1			T544	2		T852	6		T528	1
values[31]	429	1			T544	2		T852	6		T528	1
values[32]	414	1			T544	3		T852	6		T528	1
values[33]	419	1			T544	4		T852	38		T528	1
values[34]	349	1			T544	2		T852	5		T528	1
values[35]	422	1			T544	2		T852	10		T528	1
values[36]	468	1			T544	13		T852	5		T528	1
values[37]	381	1			T544	4		T852	3		T528	1
values[38]	462	1			T544	4		T852	6		T528	1
values[39]	382	1			T544	12		T852	15		T528	1
values[40]	354	1			T544	4		T852	7		T528	1
values[41]	375	1			T544	4		T852	19		T528	1
values[42]	377	1			T544	3		T852	5		T528	1
values[43]	417	1			T544	8		T852	9		T528	1
values[44]	350	1			T544	9		T852	8		T528	1
values[45]	320	1			T544	7		T852	7		T528	1
values[46]	313	1			T544	1		T852	6		T528	1
values[47]	296	1			T544	2		T852	6		T528	1
values[48]	257	1			T544	4		T852	15		T528	1
values[49]	240	1			T544	4		T852	5		T528	1
values[50]	194	1			T544	1		T852	12		T528	1
values[51]	200	1			T544	3		T852	18		T528	1
values[52]	237	1			T544	1		T852	8		T528	1
values[53]	204	1			T544	1		T852	13		T528	1
values[54]	122	1			T544	5		T852	10		T528	1
values[55]	138	1			T544	6		T852	12		T528	1
values[56]	128	1			T544	6		T852	8		T528	1
values[57]	97	1			T544	5		T852	2		T528	1
values[58]	108	1			T544	10		T528	1		T863	2
values[59]	93	1			T544	1		T528	1		T863	2
values[60]	79	1			T544	4		T528	1		T863	2
values[61]	77	1			T544	2		T528	1		T863	2
values[62]	102	1			T544	4		T528	1		T863	2
values[63]	82	1			T544	3		T528	1		T863	2
values[64]	90	1			T544	2		T528	1		T863	2
values[65]	95	1			T544	11		T528	1		T863	2
values[66]	100	1			T544	8		T528	1		T863	2
values[67]	123	1			T544	8		T528	1		T863	2
values[68]	143	1			T544	22		T528	1		T863	2
values[69]	128	1			T544	17		T528	1		T863	2
values[70]	95	1			T544	10		T528	1		T863	2
values[71]	77	1			T544	3		T528	1		T863	2
values[72]	92	1			T544	3		T528	1		T863	2
values[73]	77	1			T544	3		T528	1		T863	2
values[74]	87	1			T544	3		T528	1		T863	2
values[75]	82	1			T544	16		T528	1		T863	2
values[76]	110	1			T544	9		T528	1		T863	2
values[77]	90	1			T544	8		T528	1		T863	2
values[78]	102	1			T544	16		T528	1		T863	2
values[79]	139	1			T544	29		T528	1		T863	2
values[80]	117	1			T544	18		T528	1		T863	2
values[81]	107	1			T544	21		T528	1		T863	2
values[82]	80	1			T544	11		T528	1		T863	2
values[83]	91	1			T544	14		T528	1		T863	2
values[84]	108	1			T544	9		T528	1		T863	8
values[85]	115	1			T544	7		T528	1		T863	3
values[86]	104	1			T544	4		T528	1		T863	2
values[87]	96	1			T544	3		T528	1		T863	4
values[88]	87	1			T544	2		T528	2		T863	3
values[89]	90	1			T544	9		T528	1		T863	7
values[90]	92	1			T528	5		T863	2		T840	17
values[91]	72	1			T528	1		T863	3		T840	3
values[92]	70	1			T528	2		T863	2		T840	2
values[93]	87	1			T528	1		T863	3		T840	7
values[94]	72	1			T528	2		T863	3		T840	4
values[95]	73	1			T528	2		T863	5		T840	3
values[96]	72	1			T528	3		T863	9		T840	2
values[97]	85	1			T528	3		T863	4		T840	1
values[98]	79	1			T528	9		T863	2		T840	1
values[99]	79	1			T528	2		T863	2		T840	3
values[100]	80	1			T528	4		T863	4		T840	2
values[101]	69	1			T528	3		T863	3		T840	2
values[102]	87	1			T528	1		T863	5		T840	2
values[103]	81	1			T528	2		T863	5		T840	1
values[104]	74	1			T528	3		T863	3		T840	2
values[105]	74	1			T528	6		T863	2		T840	2
values[106]	78	1			T528	4		T863	3		T840	2
values[107]	69	1			T528	1		T863	6		T840	4
values[108]	67	1			T528	1		T863	6		T840	3
values[109]	67	1			T528	2		T863	5		T840	1
values[110]	65	1			T528	3		T863	7		T840	3
values[111]	61	1			T528	3		T863	4		T840	1
values[112]	64	1			T528	1		T863	2		T840	1
values[113]	68	1			T528	4		T863	3		T840	1
values[114]	60	1			T528	2		T863	4		T840	2
values[115]	72	1			T528	1		T863	4		T840	1
values[116]	71	1			T528	2		T863	2		T840	2
values[117]	67	1			T528	1		T863	4		T840	3
values[118]	61	1			T528	2		T863	3		T840	4
values[119]	57	1			T528	2		T863	2		T840	1
values[120]	44	1			T528	3		T863	6		T840	1
values[121]	50	1			T528	8		T863	3		T840	3
values[122]	56	1			T528	1		T863	4		T840	3
values[123]	62	1			T528	4		T863	5		T840	2
values[124]	58	1			T528	1		T863	4		T840	1
values[125]	61	1			T528	1		T863	4		T840	2
values[126]	137	1			T528	4		T863	5		T840	3
values[127]	1468	1			T528	58		T863	113		T840	44
values[128]	6680	1			T528	288		T863	470		T840	259