Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	462	1			T77	7		T599	2		T894	1
all_values[1]	454	1			T77	1		T599	1		T708	1
all_values[2]	465	1			T77	4		T599	1		T623	1
all_values[3]	459	1			T77	2		T540	1		T501	1
all_values[4]	486	1			T77	2		T544	1		T623	1
all_values[5]	470	1			T77	2		T599	1		T623	2
all_values[6]	499	1			T77	3		T544	1		T623	4
all_values[7]	437	1			T75	1		T77	1		T539	1
all_values[8]	466	1			T75	1		T77	4		T540	2
all_values[9]	468	1			T77	2		T599	2		T623	1
all_values[10]	462	1			T77	1		T501	1		T599	1
all_values[11]	526	1			T77	1		T708	1		T841	2
all_values[12]	457	1			T428	1		T708	1		T623	1
all_values[13]	504	1			T77	1		T540	1		T599	1
all_values[14]	460	1			T77	1		T599	1		T623	2
all_values[15]	476	1			T77	1		T539	1		T599	1
all_values[16]	453	1			T77	3		T428	1		T708	2
all_values[17]	452	1			T77	1		T245	1		T539	1
all_values[18]	483	1			T77	1		T599	1		T708	3
all_values[19]	516	1			T77	5		T599	1		T623	1
all_values[20]	455	1			T77	1		T539	2		T599	1
all_values[21]	499	1			T428	1		T623	3		T608	3
all_values[22]	466	1			T77	1		T540	1		T539	1
all_values[23]	461	1			T77	3		T599	2		T708	1
all_values[24]	442	1			T77	3		T428	1		T623	2
all_values[25]	465	1			T75	1		T77	2		T539	1
all_values[26]	500	1			T77	2		T623	1		T894	2
all_values[27]	491	1			T77	1		T540	1		T539	1
all_values[28]	502	1			T75	1		T77	2		T539	1
all_values[29]	453	1			T77	1		T539	1		T599	2
all_values[30]	493	1			T77	1		T540	1		T539	1
all_values[31]	479	1			T540	1		T539	1		T501	1
all_values[32]	471	1			T245	1		T599	1		T708	2
all_values[33]	472	1			T77	1		T428	1		T540	1
all_values[34]	465	1			T75	1		T428	1		T544	1
all_values[35]	485	1			T539	1		T599	1		T708	1
all_values[36]	475	1			T75	1		T77	2		T540	1
all_values[37]	502	1			T77	1		T539	1		T599	1
all_values[38]	489	1			T77	1		T428	1		T599	1
all_values[39]	428	1			T77	2		T540	1		T708	1
all_values[40]	468	1			T708	1		T623	2		T894	1
all_values[41]	473	1			T599	1		T708	1		T623	1
all_values[42]	478	1			T75	1		T77	1		T599	1
all_values[43]	495	1			T77	1		T539	2		T501	1
all_values[44]	433	1			T77	2		T599	1		T708	3
all_values[45]	475	1			T428	1		T623	1		T608	3
all_values[46]	526	1			T77	1		T501	1		T599	1
all_values[47]	475	1			T77	3		T540	1		T599	1
all_values[48]	464	1			T77	1		T428	1		T623	3
all_values[49]	435	1			T77	1		T599	1		T623	2