Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3520	1			T76	1		T77	14		T539	2
all_values[1]	3497	1			T75	3		T76	4		T77	19
all_values[2]	3543	1			T75	3		T76	4		T77	16
all_values[3]	3555	1			T75	1		T77	14		T454	2
all_values[4]	3542	1			T75	2		T76	2		T77	11
all_values[5]	3509	1			T75	3		T76	1		T77	12
all_values[6]	3448	1			T76	2		T77	15		T454	2
all_values[7]	3527	1			T75	3		T76	2		T77	12
all_values[8]	3480	1			T75	3		T76	2		T77	12
all_values[9]	3416	1			T75	1		T76	2		T77	17
all_values[10]	3559	1			T75	6		T76	2		T77	14
all_values[11]	3524	1			T75	2		T76	2		T77	16
all_values[12]	3531	1			T75	3		T77	19		T539	3
all_values[13]	3506	1			T75	1		T76	3		T77	11
all_values[14]	3449	1			T75	4		T77	14		T454	1
all_values[15]	3620	1			T75	3		T76	2		T77	11
all_values[16]	3432	1			T75	1		T76	1		T77	12
all_values[17]	3500	1			T75	4		T77	14		T454	1
all_values[18]	3599	1			T75	5		T76	2		T77	14
all_values[19]	3595	1			T76	1		T77	18		T454	3
all_values[20]	3613	1			T75	5		T76	1		T77	20
all_values[21]	3602	1			T75	2		T76	1		T77	15
all_values[22]	3641	1			T75	2		T76	1		T77	16
all_values[23]	3419	1			T75	2		T77	11		T539	2
all_values[24]	3597	1			T75	2		T76	4		T77	16
all_values[25]	3585	1			T75	3		T76	1		T77	13
all_values[26]	3561	1			T75	1		T77	11		T454	2
all_values[27]	3557	1			T75	3		T76	1		T77	10
all_values[28]	3453	1			T75	1		T76	1		T77	15
all_values[29]	3518	1			T75	3		T76	1		T77	13
all_values[30]	3451	1			T75	2		T76	2		T77	20
all_values[31]	3574	1			T75	5		T76	1		T77	10
all_values[32]	3632	1			T75	1		T76	2		T77	15
all_values[33]	3435	1			T75	3		T76	2		T77	18
all_values[34]	3493	1			T75	3		T76	1		T77	13
all_values[35]	3501	1			T75	2		T76	2		T77	11
all_values[36]	3540	1			T75	5		T76	2		T77	17
all_values[37]	3515	1			T75	2		T77	18		T454	1
all_values[38]	3489	1			T75	2		T76	1		T77	15
all_values[39]	3601	1			T75	5		T76	1		T77	13
all_values[40]	3482	1			T77	16		T454	1		T539	4
all_values[41]	3571	1			T75	1		T76	1		T77	17
all_values[42]	3470	1			T75	1		T76	2		T77	17
all_values[43]	3563	1			T75	4		T76	1		T77	13
all_values[44]	3559	1			T75	5		T76	5		T77	18
all_values[45]	3524	1			T75	3		T76	1		T77	12
all_values[46]	3461	1			T75	2		T76	2		T77	17
all_values[47]	3499	1			T75	4		T76	3		T77	15
all_values[48]	3523	1			T75	3		T76	1		T77	14
all_values[49]	3571	1			T75	3		T76	1		T77	17
all_values[50]	3451	1			T75	2		T76	3		T77	13
all_values[51]	3436	1			T77	8		T539	3		T501	5
all_values[52]	3514	1			T75	3		T77	19		T454	1
all_values[53]	3536	1			T75	3		T77	15		T539	1
all_values[54]	3671	1			T75	4		T76	2		T77	13
all_values[55]	3500	1			T75	4		T76	1		T77	14
all_values[56]	3449	1			T75	3		T76	3		T77	24
all_values[57]	3518	1			T75	5		T76	3		T77	9
all_values[58]	3566	1			T75	3		T77	13		T454	2
all_values[59]	3512	1			T75	2		T76	4		T77	21
all_values[60]	3540	1			T75	1		T76	1		T77	22
all_values[61]	3506	1			T75	3		T76	1		T77	17
all_values[62]	3581	1			T77	10		T454	1		T539	2
all_values[63]	3592	1			T75	4		T77	13		T454	1