Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	488	1			T217	4		T240	5		T423	1
all_values[1]	413	1			T240	3		T506	1		T510	1
all_values[2]	450	1			T217	2		T240	4		T423	1
all_values[3]	439	1			T217	3		T240	8		T404	2
all_values[4]	456	1			T217	1		T240	6		T423	2
all_values[5]	456	1			T217	3		T240	6		T510	2
all_values[6]	465	1			T217	2		T240	7		T507	1
all_values[7]	469	1			T217	7		T240	1		T507	1
all_values[8]	480	1			T217	2		T240	4		T404	6
all_values[9]	497	1			T217	4		T240	4		T423	1
all_values[10]	485	1			T79	1		T217	2		T240	3
all_values[11]	474	1			T217	1		T240	7		T507	1
all_values[12]	458	1			T217	2		T240	5		T507	2
all_values[13]	449	1			T217	1		T240	4		T506	1
all_values[14]	466	1			T217	2		T240	4		T404	1
all_values[15]	502	1			T240	4		T507	1		T423	1
all_values[16]	468	1			T217	1		T240	5		T515	1
all_values[17]	473	1			T217	1		T240	3		T404	5
all_values[18]	458	1			T217	1		T240	8		T506	1
all_values[19]	455	1			T217	3		T240	9		T507	1
all_values[20]	461	1			T217	1		T240	2		T423	1
all_values[21]	458	1			T217	1		T240	6		T404	2
all_values[22]	459	1			T217	1		T240	4		T506	1
all_values[23]	436	1			T217	2		T240	5		T507	1
all_values[24]	457	1			T217	2		T240	10		T423	1
all_values[25]	494	1			T217	2		T240	4		T404	1
all_values[26]	478	1			T217	2		T240	7		T404	2
all_values[27]	460	1			T217	2		T240	4		T404	2
all_values[28]	445	1			T217	4		T240	4		T432	1
all_values[29]	427	1			T217	2		T240	2		T241	1
all_values[30]	456	1			T217	3		T240	3		T404	1
all_values[31]	430	1			T217	1		T240	1		T241	1
all_values[32]	445	1			T79	1		T217	2		T240	7
all_values[33]	458	1			T217	7		T240	3		T506	1
all_values[34]	449	1			T217	5		T240	4		T404	2
all_values[35]	454	1			T217	3		T240	2		T423	2
all_values[36]	465	1			T217	3		T240	4		T510	1
all_values[37]	465	1			T217	1		T240	3		T241	1
all_values[38]	476	1			T217	5		T240	8		T404	1
all_values[39]	471	1			T217	3		T240	6		T507	1
all_values[40]	435	1			T240	5		T423	2		T404	1
all_values[41]	467	1			T217	1		T240	5		T506	1
all_values[42]	456	1			T217	4		T240	9		T506	1
all_values[43]	461	1			T217	4		T240	1		T423	1
all_values[44]	470	1			T217	1		T240	5		T404	4
all_values[45]	434	1			T240	7		T423	1		T404	2
all_values[46]	445	1			T240	5		T423	1		T404	3
all_values[47]	474	1			T217	2		T240	5		T423	1
all_values[48]	472	1			T217	1		T240	4		T404	4
all_values[49]	449	1			T79	1		T217	3		T240	2